AD1954 AD | Alldatasheet
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Technical content
Information furnished by Analog Devices is be lieved to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or other- wise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD1954 SigmaDSP™ 3-Channel, 26-Bit Signal Processing DAC
FEATURES
5 V 3-Channel Audio DAC System
Accepts Sample Rates up to 48 kHz
7 Biquad Filter Sections per Channel
Dual Dynamic Processor with Arbitrary Input/Output Curve and Adjustable Time Constants 0 ms to 6 ms Variable Delay/Channel for Speaker Alignment Stereo Spreading Algorithm for Phat Stereo™ Effect Program RAM Allows Complete New Program Download via SPI Port Parameter RAM Allows Complete Control of More Than
200 Parameters via SPI Port
SPI Port Features Safe-Upload Mode for T ransparent Filter Updates
2 Control Registers Allow Complete Control of Modes and
Differential Output for Optimum Performance 112 dB Signal-to-Noise (Not Muted) at 48 kHz Sample Rate (A-Weighted Stereo) 70 dB Stop-Band Attenuation On-Chip Clickless Volume Control Hardware and Software Controllable Clickless Mute Digital De-emphasis Processing for 32 kHz, 44.1 kHz, and 48 kHz Sample Rates Flexible Serial Data Port with Right-Justifi ed, Left-Justifi ed, I2S Compatible, and DSP Serial Port Modes Auxiliary Digital Input FUNCTIONAL BLOCK DIAGRAM SERIAL CONTROL INTERFACE MCLK MUX MCLK GENERATOR (256fS/512fS) DAC – L DAC – R DAC – SW DAT A CAPTURE OUT AUDIO DAT A MUX 26 22 DSP CORE DAT A FORMA T: 3.23 (SINGLE PRECISION) 3.45 (DOUBLE PRECISION) RAM ROM ANALOG OUTPUTS AD1954 MASTER CLOCK OUTPUT SERIAL DAT A INPUTS MASTER CLOCK INPUTS SERIAL DAT A OUTPUT SPI INPUT SPI DAT A OUTPUT AUX SERIAL DAT A INPUT DIGITAL OUTPUT Graphical Custom Programming T ools 44-Lead MQFP or 48-Lead LQFP Plastic Package
APPLICATIONS
2.0/2.1 Channel Audio Systems (T wo Main Channels plus Subwoofer) Multimedia Audio Automotive Sound Systems Minicomponent Stereo Home Theater Systems (AC-3 Postprocessor) Musical Instruments In-Seat Sound Systems (Aircraft, Motor Coaches) GENERAL DESCRIPTION The AD1954 is a complete 26-bit single-chip 3-channel digital audio playback system with built-in DSP functionality for speaker equalization, dual-band compression/limiting, delay compensa- tion, and image enhancement. These algorithms can be used to compensate for real-world limitations of speakers, amplifi ers, and listening environments, resulting in a dramatic improvement of perceived audio quality. The signal processing used in the AD1954 is comparable to that found in high-end studio equipment. Most of the processing is done in full 48-bit double-precision mode, resulting in very good low-level signal performance and the absence of limit cycles or idle tones. The compressor/limiter uses a sophisticated two-band algorithm often found in high-end broadcast compressors. (Continued on 9) REV. A
–2– TABLE OF CONTENTS Using the Sub Reinjection Paths for Systems with Cookbook Formulae for Audio EQ Biquad Coeffi cients . . .32 REV. A
–3– AD1954–SPECIFICATIONS Test conditions, unless otherwise noted. Supply Voltages (AVDD, DVDD) 5.0 V Ambient Temperature 25°C Input Clock 12.288 MHz Input Signal 1.000 kHz 0 dB Full Scale Input Sample Rate 48 kHz Measurement Bandwidth 20 Hz to 20 kHz Word Width 24 Bits Load Capacitance 2200 pF Load Impedance 2.74 k Input Voltage High 2.1 V Input Voltage Low 0.8 V ANALOG PERFORMANCE* Parameter Min T yp Max Unit RESOLUTION 24 Bits SIGNAL-TO-NOISE RATIO (20 Hz to 20 kHz) (Left/Right Output) No Filter (Stereo) 109 dB With A-Weighted Filter 112 dB DYNAMIC RANGE (20 Hz to 20 kHz, –60 dB Input) (Left/Right Output) No Filter 109 dB With A-Weighted Filter 108 112 dB TOTAL HARMONIC DISTORTION PLUS NOISE (Left/Right Output) VO = –0.5 dB –93 –100 dB SIGNAL-TO-NOISE RATIO (20 Hz to 20 kHz) (Subwoofer Output) No Filter (Stereo) 104 dB With A-Weighted Filter 107 dB DYNAMIC RANGE (20 Hz to 20 kHz, –60 dB Input) (Subwoofer Output) No Filter 104 dB With A-Weighted Filter 104 107 dB TOTAL HARMONIC DISTORTION PLUS NOISE (Subwoofer Output) VO = –0.5 dB –90 –96 dB ANALOG OUTPUTS Differential Output Range (± Full Scale) (Left/Right Output) 2.74 V p-p Differential Output Range (± Full Scale) (Subwoofer Output) 2.77 V p-p CMOUT 2.50 V DC ACCURACY Gain Error (Left/Right Channel) –5 +5 % Gain Error (Subwoofer Channel) –8 +8 % Interchannel Gain Mismatch –0.250 +0.250 dB Gain Drift 150 ppm/°C DC Offset –30 +30 mV INTERCHANNEL CROSSTALK (EIAJ Method) –120 dB INTERCHANNEL PHASE DEVIATION ±0.1 Degrees MUTE ATTENUATION –107 dB DE-EMPHASIS GAIN ERROR ±0.1 dB *Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifi cations). Specifi cations subject to change without notice. REV. A
–4– AD1954 SPECIFICATIONS (continued) DIGITAL I/O Parameter Min T yp Max Unit Input Voltage High (VIH) 2.1 V Input Voltage High (VIH) – RESETB 2.25 V Input Voltage Low (VIL) 0.8 V Input Leakage (IIH @ VIH = 2.1 V) 10 µA Input Leakage (IIL @ VIL @ VIL IL = 0.8 V)IL = 0.8 V)IL 10 µA High Level Output Voltage (VOH), IOH = 2 mA DVDD – 0.5 V Low Level Output Voltage (VOL), IOL = 2 mAOL = 2 mAOL 0.4 V Input Capacitance 20 pF Specifi cations subject to change without notice. POWER Parameter Min T yp Max Unit SUPPLIES* Voltage, Analog and Digital 4.5 5 5.5 V Analog Current 42 48 mA Analog Current, Power-Down 40 46 mA Digital Current 65 75 mA Digital Current, SPI Power-Down 6 10 mA Digital Current, Reset Power-Down 53 61 mA DISSIPATION Operation, Both Supplies 510 mW Operation, Analog Supplies 210 mW Operation, Digital Supplies 325 mW SPI Power-Down, Both Supplies 230 mW Reset Power-Down, Both Supplies 465 mW POWER SUPPLY REJECTION RATIO 1 kHz 300 mV p-p Signal at Analog Supply Pins –80 dB 20 kHz 300 mV p-p Signal at Analog Supply Pins –80 dB *ODVDD current is dependent on load capacitance and clock rate. Specifi cations subject to change without notice. TEMPERATURE RANGE Parameter Min T yp Max Unit Specifi cations Guaranteed 25 °C Functionality Guaranteed –40 +105 °C Storage –55 +125 °C Specifi cations subject to change without notice. REV. A
–5– DIGITAL TIMING Parameter Min T yp Max Unit tDMDC MCLK Recommended Duty Cycle @ 12.288 MHz (256 fSMCLK Recommended Duty Cycle @ 12.288 MHz (256 fSMCLK Recommended Duty Cycle @ 12.288 MHz (256 f Mode) 45 55 % tDMDC MCLK Recommended Duty Cycle @ 24.576 MHz (512 fSMCLK Recommended Duty Cycle @ 24.576 MHz (512 fSMCLK Recommended Duty Cycle @ 24.576 MHz (512 f Mode) 40 60 % tDMD MCLK Delay (All Mode) 25 ns tDBH BCLK Low Pulsewidth 10 ns tDBH BCLK High Pulsewidth 10 ns tDBD BCLK Delay (to BCLKO) 25 ns tDLS LRCLK Setup 0 ns tDLH LRCLK Hold 10 ns tDLD LRCLK Delay (to LRCLKO) 25 ns tDDS SDATA Setup 0 ns tDDH SDATA Hold 10 ns tDDD SDATA Delay (to SDATAO) 25 ns tCCL CCLK Low Pulsewidth 12 ns tCCH CCLK High Pulsewidth 12 ns tCLS CLATCH Setup 10 ns tCLH CLATCH Hold 10 ns tCLD CLATCH High Pulsewidth 10 ns tCDS CDATA Setup 0 ns tCDH CDATA Hold 10 ns tCOD COUT Delay 35 ns tCOH COUT Hold 2 ns tDCD DCSOUT Delay 35 ns tDCH DCSOUT Hold 2 ns tPDRP PD/RST Low Pulsewidth 5 ns Specifi cations subject to change without notice. DIGITAL FILTER CHARACTERISTICS AT 44.1 KHZ Parameter Min T yp Max Unit Pass-Band Ripple ±0.01 dB Stop-Band Attenuation 70 dB Pass Band 20 kHz 0.5442 fS fS f Stop Band 24 kHz 0.4535 fSfSf Group Delay 24.625/fS24.625/fS24.625/f sec Specifi cations subject to change without notice. REV. A
–6– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily ac cu mu late on the human body and test equipment and can discharge without detection. Although the AD1954 features proprietary ESD pro tec tion circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD pre cau tions are rec om mend ed to avoid per for mance deg ra da tion or loss of functionality. ABSOLUTE MAXIMUM RATINGS* *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifi cation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN CONFIGURATIONS 44-LEAD MQFP 40 39 3841424344 36 35 3437 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) 12 13 14 15 16 17 18 19 20 21 22 RESETB AVDD AGND AGND VOUTL– VOUTL+ AVDD AGND AVDD VOUTR+ AD1954 CDATA LRCLK1 SDATA0 BCLK0 LRCKL0 CCLK MCLK2 MCLK1 MCLK0 DEEMP/SDATA_AUX MUTE DVDD SDATA2 BCLK2 LRCLK2 SDATA1 BCLK1 VOUTR– AGND VOUTS+ VOUTS– CLATCH DGND COUT ODVDD BCLKOUT MCLKOUT DCSOUT LRCLKOUT SDATAOUT ZEROFLAG FILTCAP VREF DGND 48-LEAD LQFP 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 39 38 3743 42 41 40 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) NC AGND VOUTL– VOUTL+ AVDD AGND AVDD NC MCLK2 MCLK1 MCLK0 DEEMP/SDATA_AUX MUTE DVDD NC = NO CONNECT SDATA2 BCLK2 LRCLK2 SDATA1 VOUTR+ VOUTR– AGND VOUTS+ AD1954 BCLK1 VOUTS– DGND MCLKOUT COUT DCSOUT ODVDD LRCLKOUT BCLKOUT SDATAOUT ZEROFLAG FILTERCAP VREF NC DGND LRCLK1 SDATA0 BCLK0 LRCLK0 CDATA CCLK CLATCH RESETB AVDD AGND NC Package Characteristics (44-Lead MQFP) Min T yp Max Unit JA (Thermal Resistance— Junction to Ambient) 72 °C/W JC (Thermal Resistance— Junction to Ambient) 19.5 °C/W Package Characteristics (48-Lead LQFP) Min T yp Max Unit JA (Thermal Resistance— Junction to Ambient) 76 °C/W JC (Thermal Resistance— Junction to Ambient) 17 °C/W ORDERING GUIDE Model Temperature Range Package Description Package Option AD1954YS –40°C to +105°C 44-Lead MQFP S-44 AD1954YSRL –40°C to +105°C 44-Lead MQFP S-44 on 13" Reel AD1954YST –40°C to +105°C 48-Lead LQFP ST -48 AD1954YSTRL –40°C to +105°C 48-Lead LQFP ST -48 on 13" Reel AD1954YSTRL7 –40°C to +105°C 48-Lead LQFP ST -48 on 7" Reel EVAL-AD1954EB Evaluation Board REV. A
–7– PIN FUNCTION DESCRIPTIONS Pin No. Pin No. Input/ (44-MQFP) (48-LQFP) Mnemonic Output Description*
1 NC No Connect
1 2 MCLK2 IN Master Clock Input 2 256 fSMaster Clock Input 2 256 fSMaster Clock Input 2 256 f /512 fS/512 fS/512 f 2 3 MCLK1 IN Master Clock Input 1 256 fSMaster Clock Input 1 256 fSMaster Clock Input 1 256 f /512 fS/512 fS/512 f 3 4 MCLK0 IN Master Clock Input 0 256 fSMaster Clock Input 0 256 fSMaster Clock Input 0 256 f /512 fS/512 fS/512 f 4 5 DEEMP/ IN Enables 44.1 kHz De-emphasis Filter (Others Available through SPI Control) SDATA_AUX Auxiliary Serial Data Input 5 6 MUTE IN Mute Signal. Initiates volume ramp-down. 6 7 DVDD Digital Supply for DSP Core, 4.5 V to 5.5 V 7 8 SDATA2 IN Serial Data Input 2 8 9 BCLK2 IN Bit Clock 2 9 10 LRCLK2 IN Left/Right Clock 2 10 11 SDATA1 IN Serial Data Input 1 11 12 BCLK1 IN Bit Clock 1 12 13 DGND Digital Ground 13 14 LRCLK1 IN Left/Right Clock 1 14 15 SDATA0 IN Serial Data Input 0 15 16 BCLK0 IN Bit Clock 0 16 17 LRCLK0 IN Left/Right Clock 0 17 18 CDATA IN SPI Data Input 18 19 CCLK IN SPI Data Bit Clock 19 20 CLATCH IN SPI Data Framing Signal 20 21 RESETB IN Reset Signal, Active Low 21 22 AVDD Analog 5 V Supply 22 23 AGND Analog GND
24 NC No Connect
23 25 VOUTS– OUT Negative Sub Analog DAC Output 24 26 VOUTS+ OUT Positive Sub Analog DAC Output 25 27 AGND Analog GND 26 28 VOUTR– OUT Negative Left Analog DAC Output 27 29 VOUTR+ OUT Positive Left Analog DAC Output 28 30 AVDD Analog 5 V Supply 29 31 AGND Analog GND 30 32 AVDD Analog 5 V Supply 31 33 VOUTL+ OUT Positive Left Analog DAC Output 32 34 VOUTL– OUT Negative Left Analog DAC Output 33 35 AGND Analog GND
36 NC No Connect
37 NC No Connect
34 38 VREF IN Connection for Filtered AVDD/2 35 39 FILTCAP IN Connection for Noise Reduction Capacitor 36 40 ZEROFLAG OUT Zero Flag Output. High when both left and right channels are 0 for 1024 frames. 37 41 SDATAOUT OUT Serial Data Mux Output 38 42 BCLKOUT OUT Bit Clock Mux Output 39 43 LRCLKOUT OUT Left/Right Clock Mux Output 40 44 ODVDD Digital Supply Pin for Output Drivers, 2.5 V to 5.5 V 41 45 DCSOUT OUT Data Capture Serial Output for Data Capture Registers. Use in conjunction with selected LRCLK and BCLK to form a 3-wire output. 42 46 COUT OUT SPI Data Output. Three-stated when inactive. 43 47 MCLKOUT OUT Master Clock Output 512 fSMaster Clock Output 512 fSMaster Clock Output 512 f /256 fS/256 fS/256 f (Frequency Selected by SPI Register) 44 48 DGND Digital Ground *For a complete description of the pins, refer to the Pin Functions section. REV. A
–8– AD1954–Typical Performance Characteristics –160 0 202 4 6 8 14 16 18 –20 –80 –120 –40 –60 –100 –140 10 12 kHz dB TPC 1. FFT of Full-Scale Sine Wave (32k Points) –160 0 202 4 6 8 14 16 18 –20 –80 –120 –40 –60 –100 –140 10 12 kHz dB TPC 2. FFT of –60 dB Sine Wave (32k Points) Hz –20 20 10k –10 1k100 –12 –14 –16 –18 50 200 500 5k dB TPC 3. Frequency Response of EQ Biquad Filters 3.0 –3.0 –120 0–100 –80 –20 0.5 –1.0 –2.0 –0.5 –1.5 –2.5 –60 –40 dBFS 2.5 1.5 2.0 1.0 dB TPC 4. Linearity Plot –2.0 ms –1.5 –1.0 –0.5 0.5 1.0 1.5 2.0 V TPC 5. Tone-Burst Response with Compressor Threshold Set to –20 dB PERFORMANCE PLOTS The following plots demonstrate the performance achieved on the actual silicon. TPC 1 shows an FFT of a full-scale 1 kHz signal, with a THD+N of –100 dB, which is dominated by a second har monic. TPC 2 shows an FFT of a –60 dB sine wave, demon- strating the lack of low-level artifacts. TPC 3 shows a frequency response plot with the seven equalization biquads set to an alter- nating pattern of 6 dB boosts and cuts. TPC 4 shows a linearity plot, where the measurement was taken with the same equalization curve used to make TPC 3. When the biquad fi lters are not in use, the signal passes through the fi lters with no quantization effects. TPC 4 therefore demonstrates that using double-precision math in the biquad fi lters has virtually eliminated any quantization artifacts. TPC 5 shows a tone-burst applied to the compressor, with the attack and recovery characteristics plainly visible. The rms detector was programmed for normal rms time constants; the hold/decay feature was not used for this plot. REV. A
–10– The AD1954 has a very fl exible serial data input port, which allows for glueless interconnection to a variety of ADCs, DSP chips, AES/EBU receivers, and sample rate converters. The AD1954 can be confi gured in left-justifi ed, I2S, right-justifi ed, or DSP serial port compatible modes. It can support 16 bits, 20 bits, and 24 bits in all modes. The AD1954 accepts serial audio data in MSB fi rst, twos complement format. The part can also be set up in a 4-channel serial input mode by simultaneously using the serial input mux and the auxiliary serial input. The AD1954 operates from a single 5 V power supply. It is fabri- cated on a single monolithic integrated circuit and is housed in a 44-lead MQFP or 48-lead LQFP package for operation over the temperature range –40°C to +105°C. PIN FUNCTIONS All input pins have a logic threshold compatible with TTL input levels and can therefore be used in systems with 3.3 V logic. All digital output levels are controlled by the ODVDD pin, which may range from 2.7 V to 5.5 V, for compatibility with a wide range of external devices. (See Pin Function Descriptions table.) SDATA0, SDATA1, SDATA2—Serial Data Inputs One of these three inputs is selected by an internal mux, set by writing to Bits 7 and 6 in Control Register 2. Default is 00, which selects SDATA0. The serial format is selected by writing to Bits 3–0 of Control Register 0. See SPI Read/Write Data Formats section for recommendations on how to change input sources without causing a click or pop noise. LRCLK0, LRCLK1, LRCLK2—Left/Right Clocks for Framing the Input Data The active LRCLK input is selected by writing to Bits 7 and 6 in Control Register 2. The default is 00, which selects LRCLK0. The interpretation of the LRCLK changes according to the serial mode, set by writing to Control Register 0. BCLK0, BCLK1, BCLK2—Serial Bit Clocks for Clocking in the Serial Data The active BCLK input is selected by writing to Bits 7 and 6 in Control Register 2. Default is 00, which selects BCLK0. The interpretation of BCLK changes according to the serial mode, which is set by writing to Control Register 0. LRCLKOUT, BCLKOUT, SDATAOUT—Output of Mux that Selects One of the Three Serial Input Groups These pins may be used to send the selected serial input signals to other external devices. This output pin is enabled by writing a 1 to Bit 8 of Control Register 2. The default mode is 0 or Off. MCLK0, MCLK1, MCLK2—Master Clock Inputs Active input selected by writing to Bits 5 and 4 of Control Regis- ter 2. The default is 00, which selects MCLK0. The master clock frequency must be either 256 fS fS f or 512 fS fS f , where fS, where fS, where f is the input sampling rate. The master clock frequency is programmed by writing to Bit 2 of Control Register 2. The default is 0 (512 fS fS f ). See the Initialization section for recommendations concerning how to change clock sources without causing an audio click or pop. Note that since the default MCLK source pin is MCLK0, there must be a clock signal present on this pin on power-up so that the AD1954 can complete its initialization routine. MCLKOUT—Master Clock Output The master clock output pin may be programmed to produce either 256 fS fS f , 512 fS fS f , or a copy of the selected MCLK input pin. This pin is programmed by writing to Bits 1 and 0 of Control Register 2. The default is 00, which disables the MCLKO pin. CDATA—Serial Data In for the SPI Control Port See SPI Port section for more information on SPI port timing. COUT—Serial Data Output This is used for reading back registers and memory locations. It is three-stated when an SPI read is not active. See SPI Port section for more information on SPI port timing. CCLK—SPI Bit Rate ClockCCLK—SPI Bit Rate ClockCCLK This pin either may run continuously or be gated off in between SPI transactions. See SPI Port section for more information on SPI port timing. CLATCH—SPI Latch Signal It must go low at the beginning of an SPI transaction and high at the end of a transaction. Each SPI transaction may take a different number of CCLKs to complete, depending on the address and read/write bit that are sent at the beginning of the SPI transaction. Detailed SPI timing information is given in SPI Port section. RESETB—Active Low Reset Signal After RESETB goes high, the AD1954 goes through an initial- ization sequence where the program and parameter RAMs are initialized with the contents of the on-board boot ROMs. All SPI registers are set to 0, and the data RAMs are also zeroed. The initialization is complete after 1024 MCLK cycles. Since the MCLK IN FREQ SELECT (Bit 2 in Control Register 2) defaults to 512 fS fS f at power-up, this initialization will proceed at the external MCLK rate and will take 1024 MCLK cycles to com- plete, regardless of the absolute frequency of the external MCLK. New values should not be written to the SPI port until the initial- ization is complete. ZEROFLAG—Zero-Input Indicator This pin will go high if both serial inputs have been inactive (zero data) for 1024 LRCLK cycles. This pin may be used to drive an external mute FET for reduced noise during digital silence. This pin also functions as a test out pin, controlled by the test register at SPI Address 511. While most Test Modes are not useful to the end user, one may be of some use. If the Test Register is pro- grammed with the number 7 (decimal), the ZEROFLAG output will be switched to the output of the internal pseudo-random noise generator. This noise generator operates at a bit rate of 128 fS fS f and has a repeat time of once per 224 cycles. This mode may be used to generate white noise (or, with appropriate fi ltering, pink noise) to be used as a test signal for measuring speakers or room acoustics. REV. A
–1 1– DCSOUT—Data Capture Serial Out This pin will output the DSP’s internal signals, which can be used by external DACs or other signal processing devices. The signals that are captured and output on the DCSOUT pin are controlled by writing program counter trap numbers to SPI Addresses 263 (for the left output) and 264 (for the right output). When the inter- nal program counter contents are equal to the trap values written to the SPI port, the selected DSP register is transferred to the DCSOUT parallel-to-serial registers and shifted out on the DCSOUT pin. Table XX shows the program counter trap values and register-select values that should be used to tap various inter- nal points of the algorithm fl ow. The DCSOUT pin is meant to be used in conjunction with the LRCLK and BCLK signals that are provided to the serial input port. The format of DCSOUT is the same as the format used for the serial port. In other words, if the serial port is running in I2S mode, then the DCSOUT pin, together with the LRCLK0 and BCLK0 pins (assuming input 0 is selected), will form a valid 3-wire I2S output. The DCSOUT pin can be used for a variety of purposes. If the DCSOUT pin is used to drive another external DAC, then a 4.1 system is possible using a new program downloaded into the program RAM. DEEMP/SDATA_AUX—De-emphasis Input Pin/Auxiliary Serial DEEMP/SDATA_AUX—De-emphasis Input Pin/Auxiliary Serial DEEMP/SDATA_AUX Data Input In de-emphasis mode, if this pin is asserted high, then a digital de-emphasis fi lter will be inserted into the signal fl ow. The de-emphasis curve is valid only for a sample rate of 44.1 kHz; curves for 32 kHz and 48 kHz may be programmed using the SPI port. This pin can also be used as an auxiliary 2-channel serial data input. This function is set by writing a 1 to Bit 11 of Control Register 1. The same clocks are used for this serial input as are used for the SDATA0, SDATA1, and SDATA2 signals. This serial input can only be used in the signal processing fl ow when using Analog Devices’ custom programming tools; see the Graphical Custom Programming Tools section. The use of de-emphasis is still available while this pin is used as a serial input but only through SPI control. MUTE—Mute Output Signal When this pin is asserted high, a ramp sequence is started, which gradually reduces the volume to zero. When de-asserted, the volume ramps from zero back to the original volume setting. The ramp speed is timed so that it takes 10 ms to reach 0 volume when starting from the default 0 dB volume setting. VOUTL+, VOUTL2—Left Channel Differential Analog Outputs Full-scale outputs correspond to 1 Vrms on each output pin or 2 V rms differential, assuming a VREF input voltage of 2.5 V . The full-scale swing scales directly with VREF. These outputs are capable of driving a load of >5 k, with a maximum peak current of 1 mA from each pin. An external third order fi lter is recom- mended for fi ltering out-of-band noise. VOUTR+, VOUTR2 —Right Channel Differential Outputs See characteristics for left channel VOUTL+, VOUTL–. VOUTS+, VOUTS2—Subchannel Differential Outputs These outputs are designed to drive loads of 10 k or greater, with a peak current capability of 250 µA. This output does not use digital interpolation, since it is intended for low frequency applications. An external third order fi lter with a cutoff frequency <2 kHz is recommended. VREF—Analog Reference Voltage Input The nominal VREF input voltage is 2.5 V; the analog gain scales directly with the voltage on this pin. When using the AD1954 to drive a power amplifi er, it is recommended that the VREF voltage be derived by dividing down and heavily fi ltering the supply to the power amplifi er. This provides a benefi t if the compressor/limiter in the AD1954 is used to prevent amplifi er clipping. In this case, if the DAC output voltage is scaled to the amplifi er power supply, a fi xed compressor threshold can be used to protect an amplifi er whose supply may vary over a wide range. Any ac signal on this pin will cause distortion, and therefore, a large decoupling capaci- tor may be necessary to ensure that the voltage on VREF is clean. The input impedance of VREF is greater than 1 M. FILTCAP—Filter Capacitor Point This pin is used to reduce the noise on an internal biasing point in order to provide the highest performance. It may not be neces- sary to connect this pin, depending on the quality of the layout and the grounding used in the application circuit. DVDD—Digital VDD for Core 5 V nominal. ODVDD—Digital VDD for All Digital Outputs Variable from 2.7 V to 5.5 V . DGND (2)—Digital Ground AVDD (3)—Analog VDD 5 V nominal. For best results, use a separate regulator for AVDD. Bypass capacitors should be placed close to the pins and connected directly to the analog ground plane. AGND (3)—Analog Ground For best performance, separate nonoverlapping analog and digital ground planes should be used. REV. A
Figure 2 shows the signal processing fl ow diagram of the AD1954. algorithm that increases the perceived spread of the stereo image. to be inserted at various places in the signal path. signal back up at the end of the biquad fi lter section.
1 BIQUAD
7 BIQUAD
Figure 2. Signal Processing Flow
maximized under all conditions. This is illustrated in Figure 15. Figure 15. Optimizing Woofer Loudness Using the writing to Bits 5 and 4 of Control Register 1 over the SPI port. with CD decoder chips that have a de-emphasis output pin. priate set of crossover fi lters. the subwoofer path or the main left/right path.
–20– Table II. SPI Port Address Decoding SPI Address Register Name Read/Write Word Length 0–255 Parameter RAM Write: 22 Bits Read: 22 Bits
256 SPI Control Register 1 Write: 11 Bits
Read: 2 Bits
257 SPI Control Register 2 Write: 9 Bits
Read: N/A
258 Volume Left Write: 22 Bits
Read: N/A
259 Volume Right Write: 22 Bits
Read: N/A
260 Volume Sub Write: 22 Bits
Read: N/A
261 Data Capture (SPI Out) #1 Write: 9-Bit Program Counter Value, 2-Bit Register Address
Read: 24 Bits
262 Data Capture (SPI Out) #2 Write: 9-Bit Program Counter Value, 2-Bit Register Address
Read: 24 Bits
263 Data Capture (Serial Out) Left Write: 9-Bit Program Counter Value, 2-Bit Register Address
Read: N/A
264 Data Capture (Serial Out) Right Write: 9-Bit Program Counter Value, 2-Bit Register Address
Read: N/A
265 Parameter RAM Safe Load Register 0 Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Read: N/A
266 Parameter RAM Safe Load Register 1 Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Read: N/A
267 Parameter RAM Safe Load Register 2 Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Read: N/A
268 Parameter RAM Safe Load Register 3 Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Read: N/A
269 Parameter RAM Safe Load Register 4 Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Read: N/A 270–510 Unused
511 Test Register Write: 8 Bits
Read: N/A 512–1024 Program RAM Write: 35 Bits Read: 35 Bits SPI Address Decoding Table II shows the address decoding used in the SPI port. The SPI address space encompasses a set a registers and two RAMs, one for holding signal processing parameters and one for hold- ing the program instructions. Both of the RAMs are loaded on power-up from on-board boot ROMs. Control Register 1 Control Register 1 is an 11-bit register that controls data capture, serial modes, de-emphasis, mute, power-down, and SPI-to- memory transfers. T able III documents the contents of this register. Table IV details the two bits in the register’s read operation. Bits 1:0 set the word length, which is used in right-justifi ed serial modes to determine where the MSB is located relative to the start of the audio frame. Bits 3:2 select one of four serial modes, which are discussed in the Serial Data Input Port section. The de-emphasis curve selection Bits 5:4 turn on the internal de-emphasis fi lter for one of three possible sample rates. Bit 6, the soft power-down bit, stops the internal clocks to the DSP core, but does not reset the part. The digital power consumption is reduced to a low level when this bit is asserted. Reset can only be asserted using the external reset pin. Soft mute (Bit 7) is used to initiate a volume ramp-down sequence. If the initial volume was set to 1.0, this operation will take 512 audio frames to complete. When this bit is de-asserted, a ramp-up sequence is initiated until the volume returns to its original setting. When set, Bit 8 enables the DCSOUT pin. This must be set in order to read from the data capture serial out registers. REV. A
–21– The initiate-safe-transfer Bit 9 will request a data transfer from the SPI safeload registers to the parameter RAM. The safeload registers contain address-data pairs, and only those registers that have been written to since the last transfer operation will be uploaded. The user may poll for this operation to complete by reading Bit 0 of Control Register 1. The Safeload Mechanism section goes into more detail on this feature. Bit 10, the halt program bit, is used to initiate a volume ramp-down followed by a shutdown of the DSP core. The user may poll for this operation to complete by reading Bit 1 of Control Register 1. Bit 11 sets the function of the de-emphasis/auxiliary serial input pin. When this bit is set to 1, the pin will function as an auxiliary serial input that is clocked by the input mux’s selected clocks. When set to 0, this pin enables the 44.1 kHz de-emphasis curve. Table III. Control Register 1 Write Defi nition Register Bits Function
11 De-emphasis/Auxiliary Serial Input Pin Select
(1 = Auxiliary Serial Input)
10 Halt Program (1 = Halt)
9 Initiate Safe Transfer (1 = Transfer)
8 Enable DCSOUT Output Pin (1 = Enable)
7 Soft Mute (1 = Start Mute Sequence)
6 Soft Power-Down (1 = Power-Down)
5:4 De-emphasis Curve Select 00 = None 01 = 44.1 kHz 10 = 32 kHz 11 = 48 kHz 3:2 Serial in Mode 00 = I2S 01 = Right-Justifi ed 10 = DSP 11 = Left-Justifi ed 1:0 Word Length 00 = 24 Bits 01 = 20 Bits 10 = 16 Bits 11 = 16 Bits Table IV . Control Register 1 Read Defi nition Register Bits Function
1 DSP Core Shutdown Complete
1 = Shutdown Complete 0 = Not Shut Down
0 Safe Memory Load Complete
1 = Complete (Note: Cleared after Read) 0 = Not Complete Bit 0 is asserted when all requested safeload registers have been transferred to the parameter RAM. It is cleared after the read operation is complete. Bit 1 is asserted after the requested shutdown of the DSP is com- pleted. When this bit is set, the user is free to write or read any RAM location without causing an audio pop or click. Table V . Control Register 2 Write Defi nition Register Bits Function
9 Volume Ramp Speed
1 = 160 ms Full Ramp Time 0 = 20 ms Full Ramp Time
8 Serial Port Output Enable
1 = Enabled 0 = Disabled 7:6 Serial Port Input Select 00 = IN0 01 = IN1 10 = IN2 11 = NA 5:4 MCLK Input Select 00 = MCLK0 01 = MCLK1 10 = MCLK2 11 = NA
3 Reserved
2 MCLK in Frequency Select
0 = 512 fSfSf 1 = 256 fS fS f 1:0 MCLK Out Frequency Select 00 = Disabled 01 = 512 fS fS f 10 = 256 fS fS f 11 = MCLK_Out = MCLK_In (Feedthrough) Control Register 2 T able V documents the contents of Control Register 2. Bits 1 and 0 set the frequency of the MCLKOUT pin. If these bits are set to 00, then the MCLKOUT pin is disabled (default). When set to 01, the MCLKOUT pin is set to 512 fS fS f , which is the same as the internal master clock used by the DSP core. When set to 10, this pin is set to 256 fS fS f , derived by dividing the internal DSP clock by 2. In this mode, the output 256 fSclock by 2. In this mode, the output 256 fSclock by 2. In this mode, the output 256 f clock will be inverted with respect to the input 256 fSwith respect to the input 256 fSwith respect to the input 256 f clock. This is not the case with the feedthrough mode. When set to 11, the MCLKOUT pin mirrors the selected MCLK input pin (it’s the output of the MCLK mux selector). Note that the internal DSP master clock may either be the same as the selected MCLK pin (when MCLK frequency select is set to 512 fS fS f mode) or may be derived from the MCLK pin using an internal clock doubler (when MCLK frequency select is set to 256 fS fS f ). Bit 2 selects one of two possible MCLK input frequencies. When set to 0 (default), the MCLK frequency is set to 512 fS fS f . In this mode, the internal DSP clock and the external MCLK are at the same frequency. When set to 1, the MCLK frequency is set to 256 fS fS f , and an internal clock doubler is used to generate the DSP clock. Bits 5 and 4 select one of three clock input sources using an inter- nal mux. To avoid click and pop noises when switching MCLK sources, it is recommended that the user put the DSP core in shutdown before switching MCLK sources. Bits 7 and 6 select one of three serial input sources using an internal mux. Each source selection includes a separate SDATA, LRCLK, and BCLK input. To avoid click and pop noises when switching serial sources, it is recommended that the user put the DSP core in shutdown before writing to these bits. REV. A
Bits 7 and 6. The default is 0 (disabled). will take 8192 LRCLK periods. decrement from a volume of 1.0 (default) down to 0 (muted). LRCLKs, and the volume will pass through 0 on the way. characteristics, as well as delay and spatialization settings. with no signal processing capability.
- Direct read/write. This method allows direct access to the
- Direct read/write after core shutdown. This method avoids
address followed by blocks of data are sent to the RAM.
- Safeload writes. This is where up to fi ve SPI registers are loaded
available for writing to the program RAM or control registers. The next section discusses these options in more detail. graphical representation of this mechanism’s volume envelope. Points A through D are referenced in the following description. SPI Read/Write Data Formats section of this data sheet. Figure 18. Recommended Sequences for Complete Parameter or Program RAM Uploaded Using Shutdown Mechanism
–23– NOTES 1The detector hold and decay times are integer values, while the rest of the parameters are fractional twos complement values. 2The default decay time of the hold/release circuit is set fast enough so that the decay is dominated by the time constant of the rms detector. Table VI. Parameter RAM Contents—Default Program 0 IIR0 Left b0 1.0
1 IIR0 Left b1 0
2 IIR0 Left b2 0
3 IIR0 Left a1 0
4 IIR0 Left a2 0
5 IIR1 Left b0 1.0
6 IIR1 Left b1 0
7 IIR1 Left b2 0
8 IIR1 Left a1 0
9 IIR1 Left a2 0
10 IIR2 Left b0 1.0
11 IIR2 Left b1 0
12 IIR2 Left b2 0
13 IIR2 Left a1 0
14 IIR2 Left a2 0
15 IIR3 Left b0 1.0
16 IIR3 Left b1 0
17 IIR3 Left b2 0
18 IIR3 Left a1 0
19 IIR3 Left a2 0
20 IIR4 Left b0 1.0
21 IIR4 Left b1 0
22 IIR4 Left b2 0
23 IIR4 Left a1 0
24 IIR4 Left a2 0
25 IIR5 Left b0 1.0
26 IIR5 Left b1 0
27 IIR5 Left b2 0
28 IIR5 Left a1 0
29 IIR5 Left a2 0
30 IIR6 Left b0 1.0
31 IIR6 Left b1 0
32 IIR6 Left b2 0
33 IIR6 Left a1 0
34 IIR6 Left a2 0
35 IIR0 Right b0 1.0
36 IIR0 Right b1 0
37 IIR0 Right b2 0
38 IIR0 Right a1 0
39 IIR0 Right a2 0
40 IIR1 Right b0 1.0
41 IIR1 Right b1 0
42 IIR1 Right b2 0
43 IIR1 Right a1 0
44 IIR1 Right a2 0
45 IIR2 Right b0 1.0
46 IIR2 Right b1 0
47 IIR2 Right b2 0
48 IIR2 Right a1 0
49 IIR2 Right a2 0
50 IIR3 Right b0 1.0
51 IIR3 Right b1 0
52 IIR3 Right b2 0
53 IIR3 Right a1 0
Addr Function 2.20 Format
54 IIR3 Right a2 0
55 IIR4 Right b0 1.0
56 IIR4 Right b1 0
57 IIR4 Right b2 0
58 IIR4 Right a1 0
59 IIR4 Right a2 0
60 IIR5 Right b0 1.0
61 IIR5 Right b1 0
62 IIR5 Right b2 0
63 IIR5 Right a1 0
64 IIR5 Right a2 0
65 IIR6 Right b0 1.0
66 IIR6 Right b1 0
67 IIR6 Right b2 0
68 IIR6 Right a1 0
69 IIR6 Right a2 0
70 IIR0 Xover Left b0 1.0
71 IIR0 Xover Left b1 0
72 IIR0 Xover Left b2 0
73 IIR0 Xover Left a1 0
74 IIR0 Xover Left a2 0
75 IIR1 Xover Left b0 1.0
76 IIR1 Xover Left b1 0
77 IIR1 Xover Left b2 0
78 IIR1 Xover Left a1 0
79 IIR1 Xover Left a2 0
80 IIR0 Xover Right b0 1.0
81 IIR0 Xover Right b1 0
82 IIR0 Xover Right b2 0
83 IIR0 Xover Right a1 0
84 IIR0 Xover Right a2 0
85 IIR1 Xover Right b0 1.0
86 IIR1 Xover Right b1 0
87 IIR1 Xover Right b2 0
88 IIR1 Xover Right a1 0
89 IIR1 Xover Right a2 0
90 IIR0 Xover Sub b0 1.0
91 IIR0 Xover Sub b1 0
92 IIR0 Xover Sub b2 0
93 IIR0 Xover Sub a1 0
94 IIR0 Xover Sub a2 0
95 IIR1 Xover Sub b0 1.0
96 IIR1 Xover Sub b1 0
97 IIR1 Xover Sub b2 0
98 IIR1 Xover Sub a1 0
99 IIR1 Xover Sub a2 0
100 IIR2 Xover Sub b0 1.0
101 IIR2 Xover Sub b1 0
102 IIR2 Xover Sub b2 0
103 IIR2 Xover Sub a1 0
104 IIR2 Xover Sub a2 0
105 IIR Sub rms b0 1.0
106 IIR Sub rms b1 0
107 IIR Sub rms b2 0
Addr Function 2.20 Format
108 IIR Sub rms a1 0
109 IIR Sub rms a2 0
110–142 Main Compressor 1.0 (all) Look-Up T able Base 143 Main Compressor 5.75 104 Attack/rms Time (120 dB/sec) Constant 144 Main Post- 1.0 Compressor Gain 145–177 Subwoofer 1.0 Compressor Look-Up T able Base 178 Sub Compressor 5.75 104 Attack/rms Time (120 dB/sec) Constant 179 Post-Compressor 1.0 Gain (Sub)
180 High-Pass Filter
181 Main Compressor 0
182 Delay Left 0
183 Delay Right 0
184 Delay Sub 0
185 Stereo Spreading 0
186 Stereo Spreading 0.112694 Frequency Control 187 Subwoofer 0.0 Reinjection to Main Left 188 Subwoofer 0.0 Reinjection to Main Right 189 Subwoofer Channel 0.5 Input Gain from Left In 190 Subwoofer Channel 0.5 Input Gain from Right In
191 Main Detector Hold 01
Time, Samples (4095 Max)
192 Sub Detector Hold 01
Time, Samples (4095 Max) 193 Main Detector 0.069611 Decay Time (10000 dB/sec)2 194 Sub Detector 0.069611 Decay Time (10000 dB/sec)2 195–255 Unused Default Value in Fractional Addr Function 2.20 Format REV. A
–24– that lasts for 10 ms to 20 ms. Again, this reduces the chance of any pop or click noise from occurring. Note that this shutdown sequence assumes that the part is set to the fast volume ramp speed (Control Register 2, Bit 9). If the slow ramp speed is set, the volume may not reach zero before the part enters shutdown and a click or pop may be heard. Safeload Mechanism Many applications require real-time control of fi lter characteristics, such as bass/treble controls and parametric or graphic equalization. T o prevent instability from occurring, all of the parameters of a particular biquad fi lter must be updated at the same time; other- wise, the fi lter could execute for one or two audio frames with a mixture of old and new coeffi cients. This mix of old and new could cause temporary instability, leading to transients that could take a long time to decay. The method used in the AD1954 to eliminate this problem is to load a set of fi ve registers in the SPI port with the desired param- eter RAM address and data. Five registers are used because each biquad fi lter has fi ve coeffi cients. Once these registers are loaded, the initiate safe transfer bit in Control Register 1 should be set. Once this bit is set, the processor waits for a period of time in the program sequence where the parameter RAM is not being accessed for at least fi ve consecutive instruction cycles. When the program counter reaches this point, the parameter RAM is writ- ten with fi ve new data values at addresses corresponding to those that were entered in the safeload registers. When the operation is complete, Bit 0 of Control Register 1 (read) is set. This bit may be polled by the external microprocessor until a 1 is read and will be reset on a read operation. The polling operation is not required; the safeload mechanism guarantees that the transfer will be complete within one audio frame. The safeload logic automatically sends only those safeload registers that have been written to since the last safeload operation. For example, if only two parameters are to be sent, then it is neces- sary to write to only two of the fi ve safeload registers. When the request safe transfer bit is asserted, only those two registers will be sent; the other three registers are not sent and can still hold old or invalid data. The safeload mechanism is not limited to uploading biquad coeffi cients; any set of fi ve values in the parameter RAM may be updated in the same way. This allows real-time adjustment of the compressor/limiter, delay, or stereo spreading blocks. Summary of RAM Modes Table VII shows the sizes and available modes of the parameter RAM and the program RAM. SPI READ/WRITE DATA FORMATS The read/write formats of the SPI port are designed to be byte- oriented. This allows for easy programming of common microcon- troller chips. To fi t into a byte-oriented format, 0s are appended to the data fi elds to extend the data-word to the next multiple of 8 bits. For example, 22-bit words written to the SPI parameter RAM are appended with two leading zeroes to reach 24 bits (3 bytes), and 35-bit words written to the program RAM are appended with fi ve zeros to reach 40 bits (5 bytes). These zero- extended data fi elds are appended to a 2-byte fi eld consisting of a read/write bit and a 10-bit address. The SPI port knows how many data bytes to expect based on the address that is received in the fi rst two bytes. The total number of bytes for a single-location SPI write command can vary from 4 bytes (for a control register write) to 7 bytes (for a program RAM write). Block writes may be used to fi ll contiguous locations in program RAM or parameter RAM. The read and write formats of the parameter RAM, program RAM and registers are detailed in Tables VIII to XIX. Table VII. Read/Write Modes SPI Address Burst Mode Memory Size Range Read Write Available Write Modes Parameter RAM 256 22 0–255 Y es Y es Y es Direct write, write after core shutdown, safeload write Program RAM 512 35 512–1023 Y es Y es Y es Direct write, write after core shutdown Table VIII. Parameter RAM Read/Write Format (Single Address) Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 00000, R/W00000, R/W00000, R/ , Addr[9:8] Addr[7:0] 00, Param[21:16] Param[15:8] Param[7:0] Table IX. Parameter RAM Block Read/Write Format (Burst Moded) Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 00000, R/W00000, R/W00000, R/ , Addr[9:8] Addr[7:0] 00, Param[21:16] Param[15:8] Param[7:0] Table X. Program RAM Read/Write Format (Single Address) Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 00000, R/W00000, R/W00000, R/ , Addr[9:8] Addr[7:0] 00000, Prog[34:32] Prog[31:24] Prog[23:16] Prog[15:8] Prog[7:0] Byte 5 Byte 8 Byte 6 Byte 9 Byte 7 Byte 10 ADDR + 1 ADDR + 2 Byte 8 Byte 9 Byte 10 ADDR REV. A
–25– Byte 7 Byte 12 Byte 8 Byte 13 Byte 9 Byte 14 Byte 10 Byte 15 Byte 11 Byte 16 ADDR + 1 ADDR + 2 Byte 12 Byte 13 Byte 14 Byte 15 Byte 16 Table XI. Program RAM Read/Write Format (Burst Address) Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 00000, R/W00000, R/W00000, R/ , Addr[9:8] Addr[7:0] 00000, Prog[34:32] Prog[31:24] Prog[23:16] Prog[15:8] Prog[7:0] Table XII. SPI Control Register 1 Write Format Byte 0 Byte 1 Byte 2 Byte 3 00000, R/W00000, R/W00000, R/ , Addr[9:8] Addr[7:0] 0000, Bit[11:8] Bit[7:0] Table XIII. SPI Control Register 1 Read Format Byte 0 Byte 1 Byte 2 00000, R/W00000, R/W00000, R/ , Addr[9:8] Addr[7:0] 000000, Bit[1:0] Table XIV . SPI Control Register 2 Write Format Byte 0 Byte 1 Byte 2 Byte 3 Table XV . SPIVolume Register Write Format Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 000000, Addr[9:8] Addr[7:0] 00, Volume[21:16] Volume[15:8] Volume[7:0] Table XVI. Data Capture Register Write Format Byte 0 Byte 1 Byte 2 Byte 3 00000, R/W00000, R/W00000, R/ , Addr[9:8] Addr[7:0] 00000, ProgCount[8:6]1 ProgCount[5:0], RegSel[1:0]1, 2 NOTES 1ProgCount[8:0] = value of program counter where trap occurs (see Table XX). 2RegSel[1:0] selects one of four registers (see Data Capture Register section). Table XVII. Data Capture Serial Out Register (Address and Register Select) Write Format Byte 0 Byte 1 Byte 2 Byte 3 00000, R/W00000, R/W00000, R/ , Addr[9:8] Addr[7:0] 00000, ProgCount[8:6]1 ProgCount[5:0], RegSel[1:0]1, 2 NOTES 1ProgCount[8:0] = value of program counter where trap occurs (see Table XX). 2RegSel[1:0] selects one of four registers (see Data Capture Register section). Table XVIII. Data Capture Read Format Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 00000, R/W00000, R/W00000, R/ , Addr[9:8] Addr[7:0] 00000000 Data[23:16] Data[15:8] Data[7:0] Table XIX. Safeload Register Write Format Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 00000, R/W00000, R/W00000, R/ , Addr[9:8] Addr[7:0] ParamAddr[7:0] 00, Param[21:16] Param[15:8] Param[7:0] ADDR REV. A
–26– INITIALIZATION Power-Up Sequence The AD1954 has a built-in power-up sequence that initializes the contents of the internal RAMs. During this time, the contents of the internal program boot ROM are copied to the internal program RAM memory, and likewise, the SPI parameter RAM is fi lled with values from its associated boot ROM. The data memo- ries are also cleared during this time. The boot sequence lasts for 1024 MCLK cycles and starts on the rising edge of the RESETB pin. Since the boot sequence requires a stable master clock, the user should avoid writing to or reading from the SPI registers during this period of time. Note that the default power-on state of the internal clock mode circuitry is 512 fS fS f , or about 24 MHz for normal audio sample rates. This mode bypasses all the internal clock doublers and allows the external master clock to directly operate the DSP core. If the external master clock is 256 fS fS f , then the boot sequence will operate at this reduced clock rate and will take slightly longer to complete. After the boot sequence has fi nished, the clock modes may be set via the SPI port. For example, if the external master clock frequency is 256 fS fS f clock, the boot sequence would take 1024 256 fS fS f clock cycles to complete, after which an SPI write could occur to put the AD1954 in 256 fS fS f mode. The default state of the MCLK input selector is MCLK0. Since this input selector is controlled using the SPI port, and the SPI port cannot be written to until the boot sequence is complete, there must be a stable master clock signal present on the MCLK0 pin at startup. Setting the Clock Mode The AD1954 contains a clock doubler circuit that is used to gener- ate an internal 512 fS fS f clock when the external clock is 256 fS fS f . The clock mode is set by writing to Bit 2 of Control Register 2. When the clock mode is changed, it is possible that a glitch will occur on the internal MCLK signal. This may cause the proces- sor to inadvertently write an incorrect value into the data RAM, which could cause an audio pop or click sound. To prevent this the following procedure is recommended: 1. Assert the soft power-down bit (Bit 6 in Control Register 1) to stop the internal MCLK. 2. Write the desired clock mode into Bit 2 of Control Register 2. 3. Wait at least 1 ms while the clock doublers settle. 4. De-assert the soft power-down bit. An alternative procedure is to initiate a soft shutdown of the pro- cessor core by writing a 1 to the halt program bit in Control Register 1. This initiates a volume ramp-down sequence followed by a shutdown of the DSP core. Once the core is shut down (which can be verifi ed by reading Bit 1 from Control Register 1 or by waiting at least 20 ms), the new clock mode can be programmed by writing to Bit 2 of Control Register 2. The DSP core can then be restarted by clearing the halt program bit in Control Register 1. Setting the Data and MCLK Input Selectors The AD1954 contains input selectors for both serial data inputs and the MCLK input. This allows the AD1954 to select a variety of input and clock sources with no external hardware required. These input selectors are controlled by writing to SPI Control Register 2. When the data source or MCLK source is changed by writing to the SPI port, it is possible that a pop or click will occur in the audio. To prevent this noise, the core should be shut down by writing a 1 to the halt program bit in Control Register 1. This initiates a volume ramp-down sequence followed by a shutdown of the DSP core. Once the core is shut down (which can be veri- fi ed by reading Bit 1 from Control Register 1 or by waiting at least 20 ms after the halt program command is issued), the new data or MCLK source can be programmed by writing to Control Register 2. The DSP core can then be restarted by clearing the halt program bit in Control Register 1. DATA CAPTURE REGISTERS The AD1954 incorporates a feature called data capture. Using this feature, any node in the signal processing fl ow may be sent to either an SPI readable register or a dedicated serial output pin. This allows the basic functionality of the AD1954 to be extended to a larger number of channels. Alternatively, it can be used to monitor and display information about signal levels or compressor/limiter activity. The AD1954 contains four independent data capture registers. Two of these registers transfer their data to the data capture serial output (DCSOUT) pin. The serial data format of this pin is the same as the serial data format used for the main digital inputs, and the LRCLK and BCLK signals can therefore be used as frame sync and bit clock signals. This pin is primarily intended to feed signals to an external DAC or DSP chip to extend the number of channels that the internal DSP can access. The other two registers may be read back over the SPI port and can be used for a variety of purposes. One example might be to access the dB output of the internal rms detector to run a front-panel signal level display. A sample system is shown in Figure 19. For each of the four data capture registers, a capture count and a register select must be set. The capture count is a number between 0 and 511 that corresponds to the program step number where the capture will occur. The register select fi eld programs one of four registers in the DSP core that will be transferred to the data cap- ture register when the program counter equals the capture count. The register select fi eld is decoded as follows: 00: Multiplier Output (Mult_Out) 01: Output of dB Conversion Block (DB_OUT) 10: Multiplier Data Input (MDI) 11: Multiplier Coeffi cient Input (MCI) The capture count and register select bits are set by writing to one of the four data capture registers at the following SPI addresses: 261: SPI Data Capture Setup Register 1 262: SPI Data Capture Setup Register 2 263: Data Capture Serial Out Setup Register 1 264: Data Capture Serial Out Setup Register 2 REV. A
than 0 dB, then the digital output will be clipped. value of the full-scale digital signal. AD1954 is set for no processing. cient of 01000000000000000000 corresponds to a gain of 1.0. to be monitored in the default signal processing fl ow. in the SPI section of this data sheet. Figure 19. Typical Application of Data Capture Feature
–28– Table XX. Data Capture Trap Indexes and Register Select—Default Program Program Count Register Signal Description Index (9 Bits) Select (2 Bits) Numeric Format HPF Out Left 15 Mult_Out 1.23, Clipped HPF Out Right 259 Mult_Out 1.23, Clipped De-emphasis Out Left 19 Mult_Out 1.23, Clipped De-emphasis Out Right 263 Mult_Out 1.23, Clipped Left Biquad 0 Output 34 Mult_Out 1.23, Clipped Left Biquad 1 Output 43 Mult_Out 1.23, Clipped Left Biquad 2 Output 52 Mult_Out 1.23, Clipped Left Biquad 3 Output 61 Mult_Out 1.23, Clipped Left Biquad 4 Output 70 Mult_Out 1.23, Clipped Left Biquad 5 Output 79 Mult_Out 1.23, Clipped Left Biquad 6 Output 88 Mult_Out 1.23, Clipped Right Biquad 0 Output 284 Mult_Out 1.23, Clipped Right Biquad 1 Output 293 Mult_Out 1.23, Clipped Right Biquad 2 Output 302 Mult_Out 1.23, Clipped Right Biquad 3 Output 311 Mult_Out 1.23, Clipped Right Biquad 4 Output 320 Mult_Out 1.23, Clipped Right Biquad 5 Output 329 Mult_Out 1.23, Clipped Right Biquad 6 Output 338 Mult_Out 1.23, Clipped Volume Out Left 114 Mult_Out 1.23, Clipped Volume Out Right 111 Mult_Out 1.23, Clipped Volume Out Sub 459 Mult_Out 1.23, Clipped Phat Stereo Out Left 115 Mult_Out 1.23, Clipped Phat Stereo Out Right 112 Mult_Out 1.23, Clipped Delay Output Left 190 Mult_Out 1.23, Clipped Delay Output Right 361 Mult_Out 1.23, Clipped Main Compressor rms Out (dB) 154 DB_Out 24-Bit Positive Binary, Bit 19 Corresponds to a 3 dB Change Main Compressor Gain Reduction 165 MCI 2.22, 2 LSBs = 0 (Linear) Look-Ahead Delay Output Left 165 MDI 3.21, 2 LSBs Truncated Look-Ahead Delay Output Right 178 MDI 3.21, 2 LSBs Truncated Main Compressor Out Left 175 Mult_Out 1.23, Clipped Main Compressor Out Right 188 Mult_Out 1.23, Clipped Interpolator Input Left 191 Mult_Out 1.23, Clipped (Includes Sub Reinject) Interpolator Input Right 362 Mult_Out 1.23, Clipped (Includes Sub Reinject) Subchannel Filter Input 430 Mult_Out 1.23, Clipped Sub Xover Biquad 0 Output 438 Mult_Out 1.23, Clipped Sub Xover Biquad 1 Output 447 Mult_Out 1.23, Clipped Sub Xover Biquad 2 Output 456 Mult_Out 1.23, Clipped Left Xover Biquad 0 Output 99 Mult_Out 1.23, Clipped Left Xover Biquad 1 Output 108 Mult_Out 1.23, Clipped Right Xover Biquad 0 Output 349 Mult_Out 1.23, Clipped Right Xover Biquad 1 Output 358 Mult_Out 1.23, Clipped Sub Delay Output 511 Mult_Out 1.23, Clipped Sub rms Biquad Output 467 Mult_Out 1.23, Clipped Sub rms Output (dB) 489 DB_Out 24-Bit Positive Binary, Bit 19 Corresponds to a 3 dB Change Sub Compressor Gain (Linear) 495 MCI 2.22, 2 LSBs = 0 Subchannel Output 511 Mult_Out 1.23, Clipped REV. A
exactly 64 BCLKs per audio frame. left-justifi ed mode can accept any word length up to 24 bits. for the right channel. Data is sampled on the rising edge of BCLK.
12 BCLK, or 8 BCLK intervals, depending on the selected word
mode, it is assumed that there are 64 BCLKs per frame. maintained from that point forward. The AD1954 offers two methods of muting the analog output. ing the device by automatically ramping the gain up or down.
- DSP MODE DOESN’T IDENTIFY CHANNEL.
- LRCLK NORMALLY OPERATES AT fS EXCEPT DSP MODE, WHICH IS 2 fS.
- BCLK FREQUENCY IS NORMALLY 64 LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 20. Serial Input Modes
–31– GRAPHICAL CUSTOM PROGRAMMING TOOLS Custom programming tools are available for the AD1954 from ADI. These graphical tools allow the user to modify the default signal processing fl ow by individually placing each block (e.g., biquad fi lter, Phat Stereo, dynamics processor) and connecting them in any desired fashion. The program then creates a fi le that is loaded into the AD1954’s program RAM. All of the contents of the parame- ter RAM can also be set using these tools. For more information on these programming tools, contact SigmaDSP@analog.com. REV. A
–32– APPENDIX Cookbook Formulae for Audio EQ Biquad Coeffi cients (Adapted from Robert Bristow-Johnson’s Internet Posting) For designing a parametric EQ, follow the steps below. 1. Given: Frequency Q dB_Gain Sample_Rate 2. Compute intermediate variables: A = 10(dB_Gain/40) = 2 Frequency/Sample_Rate sn = sin() cs = cos() = sn/(2 Q) 3. Compute coeffi cients: 4. The transfer function implemented by the AD1954 is given by: Note the inversion in sign of a1 and a2 relative to the more stan dard form. This form is used in this document because the AD1954 implements the difference equation using the formula below. REV. A
–33– OUTLINE DIMENSIONS 44-Lead Metric Quad Flat Package [MQFP] (S-44) Dimensions shown in millimeters 0.80 BSC 0.45 0.29 2.45 MAX 1.03 0.88 0.73 0.8SEATING PLANE TOP VIEW (PINS DOWN) COPLANARITY 0.10 PIN 1
0.25 MAX
0.10 MIN
ROTATED 90 CCW 02.20 2.00 1.80 VIEW A 13.45 13.20 SQ 12.95 10.20 10.00 SQ 9.80 COMPLIANT TO JEDEC STANDARDS MO-112-AB 48-Lead Low Profi le Quad Flat Package [LQFP] (ST -48) Dimensions shown in millimeters TOP VIEW (PINS DOWN) 3748 0.27 0.22 0.17 0.50 BSC 7.00 BSC SQ SEATING PLANE 1.60 MAX 0.75 0.60 0.45 VIEW A
9.00 BSC
0.20 0.09 1.45 1.40 1.35
0.08 MAX
ROTATED 90 CCW SEATING PLANE 10 3.5 00.15 0.05 COMPLIANT TO JEDEC STANDARDS MS-026BBC REV. A
–34–
Revision History
8/03—Data Sheet changed from REV . 0 to REV . A. REV. A
–35–
C02760–0–8/03(A) –36–