AD1940

AD1940 (Rev. B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 36

Technical content

Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent ri ghts of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113©2004–2010 Analog Devices, Inc. All rights reserved.

FEATURES

16-channel digital audio processor Accepts sample rates up to 192 kHz 28-bit × 28-bit multiplier with full 56-bit accumulator Fully programmable program RAM for custom program download Parameter RAM allows complete control of 1,024 parameters Control port features safeload for transparent parameter updates and complete mode and memory transfer control Target/slew RAM for click-free volume control and dynamic parameter updates Double precision mode for full 56-bit processing PLL for generating MCLK from 64 × fS, 256 × fS, 384 × fS, or 512 × fS clocks Hardware-accelerated DSP core 21 kB (6,144 words) data memory for up to 128 ms of audio delay at f s = 48 kHz Flexible serial data port with I2S-compatible, left-justified, and right-justified serial port modes 8- and 16-channel TDM input/output modes On-chip voltage regulator for compatibility with 3.3 V and

5 V systems

Programmable low power mode Fast start-up and boot time from power-on or reset 48-lead LQFP plastic package

APPLICATIONS

Home theater systems (Dolby digital/DTS postprocessor) Multichannel audio systems Mini-component stereos Multimedia audio Digital speaker crossover Musical instruments In-seat sound systems (aircrafts/motor coaches) FUNCTIONAL BLOCK DIAGRAM VOLTAGE REGULATOR AD1940/AD1941 28 × 28 DSP CORE DATA FORMAT: PLL SERIAL CONTROL INTERFACE SERIAL DATA/ TDM INPUTS MASTER CLOCK INPUT SPI/I2C I/O RAM ROM SERIAL DATA/ TDM OUTPUTS 04607-0-001 5.23 (SINGLE PRECISION) 10.46 (DOUBLE PRECISION) Figure 1. GENERAL DESCRIPTION The AD1940/AD1941 are a complete 28-bit, single-chip, multi- channel audio SigmaDSP™ for equalization, multiband dynamic processing, delay compensation, speaker compensation, and image enhancement. These algorithms can be used to compen- sate for the real world limitations of speakers, amplifiers, and listening environments, resulting in a dramatic improvement of perceived audio quality. The signal processing used in the AD1940/AD1941 is comparable to that found in high end studio equipment. Most of the processing is done in full, 56-bit double-precision mode, resulting in very good, low level signal performance and the absence of limit cycles or idle tones. The dynamics processor uses a sophisticated, multiple-breakpoint algorithm often found in high end broadcast compressors. The AD1940/AD1941 are a fully programmable DSP . Easy to use software allows the user to graphically configure a custom signal processing flow using blocks such as biquad filters, dyna- mics processors, and surround sound processors. An extensive control port allows click-free parameter updates, along with readback capability from any point in the algorithm flow. The AD1940/AD1941’s digital input and output ports allow a glueless connection to ADCs and DACs by multiple, 2-channel serial data streams or TDM data streams. When in TDM mode, the AD1940/AD1941 can input 8 or 16 channels of serial data, and can output 8 or 16 channels of serial data. The input and output port configurations can be individually set. The AD1940 is controlled by a 4-wire SPI ® port; the AD1941 is controlled by a 2-wire I2C® bus. Other than the control interface, the functions of the two parts are identical.

Rev. B | Page 2 of 36 TABLE OF CONTENTS Recommended Program/Parameter Loading Procedures .... 20

REVISION HISTORY

4/10—Rev. A to Rev. B 4/05—Rev. 0 to Rev. A 7/04—Revision 0: Initial Version

Rev. B | Page 3 of 36 SPECIFICATIONS Test conditions, unless otherwise noted. Table 1. Parameter Conditions Supply Voltage (VDD) 2.5 V PLL Voltage (PLL_VDD) 2.5 V Output Voltage (ODVDD) 5.0 V INVDD Voltage 5.0 V Ambient Temperature 25°C Master Clock Input 3.072 MHz, 64 × fs mode Load Capacitance 50 pF Load Current ±1 mA Input Voltage, HI 2.4 V Input Voltage, LO 0.8 V DIGITAL I/O VDD = 2.25 V to 2.75 V . Specifications measured across −40°C to 125°C (case). Table 2. Parameter Comments Min Max Unit Input Voltage, HI (VIH) 2.1 V Input Voltage, LO (VIL) 0.8 V Input Leakage (IIH) 10 μA Input Leakage (IIL) 10 μA High Level Output Voltage (VOH) ODVDD = 4.5 V, IOH = 1 mA 3.9 V High Level Output Voltage (VOH) ODVDD = 3.0 V, IOH = 1 mA 2.6 V Low Level Output Voltage (VOL) ODVDD = 4.5 V, IOL = 1 mA1 0.4 V Low Level Output Voltage (VOL) ODVDD = 3.0 V, IOL = 1 mA1 0.3 V Input Capacitance 5 pF 1 SDA is measured with a 3 mA sink current. POWER Table 3. Parameter Min Typ Max1 Unit SUPPLIES Voltage 2.25 2.5 2.75 V Digital Current 92 1552 mA PLL Current 3.5 8 mA Digital Current, Reset 4.53 13 3 mA PLL Current, Reset 3 8.5 mA DISSIPATION Operation, All Supplies 238.8 mW Reset, All Supplies 10.8 mW 1 Maximum specifications are measured across −40°C to 125°C (case) and across VDD = 2.25 V to 2.75 V. 2 Measurement running a typical large program that writes to all 16 outputs with 0 dB digital sine waves applied to all eight inputs. The end user’s program may differ. 3 The digital reset current is specified for the given test conditions. This current scales with the input MCLK rate, so higher input clocks draw more current while in reset.

VDD = 2.25 to 2.75 V . Specifications measured across –40°C to 125°C. Table 4. Digital Timing1 1 All timing specifications are given for the default (I2S) states of the serial input control port and the serial output control ports. See Table 37. master clock at fs = 48 kHz has a 14 ns period. The values in parentheses are the timing values for fs = 48 kHz.

Rev. B | Page 5 of 36 PLL VDD = 2.25 to 2.75 V . Specifications measured across –40°C to 125°C. Table 5. Parameter Min Typ Max Unit Lock Time 3 20 ms REGULATOR VDD = 2.25 to 2.75 V . Specifications measured across –40°C to 125°C. Table 6. Parameter Min Typ Max Unit VSENSE Output Voltage 2.25 2.5 2.68 V TEMPERATURE RANGE Table 7. Parameter Min Typ Max Unit Functionality Guaranteed –40 +105 °C Ambient –40 +125 °C Case

Table 9. Package Characteristics degradation or loss of functionality.

Figure 7. 48-Lead LQFP Pin Configuration, AD1940 Figure 8. 48-Lead LQFP Pin Configuration, AD1941 Table 10. Pin Function Descriptions 2 2 IN MCLK Master Clock Input. 3 3 RESERVED This pin should be connected to ground. 4 4 IN PLL_CTRL0 PLL Control 0. 5 5 IN PLL_CTRL1 PLL Control 1. 6 6 IN PLL_CTRL2 PLL Control 2. 9 IN I2C_FILT_ENB I2C Filter Enable, Active Low. 10 10 IN LRCLK_IN Left/Right Clock for Serial or TDM Data Inputs. 11 11 IN BCLK_IN Bit Clock for Serial or TDM Data Inputs. 14 14 IN SDATA_IN0 Serial Data Input 0. 15 12 IN SDATA_IN1 Serial Data Input 1. 16 16 IN SDATA_IN2/TDM_IN1 Serial Data Input 2/TDM Input 1. 17 17 IN SDATA_IN3/TDM_IN0 Serial Data Input 3/TDM Input 0. 18 18 IN ADR_SEL Control Port Address Select. 19 OUT COUT SPI Data Output. 21 IN CLATCH SPI Data Latch.

Rev. B | Page 10 of 36 Pin No. AD1940 AD1941 I/O Mnemonic Description 22 IN CDATA Data Input for SPI. 19 IN/OUT SDA I2C Serial Data I/O. 20 IN SCL I2C Clock. 23 23 IN RESETB Reset the AD1940/AD1941. 26 26 IN/OUT LRCLK_OUT0 Left/Right Clock Output 0. 27 27 IN/OUT BCLK_OUT0 Bit Clock Output 0. 28, 33, 40 28, 33, 40 ODVDD Power Connection for Output Pins. 29 29 OUT SDATA_OUT0/TDM_O0 Serial Data Output 0/TDM (16- or 8-Channel) Output 0. 30 30 OUT SDATA_OUT1 Serial Data Output 1. 31 31 OUT SDATA_OUT2 Serial Data Output 2. 32 32 OUT SDATA_OUT3 Serial Data Output 3. 34 34 IN/OUT LRCLK_OUT1 Left/Right Clock Output 1. 35 35 IN/OUT BCLK_OUT1 Bit Clock Output 1. 38 38 OUT SDATA_OUT4/TDM_O1 Serial Data Output 4./TDM (8-Channel) Output 1. 39 39 OUT SDATA_OUT5 Serial Data Output 5. 41 41 OUT SDATA_OUT6 Serial Data Output 6. 42 42 OUT SDATA_OUT7/DCSOUT Serial Data Output 7/Data Capture Output. 43 43 INVDD Input Voltage Reference. 44 44 IN VSUPPLY Voltage Level Input to Regulator. Usually 3.3 V or 5 V. 45 45 IN VSENSE Digital Power Level. Should be tied to VDD. 46 46 OUT VDRIVE Drive for External PNP Transistor. 47 47 OUT VREF Reference Level for Voltage Regulator.

Rev. B | Page 11 of 36 The core of the AD1940/AD1941 is a 28-bit DSP (56-bit, double precision) optimized for audio processing. The parts’ program RAM can be loaded with a custom program after power-up. Signal processing parameters are stored in a 1024 location parameter RAM, which is initialized on power-up by an internal boot ROM. New values are written to the parameter RAM using the control port. The values stored in the parameter RAM control individual signal processing blocks, such as IIR equali-zation filters, dynamics processors, audio delays, and mixer levels. A safeload feature allows parameters to be transparently updated without causing clicks on the output signals. The target/slew RAM contains 64 locations and can be used as channel volume controls or for other parameter updates. These RAM locations take a target value for a given parameter and ramp the current parameter value to the new value using a specified time constant and one of a selection of linear or logarithmic curves. The AD1940/AD1941 contain eight independent data capture circuits that can be programmed to tap the signal flow of the processor at any point in the DSP algorithm flow. Six of these captured signals can be accessed by reading from the data capture registers through the control port. The remaining two data capture registers can be used to send any internal captured signal to a stereo digital output signal on Pin SDATA_OUT7 for driving external DACs or digital analyzers. The AD1940/AD1941 have a sophisticated control port that supports complete read/write capability of all memory locations. Five control registers (Core, RAM configuration, Serial Output 0 to 7, Serial Output 8 to 15, and serial input) are provided to offer complete control of the chip’s configuration and serial modes. Handshaking is included for ease of memory uploads/downloads. The AD1940 is SPI-controlled and the AD1941 is controlled by an I 2C bus. The AD1940/AD1941 have very flexible serial data input/output ports that allow glueless interconnection to a variety of ADCs, DACs, general-purpose DSPs, S/PDIF receivers and trans-mitters, and sample rate converters. The AD1940/AD1941 can be configured in I 2S, left-justified, right- justified, or TDM serial port-compatible modes. It can support 16, 20, and 24 bits in all modes. The AD1940/AD1941 accepts serial audio data in MSB first and twos complement format. A master clock phase-locked loop (PLL) allows the AD1940/ AD1941 to be clocked from a variety of different clock speeds. The PLL can accept inputs of 64 × f S, 256 × fS, 384 × fS, or 512 × fS to generate the core’s internal master clock. The AD1940/AD1941 operate from a single 2.5 V power supply. An on-board voltage regulator can be used to operate the chip with 3.3 V or 5 V supplies. They are fabricated on a single monolithic integrated circuit and are housed in 48-lead LQFP packages for operation over the –40°C to +105°C temperature range. 04607-0-003 28 × 28 DSP CORE DATA FORMAT: 5.23 (SINGLE PRECISION) 10.46 (DOUBLE PRECISION) VOLTAGE REGULATORMEMORY CONTROLLERS CONTROL REGISITER TRAP REG. SAFELOAD REGISTER SERIAL CONTROL PORT MCLK PLL DATA MEMORY 6k × 28 TARGET/SLEW RAM 64 × 28 SERIAL DATA/TDM INPUT GROUP PLL MODE SELECT MASTER CLOCK INPUT CONTROL PORT I/O GROUP RESETB PROGRAM RAM 1536 × 40 BOOT ROM BOOT ROM PARAMETER RAM 1024 × 28 COEFFICIENT ROM 512 × 28 SERIAL DATA/ TDM OUTPUT GROUP REGULATOR GROUP ADDRESS SELECT Figure 9. Block Diagram

Rev. B | Page 12 of 36 PIN FUNCTIONS Table 10 shows the AD1940/AD1941’s pin numbers, names, and functions. Input pins have a logic threshold compatible with TTL input levels and may be used in systems with 3.3 V or 5 V logic. SDATA_IN0 SDATA_IN1 SDATA_IN2/TDM_IN1 SDATA_IN3/TDM_IN0 Serial Data/TDM Inputs. The serial format is selected by writing to Bits 2:0 of the serial input port control register. SDATA_IN2 and SDATA_IN3 are dual-function pins that can be set to a variety of standard 2-channel formats or to TDM mode. Two of these four pins (SDATA_IN2 and SDATA_IN3) can be used as TDM inputs in either dual-wire 8-channel mode or single-wire 16-channel mode (TDM_O0 only). In dual-wire 8-channel mode, Channels 0 to 7 are input on SDATA_IN3 and Channels 8 to 15 on SDATA_IN2. In single-wire 16-channel mode, Channels 0 to 15 are input on SDATA_IN2. See the Serial Data Input/Output Ports section for further explanation. LRCLK_IN BCLK_IN Left/Right and Bit Clocks for Timing the Input Data. These input clocks are associated with the SDATA_IN0 through SDATA_IN3 signals. The input port is always in a slave configuration. These pins also function as frame sync and bit clock for the input TDM stream. SDATA_OUT0/TDM_O0 SDATA_OUT1 SDATA_OUT2 SDATA_OUT3 SDATA_OUT4/TDM_O1 SDATA_OUT5 SDATA_OUT6 SDATA_OUT7/DCSOUT Serial Data/TDM/Data Capture Outputs. These pins are used for serial digital outputs. For non-TDM systems, these eight pins can output 16 channels of digital audio, using a variety of standard 2-channel formats. They are grouped into two groups of four pins (Pins 0 to 3 and Pins 4 to 7); each group can be independently set to any of the available serial modes, allowing the AD1940/AD1941 to simultaneously communicate with two external devices with different serial formats. Two of these eight pins (SDATA_OUT0 and SDATA_OUT4) can be used as TDM outputs in either dual-wire 8-channel mode or single-wire 16- channel mode (TDM_OUT0 only). In dual-wire 8-channel mode, Channels 0 to 7 are output on SDATA_OUT0 and Channels 8 to 15 on SDATA_OUT4. See the Serial Data Input/Output Ports section for further explanation. SDATA_OUT7 can also be used as a data capture output, as described in the Data Capture Registers section. LRCLK_OUT0 BCLK_OUT0 Output Clocks. This clock pair is used for outputs SDATA_OUT0 through SDATA_OUT3. In slave mode, these clocks are inputs to the AD1940/AD1941. On power-up, these pins are set to slave mode to avoid conflicts with external master mode devices. LRCLK_OUT1 BCLK_OUT1 Output Clocks. This clock pair is used for outputs SDATA_OUT4 through SDATA_OUT7. In slave mode, these clocks are inputs to the AD1940/AD1941. On power-up, these pins are set to slave mode to avoid conflicts with external master mode devices. MCLK Master Clock Input. The AD1940/AD1941 uses a PLL to generate the appropriate internal clock for the DSP core. An in-depth description of using the PLL is found in the Setting Master Clock/PLL Mode section. PLL_CTRL0 PLL_CTRL1 PLL_CTRL2 PLL Mode Control Pins. The functionality of these pins is described in the Setting Master Clock/PLL Mode section. CDATA (AD1940) Serial Data Input for the SPI Control Port. COUT (AD1940) Serial Data Output for the SPI Port. This is used for reading back registers and memory locations. It is three-stated when an SPI read is not active. CCLK (AD1940) SPI Bit Clock. This clock may either run continuously or be gated off between SPI transactions. CLATCH (AD1940) SPI Latch Signal. This must go low at the beginning of an SPI transaction and high at the end of a transaction. Each SPI transaction may take a different number of CCLKs to complete, depending on the address and read/write bit that are sent at the beginning of the SPI transaction. SCL (AD1941) I2C Clock. This pin is always an input because the AD1941 cannot act as a master on the I2C bus. The line connected to this pin should have a 2 kΩ pull-up resistor on it. SDA (AD1941) I2C Serial Data. The data line is bidirectional. The line connected to this pin should have a 2 kΩ pull-up resistor on it.

Rev. B | Page 13 of 36 I2C_FILT_ENB (AD1941) I2C Spike Filter Enable/Disable. This enables (active low) the I2C spike filter, which is used to prevent noise or glitches on the I2C bus from improperly affecting the AD1941. ADR_SEL Address Select. This pin selects the address for the AD1940/ AD1941’s communication with the control port. This allows two AD1940s to be used with a single CLATCH signal or two AD1941s to be used on the same I 2C bus. RESETB Active-Low Reset Signal. After RESETB goes high, the AD1940/AD1941 goes through an initialization sequence where the program and parameter RAMs are initialized with the contents of the on-board boot ROMs. All registers are set to 0, and the data RAMs are also set to 0. The initialization is com- plete after 8,192 internal MCLK cycles (referenced to the rising edge of RESETB), which corresponds to 1,366 external MCLK cycles if the part is in 256 × f S mode. New values should not be written to the control port until the initialization is complete. VREF Voltage Reference for Regulator. This pin is driven by an internal 1.15 V reference voltage. VDRIVE Drive for External Transistor. The base of the voltage regulator’s external PNP transistor is driven from this pin. VSENSE Digital Power Level. The voltage level on the VDD pins is sensed on VSENSE. VSENSE should be tied to VDD. VSUPPLY Main Supply Voltage Level. This pin is tied to the board’s main voltage supply. This is usually 3.3 V or 5 V . VDD (4) Digital VDD for Core. 2.5 V nominal. GND (4) Digital Ground. PLL_VDD Supply for AD1940/AD1941 PLL. 2.5 V nominal. PLL_GND PLL Ground. ODVDD (3) VDD for All Digital Outputs. The high levels of the digital output signals are set on this pin. The voltage can range from 2.5 V to 5.0 V . INVDD Peak Input Voltage Level. The highest voltage level that the input pin sees should be connected to INVDD. This is to protect the chip inputs from voltage overstress. The voltage on this pin must always be at or above the level of ODVDD.

time control of all signal processing functions. processor to allow internal gains up to 24 dB without clipping. input signal in the signal flow. gains of up to 24 dB without encountering internal clipping. range of 1.0 (minus 1 LSB) to –1.0. Figure 10. Numeric Precision and Clipping Structure outputs are muted by default (see Power-Up Sequence section). in the core control register. AD1940/AD1941’s program RAM through the control port.

• Single- and double-precision biquad filters
• Mono and multichannel dynamics processors
• Mixers and splitters
• Tone and noise generators
• First-order filters
• Fixed and variable gain
• RMS look-up tables
• Loudness
• Delay
• Stereo enhancement (Phat Stereo
• Dynamic bass boost
• Interpolators and dececimators More blocks are always in development. Analog Devices also provides proprietary and third-party algorithms for applications such as matrix decoding, bass enhancement, and surround virtualizers. Contact an ADI sales representative for infor- mation about licensing these algorithms.

control, are programmed by writing to the control registers. on the type of data that is written. data, such as control port, program, or parameter data. the core control register), new data loaded, and then restarted. data written should be MSB first. Table 11. Generic SPI Word Format (Logic Level 1) or a write (Logic Level 0). appropriate RAM location or register. Control Port Read/Write Data Formats section. diagram of a single SPI read operation is shown in Figure 12. R/W bit, and subsequent bytes carry the data.

Table 12. AD1941 I2C Addresses and the part returns to the idle condition. Table 13 shows the timing of a single-word write operation. Table 14 shows the timing of a burst mode write sequence. acknowledge pulse to the AD1941. to a register or memory area with word lengths of two bytes. address increments after the appropriate number of bytes.

Figure 14. AD1941 I2C Read Format Table 13. Single Word I2C Write Table 14. Burst Mode I2C Write Table 15. Single Word I2C Read Table 16. Burst Mode I2C Read

Table 17. Control Port Addresses Table 18. RAM Read/Write Modes

2 Safeload write

1 DSP core should be shut down first to avoid clicks/pops. 2 The target/slew RAMs need to be written through the safeload registers. Safeload writes may be done in either single write mode or burst mode. are initialized on power-up from on-board boot ROMs. parameter, program, and target/slew RAMs.

1. The parameter RAM is initialized to all 0s on power-up.
2. Direct Read/Write. This method allows direct access to
3. Safeload Write. Up to five safeload registers can be loaded

program RAM or control registers. The following sections discuss these two options in more detail.

mechanisms for disabling the core.

1. Assert Bit 9 (low to assert—default setting) and Bit 6 (high
2. Fill the program RAM using burst mode writes.
3. Fill the parameter RAM using burst mode writes.
4. Assert Bit 7 of the core control register to initiate a data-
5. Deassert Bit 9 and Bit 6 of the core control register to allow
6. Assert Bit 12 of the core control register. This begins a

register, or simply wait for a given amount of time).

1. Assert Bit 9 (low to assert) and Bit 6 (high to assert) of the

serial output registers, and the serial input registers.

1. Fill the program RAM using burst mode writes.
2. Fill the parameter RAM using burst mode writes.
3. Assert Bit 7 of the core control register to initiate a data-
4. Deassert Bit 9 and Bit 6 of the core control register.
5. If the newly loaded program also uses the target/slew

format for the constant time ramping. safeload registers as described in the Safeload Registers section. Table 19. Linear, Constant dB, and RC Type Table 20. Constant Time Ramp Data Write

• Linear—Value slews to target using a fixed step size.
• Constant dB—Value slews to target using the current value to calculate the step size. The resulting curve has a constant rise and decay when measured in dB.
• RC type—Value slews to target using the difference between target and current values to calculate the step size, producing a simple RC type curve for rising and falling.
• Constant Time—Value slews to the target in a fixed number of steps in a linear fashion. The control port mute has no affect on this type.

Table 21. Target/Slew RAM Ramp Type Settings

00 Linear

01 Constant dB

10 RC type

11 Constant time

• Ramp Type (2 bits)
• Time Constant (4 bits) 0000 = Fastest 1111 = Slowest
• Data (28 Bits): 5.23 Format Ramp Type 4—Constant Time (34-Bit Write) The target word for the constant time ramp type is written in five parts, with the 34-bit command again written with six leading zeros to extend the data write to five bytes. The parts of the constant time target RAM write are the following:
• Ramp Type (2 bits).
• Update Step (1 bit). Set to 1 when new target is loaded to trigger step value update. Value is automatically reset after the step value is updated.
• Number of Steps (3 bits). The number of steps that it takes to slew to the target value is set by these three bits, with the number of steps equal to 23-bit setting + 6. 000 = 64 001 = 128 010 = 256 011 = 512 100 = 1024 101 = 2048 110 = 4096 111 = 8196
• Data (16 bits). 2.14 format.
• Reserved (12 bits). When writing to the RAM, these bits should all be set to 0. Target and Slew RAM Initialization On reset, the target/slew RAM initializes to preset values. The target RAM initializes to a linear ramp type with a time constant of 5 and the data set to 1.0. The slew RAM initializes to a value of 1.0. These defaults give a full-scale (1.0 to 0.0) ramp time of 21.3 ms. Linear Update Math Linear math is the addition or subtraction of a constant value (step). The equation to describe this step size is 5 2 − ×= tconststep The result of the equation is normalized to a 5.23 data format. This gives a time constant range from 6.75 ms to 213.4 ms (–60 dB relative to 0 dB full scale). An example of this kind of update is shown in Figure 15 and Figure 16. All slew RAM figure examples, except the half-scale constant time ramp plot, show an increasing or decreasing ramp between –80 dB and 0 dB (full scale). All figures except the constant time plots (Figure 19 and Figure 21) use a time constant of 0x7 (0x0 being the fastest and 0xF being the slowest). TIME (ms) OUTPUT LEVEL (V) 0.4 0.6 0.8 0.2 –0.4 –0.2 –0.8 –0.6 01 0 2 0 3 0 04607-0-017

Figure 15. Slew RAM—Linear Update Increasing Ramp

selections are shown in Table 23. Table 23. Data Capture Output Register Select

00 Multiplier X input (Mult_X_input)

01 Multiplier Y input (Mult_Y_input)

10 Multiplier-Accumulator Output (MAC_out)

11 Accumulator Feedback (Accum_fback)

the internal 5.23 data-word. capture registers can be seen in Table 32 and Table 33. click or pop when shutdown is asserted. been previously written to the high bits of the target RAM. Table 24. DSP Core Control Register (2642)

13 Slew RAM muted (read-only)

12 Mute slew RAM, all locations

11 Reserved, set to 0

10 Use serial out LRCLK for output latch

9 Clear internal registers to all 0s, active low

8 Force multiplier to 0

7 Inititalize data memory with 0s

6 Mute serial input port

5 Initiate safe transfer to target RAM

4 Initiate safe transfer to parameter RAM

assembly language coding in the ADI graphical tools. occurring during the power-up sequence.

Setting this bit to 1 initializes all data memory locations to 0. download has occurred to ensure click-free operation. have been written since the last safeload event are transferred. Address 0 corresponds to the first target RAM location. have been written since the last safeload event are transferred. Address 0 corresponds to the first parameter RAM location. length of 192 steps is available, but is not commonly used. consumption of the part is cut approximately in half. Table 25. RAM Configuration Register (2643) mented automatically at the audio frame rate. order to extend the data word to the next multiple of eight bits.

Table 26. Parameter RAM Read/Write Format (Single Address) Table 27. Parameter RAM Block Read/Write Format (Burst Mode) increments until the data transfer reaches the IC's last address. Table 28. Program RAM Read/Write Format (Single Address) Table 29. Program RAM Block Read/Write Format (Burst Mode) increments until the data transfer reaches the IC's last address. Table 30. Control Register Read/Write Format (Core, Serial Out 0, Serial Out 1) Table 31. Control Register Read/Write Format (RAM Configuration, Serial Input)

Table 32. Data Capture Register Write Format 1 Progcount [10:0] = value of program counter where trap occurs (the table of values is generated by the program compiler). 2 Regsel [1:0] selects one of four registers (see Data Capture Registers section). Table 33. Data Capture (Control Port Readback) Register Read Format Table 34. Safeload Register Data Write Format Table 35. Safeload Register Address Write Format

serial output and serial input control registers. modes in which the serial output port will function. modes requires the LSB to align with the edge of the LRCLK. LRCLK_OUT1 and BCLK_OUT1 Clock Ports 8 to 15. apply to both master and slave modes unless otherwise noted. Table 36. Serial Output Port Master/Slave Mode Capabilities Table 37. Data Format Configurations

Table 38. Serial Output Control Register 1

15 Dither enable

14 Internally link TDM streams into single,

13 LRCLK polarity

12 BCLK polarity

11 Master/Slave

6 Frame sync type

5 Serial output/TDM mode control

101 Reserved

111 Reserved

Table 39. Serial Output Control Register 2

14 Data capture serial out enable

Setting this bit to 1 enables dither on the appropriate channels. Pins SDATA_OUT0 and SDATA_OUT4. Capture Registers section for a full explanation of this mode. This bit sets whether the output port is a clock master or slave. which time they become clock outputs. from the internal 73.728 MHz core clock. This bit sets the type of signal on the LRCLK_OUTx pins. clock at the beginning of the data frame. control registers to enable 16-channel TDM on SDATA_OUT0. following the LSB are set to 0. Table 40. Serial Input Control Register (2646)

4 LRCLK polarity

3 BCLK polarity

in on SDATA_IN2/TDM_IN1 and SDATA_IN3/TDM_IN0. 16-channel TDM input mode, input on TDM_IN1. register) that follows a falling edge on the LRCLK_IN pin. be used, and a high pulse should be used when the bit it set to 1.

32 BCLKs

256 BCLKs

Figure 26. 8-Channel TDM Mode Figure 27. TDM Mode with Pulse Word Clock

also cleared during this time. pins. Reset is synched to the falling edge of the internal MCLK. to the 16 digital outputs, as shown in Figure 28. Figure 28. Default Program Signal Flow Table 41. PLL Modes

1 X = don’t care

pins should be changed while RESETB is held low. Figure 29. The 10 μF and 100 nF capacitors shown in this capacitor should be connected between this pin and ground. resistor should be connected between VDRIVE and VSUPPLY . Figure 29. Voltage Regulator Design

Rev. B | Page 34 of 36 There are two specifications that should be taken into consideration when choosing a regulator transistor. First, the transistor’s current amplification factor (hFE or beta) should be at least 100. Second, the transistor’s collector needs to be able to dissipate the heat generated when regulating from 3.3 V or 5 V to 2.5 V . The maximum current draw of the AD1940/AD1941 is 163 mA (maximum digital current + maximum PLL current). The equations for the minimum power dissipation specs for both 3.3 V and 5 V follow: (5 V – 2.5 V) × 163 mA = 480 mW (3.3 V – 2.5 V) × 163 mA = 130 mW If the regulator is not used in the design, VREF, VDRIVE, and VSENSE can be tied to ground. VSUPPLY should be connected to the same or higher potential as the VDD pin.

Figure 30. 48-Lead Low-Profile Quad Flat Package [LQFP]

Rev. B | Page 36 of 36 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2004–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04607-0-4/10(B)