AD1938

AD1938 (Rev. E)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 32

Technical content

4 ADC/8 DAC with PLL,

192 kHz, 24-Bit Codec Data Sheet AD1938 Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2006–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

PLL generated or direct master clock Low EMI design 108 dB DAC/107 dB ADC dynamic range and SNR −94 dB THD + N

3.3 V single supply

Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates Differential ADC input Single-ended DAC output Log volume control with autoramp function SPI controllable for flexibility Software-controllable clickless mute Software power-down Right-justified, left-justified, I2S-justified, and TDM modes Master and slave modes up to 16-channel input/output 48-lead LQFP package Qualified for automotive applications

APPLICATIONS

Digital audio effects processors GENERAL DESCRIPTION The AD1938 is a high performance, single-chip codec that pro- vides four analog-to-digital converters (ADCs) with input and eight digital-to-analog converters (DACs) with single-ended output using the Analog Devices, Inc., patented multibit sigma-delta (Σ-Δ) architecture. An SPI port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1938 operates from 3.3 V digital and analog supplies. The AD1938 is available in a 48-lead (single-ended output) LQFP package. Other members of this family include a diffe- rential DAC output and I2C® control port version. The AD1938 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the master clock from the LR clock or from an external crystal, the AD1938 elimi- nates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The DACs and ADCs are designed using the latest Analog Devices continuous time architectures to further minimize EMI. By using 3.3 V supplies, power consumption is minimized, further reducing emissions. FUNCTIONAL BLOCK DIAGRAM DIGITAL FILTER SERIAL DATA PORT DIGITAL AUDIO INPUT/OUTPUT PRECISION VOLTAGE REFERENCE TIMING MANAGEMENT AND CONTROL (CLOCK AND PLL) SPI CONTROL PORT CONTROL DATA INPUT/OUTPUT AD1938 ADC ADC ADC ADC ANALOG AUDIO INPUTS ANALOG AUDIO OUTPUTS DAC DAC DAC DAC DAC DAC DAC DAC DIGITAL FILTER AND VOLUME CONTROL SDATA OUT SDATA IN CLOCKS 05582-001 Figure 1.

Rev. E | Page 2 of 32 TABLE OF CONTENTS

REVISION HISTORY

2/13—Rev. D to Rev. E 7/11—Rev. C to Rev. D Changes to Table 10, DSDATAx/ASDATAx Pin Descriptions ... 9 1/11—Rev. B to Rev. C 8/09—Rev. A to Rev. B 7/08—Rev. 0 to Rev. A 5/06—Revision 0: Initial Version

Rev. E | Page 3 of 32 SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply voltages (AVDD, DVDD) 3.3 V Temperature range1 as specified in Table 1 and Table 2 Master clock 12.288 MHz (48 kHz fS, 256 × fS mode) Input sample rate 48 kHz Measurement bandwidth 20 Hz to 20 kHz Word width 24 bits Load capacitance (digital output) 20 pF Load current (digital output) ±1 mA or 1.5 kΩ to ½ DVDD supply Input voltage high 2.0 V Input voltage low 0.8 V 1 Functionally guaranteed at −40°C to +125°C case temperature. ANALOG PERFORMANCE SPECIFICATIONS Specifications guaranteed at an ambient temperature of 25°C. Table 1. Parameter Conditions Min Typ Max Unit ANALOG-TO-DIGITAL CONVERTERS ADC Resolution All ADCs 24 Bits Dynamic Range 20 Hz to 20 kHz, −60 dB input No Filter (RMS) 98 102 dB With A-Weighted Filter (RMS) 100 105 dB Total Harmonic Distortion + Noise −1 dBFS −96 −87 dB Full-Scale Input Voltage (Differential) 1.9 V rms Gain Error −10 +10 % Interchannel Gain Mismatch −0.25 +0.25 dB Offset Error −10 0 +10 mV Gain Drift 100 ppm/°C Interchannel Isolation −110 dB CMRR 100 mV rms, 1 kHz 55 dB 100 mV rms, 20 kHz 55 dB Input Resistance 14 kΩ Input Capacitance 10 pF Input Common-Mode Bias Voltage 1.5 V DIGITAL-TO-ANALOG CONVERTERS Dynamic Range 20 Hz to 20 kHz, −60 dB input No Filter (RMS) 98 104 dB With A-Weighted Filter (RMS) 100 106 dB With A-Weighted Filter (Average) 108 dB Total Harmonic Distortion + Noise 0 dBFS Single-Ended Version Two channels running −92 dB Single-Ended Version Eight channels running −86 −75 dB Full-Scale Output Voltage 0.88 (2.48) V rms (V p-p) Gain Error −10 +10 % Interchannel Gain Mismatch −0.2 +0.2 dB Offset Error −25 −4 +25 mV Gain Drift −30 +30 ppm/°C

Rev. E | Page 4 of 32 Parameter Conditions Min Typ Max Unit Interchannel Isolation 100 dB Interchannel Phase Deviation 0 Degrees Volume Control Step 0.375 dB Volume Control Range 95 dB De-emphasis Gain Error ±0.6 dB Output Resistance at Each Pin 100 Ω REFERENCE Internal Reference Voltage FIL TR pin 1.50 V External Reference Voltage FIL TR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V Specifications measured at a case temperature of 125°C. Table 2. Parameter Conditions Min Typ Max Unit ANALOG-TO-DIGITAL CONVERTERS ADC Resolution All ADCs 24 Bits Dynamic Range 20 Hz to 20 kHz, −60 dB input No Filter (RMS) 95 102 dB With A-Weighted Filter (RMS) 97 105 dB Total Harmonic Distortion + Noise −1 dBFS −96 −87 dB Full-Scale Input Voltage (Differential) 1.9 V rms Gain Error −10 +10 % Interchannel Gain Mismatch −0.25 +0.25 dB Offset Error −10 0 +10 mV DIGITAL-TO-ANALOG CONVERTERS Dynamic Range 20 Hz to 20 kHz, −60 dB input No Filter (RMS) 98 104 dB With A-Weighted Filter (RMS) 100 106 dB With A-Weighted Filter (Average) 108 dB Total Harmonic Distortion + Noise 0 dBFS Single-Ended Version Two channels running −92 dB Single-Ended Version Eight channels running −86 −70 dB Full-Scale Output Voltage 0.8775 (2.482) V rms (V p-p) Gain Error −10 +10 % Interchannel Gain Mismatch −0.2 +0.2 dB Offset Error −25 −4 25 mV Gain Drift −30 30 ppm/°C REFERENCE Internal Reference Voltage FIL TR pin 1.50 V External Reference Voltage FIL TR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V CRYSTAL OSCILLATOR SPECIFICATIONS Table 3. Parameter Min Typ Max Unit Transconductance 3.5 mmhos

Rev. E | Page 5 of 32 DIGITAL INPUT/OUTPUT SPECIFICATIONS Table 4. Parameter Conditions/Comments Min Typ Max Unit High Level Input Voltage (VIH) 2.0 V High Level Input Voltage (VIH) MCLKI/XI pin 2.2 V Low Level Input Voltage (VIL) 0.8 V Input Leakage IIH @ VIH = 2.4 V 10 µA IIL @ VIL = 0.8 V 10 µA High Level Output Voltage (VOH) IOH = 1 mA DVDD − 0.60 V Low Level Output Voltage (VOL) IOL = 1 mA 0.4 V Input Capacitance 5 pF POWER SUPPLY SPECIFICATIONS Table 5. Parameter Conditions/Comments Min Typ Max Unit SUPPLIES Voltage DVDD 3.0 3.3 3.6 V AVDD 3.0 3.3 3.6 V Digital Current Master clock = 256 fS Normal Operation fS = 48 kHz 56 mA fS = 96 kHz 65 mA fS = 192 kHz 95 mA Power-Down fS = 48 kHz to 192 kHz 2.0 mA Analog Current Normal Operation 74 mA Power-Down 23 mA DISSIPATION Operation Master clock = 256 fS, 48 kHz All Supplies 429 mW Digital Supply 185 mW Analog Supply 244 mW Power-Down, All Supplies 83 mW POWER SUPPLY REJECTION RATIO Signal at Analog Supply Pins 1 kHz, 200 mV p-p 50 dB 20 kHz, 200 mV p-p 50 dB

Rev. E | Page 6 of 32 DIGITAL FILTERS Table 6. Parameter Mode Factor Min Typ Max Unit ADC DECIMATION FILTER All modes, typical @ 48 kHz Pass Band 0.4375 fS 21 kHz Pass-Band Ripple ±0.015 dB Transition Band 0.5 fS 24 kHz Stop Band 0.5625 fS 27 kHz Stop-Band Attenuation 79 dB Group Delay 22.9844/fS 479 µs DAC INTERPOLATION FILTER Pass Band 48 kHz mode, typical @ 48 kHz 0.4535 fS 22 kHz 96 kHz mode, typical @ 96 kHz 0.3646 fS 35 kHz 192 kHz mode, typical @ 192 kHz 0.3646 fS 70 kHz Pass-Band Ripple 48 kHz mode, typical @ 48 kHz ±0.01 dB 96 kHz mode, typical @ 96 kHz ±0.05 dB 192 kHz mode, typical @ 192 kHz ±0.1 dB Transition Band 48 kHz mode, typical @ 48 kHz 0.5 fS 24 kHz 96 kHz mode, typical @ 96 kHz 0.5 fS 48 kHz 192 kHz mode, typical @ 192 kHz 0.5 fS 96 kHz Stop Band 48 kHz mode, typical @ 48 kHz 0.5465 fS 26 kHz 96 kHz mode, typical @ 96 kHz 0.6354 fS 61 kHz 192 kHz mode, typical @ 192 kHz 0.6354 fS 122 kHz Stop-Band Attenuation 48 kHz mode, typical @ 48 kHz 70 dB 96 kHz mode, typical @ 96 kHz 70 dB 192 kHz mode, typical @ 192 kHz 70 dB Group Delay 48 kHz mode, typical @ 48 kHz 25/fS 521 µs 96 kHz mode, typical @ 96 kHz 11/fS 115 µs 192 kHz mode, typical @ 192 kHz 8/fS 42 µs

Rev. E | Page 7 of 32 TIMING SPECIFICATIONS Table 7. Parameter Condition Comments Min Max Unit INPUT MASTER CLOCK (MCLK) AND RESET tMH MCLK duty cycle DAC/ADC clock source = PLL clock @ 256 fS, 384 fS, 512 fS, and 768 fS 40 60 % tMH DAC/ADC clock source = direct MCLK @ 512 fS (bypass on-chip PLL) 40 60 % fMCLK MCLK frequency PLL mode, 256 fS reference 6.9 13.8 MHz fMCLK Direct 512 fS mode 27.6 MHz tPDR RST low 15 ns tPDRR RST recovery Reset to active output 4096 tMCLK PLL Lock time MCLK and LR clock input 10 ms 256 fS VCO Clock, Output Duty Cycle, MCLKO/XO Pin 40 60 % SPI PORT See Figure 11 tCCH CCLK high 35 ns tCCL CCLK low 35 ns fCCLK CCLK frequency fCCLK = 1/tCCP, only tCCP shown in Figure 11 10 MHz tCDS CIN setup To CCLK rising 10 ns tCDH CIN hold From CCLK rising 10 ns tCLS CLATCH setup To CCLK rising 10 ns tCLH CLATCH hold From CCLK rising 10 ns tCLH CLATCH high Not shown in Figure 11 10 ns tCOE COUT enable From CCLK falling 30 ns tCOD COUT delay From CCLK falling 30 ns tCOH COUT hold From CCLK falling, not shown in Figure 11 30 ns tCOTS COUT tristate From CCLK falling 30 ns DAC SERIAL PORT See Figure 24 tDBH DBCLK high Slave mode 10 ns tDBL DBCLK low Slave mode 10 ns tDLS DLRCLK setup To DBCLK rising, slave mode 10 ns tDLH DLRCLK hold From DBCLK rising, slave mode 5 ns tDLS DLRCLK skew From DBCLK falling, master mode −8 +8 ns tDDS DSDATA setup To DBCLK rising 10 ns tDDH DSDATA hold From DBCLK rising 5 ns ADC SERIAL PORT See Figure 25 tABH ABCLK high Slave mode 10 ns tABL ABCLK low Slave mode 10 ns tALS ALRCLK setup To ABCLK rising, slave mode 10 ns tALH ALRCLK hold From ABCLK rising, slave mode 5 ns tALS ALRCLK skew From ABCLK falling, master mode −8 +8 ns tABDD ASDATA delay From ABCLK falling 18 ns AUXILIARY INTERFACE tAXDS AAUXDATA setup To AUXBCLK rising 10 ns tAXDH AAUXDATA hold From AUXBCLK rising 5 ns tDXDD DAUXDATA delay From AUXBCLK falling 18 ns tXBH AUXBCLK high 10 ns tXBL AUXBCLK low 10 ns tDLS AUXLRCLK setup To AUXBCLK rising 10 ns tDLH AUXLRCLK hold From AUXBCLK rising 5 ns

characteristics are for a 4-layer board. Table 9. Thermal Resistance

Figure 2. Pin Configuration, 48-Lead LQFP Table 10. Pin Function Descriptions 2 I MCLKI/XI Master Clock Input/Crystal Oscillator Input. 3 O MCLKO/XO Master Clock Output/Crystal Oscillator Output. 5 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 10 I PD/ RST Power-Down Reset (Active Low). 13 I DVDD Digital Power Supply. Connect to digital 3.3 V supply. 16 I DSDATA1 DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/TDM data in. 17 I/O DBCLK Bit Clock for DACs. 18 I/O DLRCLK LR Clock for DACs. 20 O ASDATA1 ADC Serial Data Output 1. Data output from ADC1/TDM ADC data out/TDM data out. 21 I/O ABCLK Bit Clock for ADCs. 22 I/O ALRCLK LR Clock for ADCs. 23 I CIN Control Data Input (SPI). 24 I/O COUT Control Data Output (SPI).

Rev. E | Page 10 of 32 Pin No. In/Out Mnemonic Description 26 I CCLK Control Clock Input (SPI). 27 I CLATCH Latch Input for Control Data (SPI). 28 O OL1 DAC 1 Left Output. 29 O OR1 DAC 1 Right Output. 30 O OL2 DAC 2 Left Output. 31 O OR2 DAC 2 Right Output. 32 I AGND Analog Ground. 33 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 34 I AGND Analog Ground. 35 O F ILTR Voltage Reference Filter Capacitor Connection. Bypass with 10 µF||100 nF to AGND. 36 I AGND Analog Ground. 37 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 38 O CM Common-Mode Reference Filter Capacitor Connection. Bypass with 47 µF||100 nF to AGND. 39 I ADC1LP ADC1 Left Positive Input. 40 I ADC1LN ADC1 Left Negative Input. 41 I ADC1RP ADC1 Right Positive Input. 42 I ADC1RN ADC1 Right Negative Input. 43 I ADC2LP ADC2 Left Positive Input. 44 I ADC2LN ADC2 Left Negative Input. 45 I ADC2RP ADC2 Right Positive Input. 46 I ADC2RN ADC2 Right Negative Input. 47 O LF PLL Loop Filter, Return to AVDD. 48 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.

Rev. E | Page 13 of 32 THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTERS (ADCS) There are four ADC channels in the AD1938 configured as two stereo pairs with differential inputs. The ADCs can operate at a nominal sample rate of 48 kHz, 96 kHz, or 192 kHz. The ADCs include on-board digital antialiasing filters with 79 dB stop- band attenuation and linear phase response, operating at an oversampling ratio of 128 (48 kHz, 96 kHz, and 192 kHz modes). Digital outputs are supplied through two serial data output pins (one for each stereo pair) and a common frame clock (ALRCLK) and bit clock (ABCLK). Alternatively, one of the TDM modes can be used to access up to 16 channels on a single TDM data line. The ADCs must be driven from a differential signal source for best performance. The input pins of the ADCs connect to inter- nal switched capacitors. To isolate the external driving op amp from the glitches caused by the internal switched capacitors, each input pin should be isolated by using a series connected, external, 100 Ω resistor together with a 1 nF capacitor connected from each input to ground. This capacitor must be of high quality, for example, ceramic NPO or polypropylene film. The differential inputs have a nominal common-mode voltage of 1.5 V . The voltage at the common-mode reference pin (CM) can be used to bias external op amps to buffer the input signals (see the Power Supply and Voltage Reference section). The inputs can also be ac-coupled and do not need an external dc bias to CM. A digital high-pass filter can be switched in line with the ADCs under serial control to remove residual dc offsets. It has a 1.4 Hz, 6 dB per octave cutoff at a 48 kHz sample rate. The cutoff frequency scales directly with sample frequency. DIGITAL-TO-ANALOG CONVERTERS (DACS) The AD1938 DAC channels are arranged as single-ended, four stereo pairs giving eight analog outputs for minimum external components. The DACs include on-board digital reconstruction filters with 70 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 4 (48 kHz or 96 kHz modes) or 2 (192 kHz mode). Each channel has its own independently programmable attenuator, adjustable in 255 steps in increments of 0.375 dB. Digital inputs are supplied through four serial data input pins (one for each stereo pair), a common frame clock (DLRCLK), and a bit clock (DBCLK). Alternatively, one of the TDM modes can be used to access up to 16 channels on a single TDM data line. Each output pin has a nominal common-mode dc level of 1.5 V and swings ±1.27 V for a 0 dBFS digital input signal. A single op amp, third-order, external, low-pass filter is recommended to remove high frequency noise present on the output pins. The use of op amps with low slew rate or low bandwidth can cause high frequency noise and tones to fold down into the audio band; therefore, exercise care in selecting these components. The voltage at CM, the common-mode reference pin, can be used to bias the external op amps that buffer the output signals (see the Power Supply and Voltage Reference section). CLOCK SIGNALS The on-chip phase locked loop (PLL) can be selected to reference the input sample rate from either of the LRCLK pins or 256, 384, 512, or 768 times the sample rate, referenced to the 48 kHz mode from the MCLKI/XI pin. The default at power-up is 256 × f S from the MCLKI/XI pin. In 96 kHz mode, the master clock frequency stays at the same absolute frequency; therefore, the actual multiplication rate is divided by 2. In 192 kHz mode, the actual multiplication rate is divided by 4. For example, if a device in the AD193x family is programmed in 256 × fS mode, the frequency of the master clock input is 256 × 48 kHz = 12.288 MHz. If the AD193x is then switched to 96 kHz operation (by writing to the SPI port), the frequency of the master clock should remain at 12.288 MHz, which becomes 128 × f S. In 192 kHz mode, this becomes 64 × fS. The internal clock for the ADCs is 256 × fS for all clock modes. The internal clock for the DACs varies by mode: 512 × fS (48 kHz mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz mode). By default, the on-board PLL generates this internal master clock from an external clock. A direct 512 × fS (referenced to 48 kHz mode) master clock can be used for either the ADCs or DACs if selected in the PLL and Clock Control 1 register. Note that it is not possible to use a direct clock for the ADCs set to the 192 kHz mode. It is required that the on-chip PLL be used in this mode. The PLL can be powered down in the PLL and Clock Control 0 register. To ensure reliable locking when changing PLL modes, or if the reference clock is unstable at power-on, power down the PLL and then power it back up when the reference clock stabilizes. The internal master clock can be disabled in the PLL and Clock Control 0 register to reduce power dissipation when the AD1938 is idle. The clock should be stable before it is enabled. Unless a standalone mode is selected (see the Serial Control Port section), the clock is disabled by reset and must be enabled by writing to the SPI port for normal operation. To maintain the highest performance possible, limit the clock jitter of the internal master clock signal to less than a 300 ps rms time interval error (TIE). Even at these levels, extra noise or tones can appear in the DAC outputs if the jitter spectrum contains large spectral peaks. If the internal PLL is not used, it is best to use an independent crystal oscillator to generate the master clock. In addition, it is especially important that the clock signal not pass through an FPGA, CPLD, or other large digital chip (such as a DSP) before being applied to the AD1938. In most cases, this induces clock jitter due to the sharing of common power and ground connections with other unrelated digital output signals. When the PLL is used, jitter in

depending on the loop filter. lock condition, an initialization routine runs inside the AD1938. This initialization lasts for approximately 256 master clock cycles. ADCs and DACs. Figure 11 shows the format of the SPI signal. Table 11. Standalone Mode Selection Figure 11. Format of SPI Signal

supply pins are provided for the analog and digital sections. All digital inputs are compatible with TTL and CMOS levels. compatible with TTL and 3.3 V CMOS levels. supply voltage. The ADC input gain varies by the inverse ratio. less than 0.5 mA source and 2 mA sink. serial ports are in the slave mode. of each pin in TDM and auxiliary modes, see Table 12. to be easily configured by the use of an auxiliary serial data port. the AUX channels are the last four slots of the TDM data stream. is available only in the 48 kHz/44.1 kHz/32 kHz sample rate. 48 kHz/44.1 kHz/32 kHz sample rate.

256 BCLKs

32 BCLKs

Figure 12. ADC TDM (8-Channel I2S Mode) Figure 13. DAC TDM (8-Channel I2S Mode)

Table 12. Pin Function Changes in TDM-AUX Modes

8 ON-CHIP DAC CHANNELS

32 BITS

Figure 14. 16-Channel AUX DAC Mode

4 ON-CHIP ADC CHANNELS 4 AUX ADC CHANNELS

Figure 15. 8-Channel AUX ADC Mode

4 ON-CHIP ADC CHANNELS AUXILIARY ADC CHANNELS UNUSED SLOTS

Figure 16. 16-Channel AUX ADC Mode

Figure 17. Combined AUX DAC and ADC Mode

AD1938 is the device attached to the DSP TDM port. normally required by the one-line TDM mode. 192 kHz sample rate into the AD1938 as shown in Figure 20. Figure 22. Note that in the 512 f

8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN

8 UNUSED SLOTS

8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN

Figure 18. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two- AD1938 Daisy Chain)

8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN

Figure 19. Dual-Line DAC TDM Mode (Applicable to 96 kHz Sample Rate, 16-Channel, Two-AD1938 Daisy Chain); DSDATA3 and DSDATA4 Are the Daisy Chain Figure 20. Dual-Line DAC TDM Mode (Applicable to 192 kHz Sample Rate, 8-Channel Mode)

4 ADC CHANNELS OF FIRST IC IN THE CHAIN4 ADC CHANNELS OF SECOND IC IN THE CHAIN

Figure 21. ADC TDM Daisy-Chain Mode (256 fS BCLK, Two-AD193x Daisy Chain)

4 ADC CHANNELS OF

Figure 22. ADC TDM Daisy-Chain Mode (512 fS BCLK, Two-AD193x Daisy Chain)

1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE WHICH IS 2 × fS.
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.

Figure 23. Stereo Serial Modes

Table 13. Pin Function Changes in TDM and AUX Modes (Replication of Table 12) Figure 26. Example of AUX Mode Connection to SHARC (AD1938 as TDM Master/AUX Master Shown)

registers that are set to full volume. Note that the first setting in each control register parameter is the default setting. Table 14. Register Format Table 15. Register Addresses and Functions

0 PLL and Clock Control 0

1 PLL and Clock Control 1

2 DAC Control 0

3 DAC Control 1

4 DAC Control 2

5 DAC individual channel mutes

6 DAC L1 volume control

7 DAC R1 volume control

8 DAC L2 volume control

9 DAC R2 volume control

10 DAC L3 volume control

11 DAC R3 volume control

12 DAC L4 volume control

13 DAC R4 volume control

14 ADC Control 0

15 ADC Control 1

16 ADC Control 2

Table 16. PLL and Clock Control Register 0

1 Power-down

11 Off

01 DLRCLK

10 ALRCLK

11 Reserved

1 Enable: ADC and DAC active

Table 17. PLL and Clock Control Register 1

1 MCLK

1 Disabled

1 Locked

Table 18. DAC Control Register 0

101 Reserved

110 Reserved

111 Reserved

01 TDM (daisy chain)

10 DAC AUX mode (ADC-, DAC-, TDM-coupled)

11 Dual-line TDM

Table 19. DAC Control Register 1

1 Latch in at end of cycle (pipeline)

1 Left high

1 Master

1 Internally generated

1 Inverted

Table 20. DAC Control Register 2

1 Mute

10 Reserved

Table 21. DAC Individual Channel Mutes Table 22. DAC Volume Controls

255 Full attenuation

Table 23. ADC Control Register 0

1 Power down

Table 24. ADC Control Register 1

10 ADC AUX mode (ADC-, DAC-, TDM-coupled)

Table 25. ADC Control Register 2

1 Pulse (32 BCLKs per channel)

1 Drive out on rising edge

by the PLL with the DLRCLK as the PLL reference frequency. Figure 27. Serial DAC Data Transmission in TDM Format Without DBCLK Figure 28. I2S Pipeline Mode in DAC Serial Data Transmission (Applicable in Stereo and TDM, Useful for High Frequency TDM Transmission.

Figure 31 and Figure 32 for the noninverting and inverting cases.

3 OP275

5 OP275

Figure 29. Typical ADC Input Filter Circuit Figure 30. Recommended Loop Filters for LRCLK and MCLK PLL Reference

2 OP275

Figure 31. Typical DAC Output Filter Circuit (Single-Ended, Noninverting) Figure 32. Typical DAC Output Filter Circuit (Single-Ended, Inverting)

Figure 33. 48-Lead Low Profile Quad Flat Package [LQFP] 2 For the AD1938YSTZ, AD1938YSTZRL, AD1938WBSTZ, and AD1938WBSTZ-RL: single-ended output; SPI control port. 3 W = Qualified for Automotive Applications. ordering information and to obtain the specific Automotive Reliability reports for these models.

Rev. E | Page 32 of 32 NOTES ©2006–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05582-0-2/13(E)