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8-Channel DAC with PLL and Single-Ended Outputs, 192 kHz, 24 Bits Data Sheet AD1934 Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 © 2007–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
PLL generated or direct master clock Low EMI design 108 dB DAC dynamic range and SNR −94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates Single-ended DAC output Log volume control with autoramp function SPI® controllable for flexibility Software-controllable clickless mute Software power-down Right-justified, left-justified, I2S, and TDM modes Master and slave modes up to 16-channel in/out 48-lead LQFP Qualified for automotive applications
APPLICATIONS
Digital audio effects processors GENERAL DESCRIPTION The AD1934 is a high performance, single chip that provides eight digital-to-analog converters (DACs) with single-ended output using the Analog Devices, Inc., patented multibit sigma- delta (Σ-Δ) architecture. An SPI port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1934 operates from 3.3 V digital and analog supplies. The AD1934 is available in a 48-lead (single-ended output) L Q F P. Other members of this family include a differential DAC output version. The AD1934 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the master clock from the LR clock or from an external crystal, the AD1934 eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The DACs are designed using the latest Analog Devices continuous time architectures to further minimize EMI. By using 3.3 V supplies, power consumption is minimized, further reducing emissions. FUNCTIONAL BLOCK DIAGRAM 06106-001 SERIAL DATA PORT PRECISION VOLTAGE REFERENCE TIMING MANAGEMENT AND CONTROL (CLOCK AND PLL) CONTROL PORT SPI CONTROL DATA INPUT/OUTPUT AD1934 DIGITAL AUDIO INPUT/OUTPUT SDATAIN CLOCKS ANALOG AUDIO OUTPUTS 6.144MHz DAC DAC DAC DAC DAC DAC DAC DAC DIGITAL FILTER AND VOLUME CONTROL Figure 1.
Rev. D | Page 2 of 29 TABLE OF CONTENTS
REVISION HISTORY
2/13—Rev. C to Rev. D 7/11—Rev. B to Rev. C Changes to Figure 2 and Table 10, DSDATAx/AUXDATA1 Pin 1/11—Rev. A to Rev. B 9/09—Rev. 0 to Rev. A 8/07—Revision 0: Initial Version
Rev. D | Page 3 of 28 SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply Voltages (AVDD, DVDD) 3.3 V Temperature Range1 As specified in Table 1 and Table 2 Master Clock 12.288 MHz (48 kHz fS, 256 × fS mode) Input Sample Rate 48 kHz Measurement Bandwidth 20 Hz to 20 kHz Word Width 24 bits Load Capacitance (Digital Output) 20 pF Load Current (Digital Output) ±1 mA or 1.5 kΩ to ½ DVDD supply Input Voltage HI 2.0 V Input Voltage LO 0.8 V 1 Functionally guaranteed at −40°C to +125°C case temperature. ANALOG PERFORMANCE SPECIFICATIONS Specifications guaranteed at 25°C (ambient). Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DIGITAL-TO-ANALOG CONVERTERS Dynamic Range 20 Hz to 20 kHz, −60 dB input No Filter (RMS) 98 104 dB With A-Weighted Filter (RMS) 100 106 dB With A-Weighted Filter (Average) 108 dB Total Harmonic Distortion + Noise 0 dBFS Single-Ended Version Two channels running −92 dB Eight channels running −86 −75 dB Full-Scale Output Voltage 0.88 (2.48) V rms (V p-p) Gain Error −10 +10 % Interchannel Gain Mismatch −0.2 +0.2 dB Offset Error −16 −4 +16 mV Gain Drift −30 +30 ppm/°C Interchannel Isolation 100 dB Interchannel Phase Deviation 0 Degrees Volume Control Step 0.375 dB Volume Control Range 95 dB De-emphasis Gain Error ±0.6 dB Output Resistance at Each Pin 100 Ω REFERENCE Internal Reference Voltage FIL TR pin 1.50 V External Reference Voltage FIL TR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V
Rev. D | Page 4 of 28 Specifications measured at 125°C (case). Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DIGITAL-TO-ANALOG CONVERTERS Dynamic Range 20 Hz to 20 kHz, −60 dB input No Filter (RMS) 98 104 dB With A-Weighted Filter (RMS) 100 106 dB With A-Weighted Filter (Average) 108 dB Total Harmonic Distortion + Noise 0 dBFS Single-Ended Version Two channels running −92 dB Eight channels running −86 −70 dB Full-Scale Output Voltage 0.8775 (2.482) V rms (V p-p) Gain Error −10 +10 % Interchannel Gain Mismatch −0.2 +0.2 dB Offset Error −16 −4 +16 mV Gain Drift −30 +30 ppm/°C REFERENCE Internal Reference Voltage FILTR pin 1.50 V External Reference Voltage FILTR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V CRYSTAL OSCILLATOR SPECIFICATIONS Table 3. Parameter Min Typ Max Unit Transconductance 3.5 mmhos DIGITAL INPUT/OUTPUT SPECIFICATIONS Table 4. Parameter Test Conditions/Comments Min Typ Max Unit Input Voltage HI (VIH) 2.0 V Input Voltage HI (VIH) MCLKI pin 2.2 V Input Voltage LO (VIL) 0.8 V Input Leakage IIH @ VIH = 2.4 V 10 μA I IL @ VIL = 0.8 V 10 μA High Level Output Voltage (VOH) IOH = 1 mA DVDD − 0.60 V Low Level Output Voltage (VOL) IOL = 1 mA 0.4 V Input Capacitance 5 pF
Rev. D | Page 5 of 28 POWER SUPPLY SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit SUPPLIES Voltage DVDD 3.0 3.3 3.6 V AVDD 3.0 3.3 3.6 V Digital Current MCLK = 256 fS Normal Operation fS = 48 kHz 56 mA fS = 96 kHz 65 mA fS = 192 kHz 95 mA Power-Down fS = 48 kHz to 192 kHz 2.0 mA Analog Current Normal Operation 74 mA Power-Down 23 mA DISSIPATION Operation MCLK = 256 fS, 48 kHz All Supplies 429 mW Digital Supply 185 mW Analog Supply 244 mW Power-Down, All Supplies 83 mW POWER SUPPLY REJECTION RATIO Signal at Analog Supply Pins 1 kHz, 200 mV p-p 50 dB 20 kHz, 200 mV p-p 50 dB
Rev. D | Page 6 of 28 DIGITAL FILTERS Table 6. Parameter Mode Factor Min Typ Max Unit DAC INTERPOLATION FILTER Pass Band 48 kHz mode, typ @ 48 kHz 0.4535 fS 22 kHz 96 kHz mode, typ @ 96 kHz 0.3646 fS 35 kHz 192 kHz mode, typ @ 192 kHz 0.3646 fS 70 kHz Pass-Band Ripple 48 kHz mode, typ @ 48 kHz ±0.01 dB 96 kHz mode, typ @ 96 kHz ±0.05 dB 192 kHz mode, typ @ 192 kHz ±0.1 dB Transition Band 48 kHz mode, typ @ 48 kHz 0.5 fS 24 kHz 96 kHz mode, typ @ 96 kHz 0.5 fS 48 kHz 192 kHz mode, typ @ 192 kHz 0.5 fS 96 kHz Stop Band 48 kHz mode, typ @ 48 kHz 0.5465 fS 26 kHz 96 kHz mode, typ @ 96 kHz 0.6354 fS 61 kHz 192 kHz mode, typ @ 192 kHz 0.6354 fS 122 kHz Stop-Band Attenuation 48 kHz mode, typ @ 48 kHz 70 dB 96 kHz mode, typ @ 96 kHz 70 dB 192 kHz mode, typ @ 192 kHz 70 dB Group Delay 48 kHz mode, typ @ 48 kHz 25/fS 521 µs 96 kHz mode, typ @ 96 kHz 11/fS 115 µs 192 kHz mode, typ @ 192 kHz 8/fS 42 µs TIMING SPECIFICATIONS Table 7. Parameter Condition Comments Min Max Unit INPUT MASTER CLOCK (MCLK) AND RESET tMH MCLK duty cycle DAC clock source = PLL clock @ 256 fS, 384 fS, 512 fS, 768 fS 40 60 % tMH DAC clock source = direct MCLK @ 512 fS (bypass on-chip PLL) 40 60 % fMCLK MCLK frequency PLL mode, 256 fS reference 6.9 13.8 MHz fMCLK Direct 512 fS mode 27.6 MHz tPDR RST low 15 ns tPDRR RST recovery Reset to active output 4096 tMCLK PLL Lock Time MCLK and LRCLK input 10 ms 256 fS VCO Clock, Output Duty Cycle MCLKO Pin 40 60 % SPI PORT See Figure 9 tCCH CCLK high 35 ns tCCL CCLK low 35 ns fCCLK CCLK frequency fCCLK = 1/tCCP, only tCCP shown in Figure 9 10 MHz tCDS CDATA setup To CCLK rising 10 ns tCDH CDATA hold From CCLK rising 10 ns tCLS CLATCH setup To CCLK rising 10 ns tCLH CLATCH hold From CCLK rising 10 ns tCLHIGH CLATCH high Not shown in Figure 9 10 ns tCOE COUT enable From CCLK falling 30 ns tCOD COUT delay From CCLK falling 30 ns tCOH COUT hold From CCLK falling, not shown in Figure 9 30 ns tCOTS COUT tri-state From CCLK falling 30 ns
Rev. D | Page 7 of 28 Parameter Condition Comments Min Max Unit DAC SERIAL PORT See Figure 16 tDBH DBCLK high Slave mode 10 ns tDBL DBCLK low Slave mode 10 ns tDLS DLRCLK setup To DBCLK rising, slave mode 10 ns tDLH DLRCLK hold From DBCLK rising, slave mode 5 ns tDLS DLRCLK skew From DBCLK falling, master mode −8 +8 ns tDDS DSDATA setup To DBCLK rising 10 ns tDDH DSDATA hold From DBCLK rising 5 ns AUXTDM SERIAL PORT See Figure 17 tABH AUXTDMBCLK high Slave mode 10 ns tABL AUXTDMBCLK low Slave mode 10 ns tALS AUXTDMLRCLK setup To AUXTDMBCLK rising, slave mode 10 ns tALH AUXTDMLRCLK hold From AUXTDMBCLK rising, slave mode 5 ns tALS AUXTDMLRCLK skew From AUXTDMBCLK falling, master mode −8 +8 ns tDDS DSDATA setup To AUXTDMBCLK, not shown in Figure 17 10 ns tDDH DSDATA hold From AUXTDMBCLK rising, not shown in Figure 17 5 ns AUXILIARY INTERFACE tDXDD AUXDATA delay From AUXBCLK falling 18 ns tXBH AUXBCLK high 10 ns tXBL AUXBCLK low 10 ns tDLS AUXLRCLK setup To AUXBCLK rising 10 ns tDLH AUXLRCLK hold From AUXBCLK rising 5 ns
θJC represents the thermal resistance, junction-to-case. All characteristics are for a 4-layer board. Table 9. Thermal Resistance
Figure 2. Pin Configuration Table 10. Pin Function Description 2 I MCLKI/XI Master Clock Input/Crystal Oscillator Input. 3 O MCLKO/XO Master Clock Output/Crystal Oscillator Output. 5 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 10 I PD/ RST Power-Down Reset (Active Low). mode)/AUX DAC2 data out (to external DAC2). 13 I DVDD Digital Power Supply. Connect to digital 3.3 V supply. 15 I/O DSDATA2 DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC2 data out/AUX not used. 16 I DSDATA1 DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/AUX TDM data in. 17 I/O DBCLK Bit Clock for DACs (Regular Stereo, TDM, or Daisy-Chain TDM Mode). 18 I/O DLRCLK LR Clock for DACs (Regular Stereo, TDM, or Daisy-Chain TDM Mode). 19 O AUXDATA1 AUX DAC1 data out (to external DAC1). 21 I/O AUXTDMBCLK Auxiliary Mode Only DAC TDM Bit Clock. 22 I/O AUXTDMLRCLK Auxiliary Mode Only DAC LR TDM Clock. 23 I CIN/ADR0 Control Data Input (SPI). 24 I/O COUT/SDA Control Data Output (SPI).
Rev. D | Page 10 of 28 Pin No. Input/Output Mnemonic Description 26 I CCLK/SCL Control Clock Input (SPI). 27 I CLATCH/ADR1 Latch Input for Control Data (SPI). 28 O OL1 DAC 1 Left Output. 29 O OR1 DAC 1 Right Output. 30 O OL2 DAC 2 Left Output. 31 O OR2 DAC 2 Right Output. 32 I AGND Analog Ground. 33 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 34 I AGND Analog Ground. 35 O F ILTR Voltage Reference Filter Capacitor Connection. Bypass with 10 µF||100 nF to AGND. 36 I AGND Analog Ground. 37 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 38 O CM Common-Mode Reference Filter Capacitor Connection. Bypass with 47 µF||100 nF to AGND. 39 to 46 NC Must Be Tied to Common Mode, Pin 38. Alternately, ac-coupled to ground. 47 O LF PLL Loop Filter. Return to AVDD. 48 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.
Rev. D | Page 12 of 28 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTERS (DACs) The AD1934 DAC channels are arranged as single-ended, four stereo pairs giving eight analog outputs for minimum external components. The DACs include on-board digital reconstruction filters with 70 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 4 (48 kHz or 96 kHz modes) or 2 (192 kHz mode). Each channel has its own independently programmable attenuator, adjustable in 255 steps in increments of 0.375 dB. Digital inputs are supplied through four serial data input pins (one for each stereo pair) and a common frame (DLRCLK) and bit (DBCLK) clock. Alternatively, one of the TDM modes can be used to access up to 16 channels on a single TDM data line. Each output pin has a nominal common-mode dc level of 1.5 V and swings ±1.27 V for a 0 dBFS digital input signal. A single op amp, third-order, external, low-pass filter is recommended to remove high frequency noise present on the output pins. The use of op amps with low slew rate or low bandwidth can cause high frequency noise and tones to fold down into the audio band; therefore, exercise care in selecting these components. The voltage at CM, the common-mode reference pin, can be used to bias the external op amps that buffer the output signals (see the Power Supply and Voltage Reference section). CLOCK SIGNALS The on-chip phase locked loop (PLL) can be selected to reference the input sample rate from either of the LRCLK pins or 256, 384, 512, or 768 times the sample rate, referenced to the 48 kHz mode from the MCLKI pin. The default at power-up is 256 × f S from MCLKI pin. In 96 kHz mode, the master clock frequency stays at the same absolute frequency; therefore, the actual multiplication rate is divided by 2. In 192 kHz mode, the actual multiplication rate is divided by 4. For example, if a device in the AD1934 family is programmed in 256 × fS mode, the frequency of the master clock input is 256 × 48 kHz = 12.288 MHz. If the AD1934 is then switched to 96 kHz operation (by writing to the SPI port), the frequency of the master clock should remain at 12.288 MHz, which is now 128 × f S. In 192 kHz mode, this becomes 64 × fS. The internal clock for the DACs varies by mode: 512 × fS (48 kHz mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz mode). By default, the on-board PLL generates this internal master clock from an external clock. A direct 512 × fS (referenced to 48 kHz mode) master clock can be used for DACs if selected in PLL and Clock Control 1 Register. The PLL can be powered down in PLL and Clock Control 0 Register. To ensure reliable locking when changing PLL modes, or if the reference clock is unstable at power-on, power down the PLL and then power it back up when the reference clock has stabilized. The internal MCLK can be disabled in PLL and Clock Control 0 Register to reduce power dissipation when the AD1934 is idle. The clock should be stable before it is enabled. Unless a stand- alone mode is selected (see the Serial Control Port section), the clock is disabled by reset and must be enabled by writing to the SPI port for normal operation. To maintain the highest performance possible, it is recommended that the clock jitter of the internal master clock signal be limited to less than 300 ps rms time interval error (TIE). Even at these levels, extra noise or tones can appear in the DAC outputs if the jitter spectrum contains large spectral peaks. If the internal PLL is not being used, it is highly recommended that an independent crystal oscillator generate the master clock. In addition, it is especially important that the clock signal not be passed through an FPGA, CPLD, or other large digital chip (such as a DSP) before being applied to the AD1934. In most cases, this induces clock jitter due to the sharing of common power and ground connections with other unrelated digital output signals. When the PLL is used, jitter in the reference clock is attenuated above a certain frequency depending on the loop filter. RESET AND POWER-DOWN Reset sets all the control registers to their default settings. To avoid pops, reset does not power down the analog outputs. After reset is deasserted, and the PLL acquires lock condition, an initialization routine runs inside the AD1934. This initialization lasts for approximately 256 MCLKs. The power-do wn bits in the PLL and Clock Control 0 and DAC Control 1 registers power down the respective sections. All other register settings are retained. To guarantee proper startup, the reset pin should be pulled low by an external resistor.
Table 11. SPI vs. Standalone Mode Configuration Figure 9. Format of SPI Signal
supply pins are provided for the analog and digital sections. All digital inputs are compatible with TTL and CMOS levels. compatible with TTL and 3.3 V CMOS levels. current drawn should be limited to less than 50 μA. level of a power amplifier based on its power supply voltage. less than 0.5 mA source and 2 mA sink. rate. The normal stereo serial modes are shown in Figure 15. programmed for left-justified, right-justified, and TDM modes. DLRCLK and DBCLK pins are used as the TDM port clocks. DAC serial ports are in the slave mode. packed into one TDM stream. In this mode, DBCLK is 256 fS. of each pin in TDM and AUX Modes, see Table 12. to be easily configured by the use of an auxiliary serial data port. available only in the 48 kHz/44.1 kHz/32 kHz sample rate.
256 BCLKs
32 BCLK
Figure 10. DAC TDM (8-Channel I2S Mode)
Table 12. Pin Function Changes in TDM and AUX Modes
32 BITS
Figure 11. 16-Channel DAC TDM-AUX Mode
device attached to the DSP TDM port. normally required by the one-line TDM mode. a 192 kHz sample rate into the AD1934, as shown in Figure 14. flexibility, the polarity of LRCLK and BCLK are programmable.
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
8 UNUSED SLOTS
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
Figure 12. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two AD1934 Daisy Chain)
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
Figure 13. Dual-Line, DAC TDM Mode (Applicable to 96 kHz Sample Rate, 16-Channel, Two AD1934 Daisy Chain; DSDATA3 and DSDATA4 A re the Daisy Chain)
Figure 14. Dual-Line, DAC TDM Mode (Applicable to 192 kHz Sample Rate, 8-Channel Mode)
- DSP MODE DOES NOT IDENTIFY CHANNEL.
- LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE, WHICH IS 2 × fS.
- BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 15. Stereo Serial Modes
Table 13. Pin Function Changes in TDM and AUX Modes (Replication of Table 12) Figure 18. Example of AUX Mode Connection to SHARC® (AD1934 as TDM Master/AUX Master Shown)
registers that are set to full volume. Note that the first setting in each control register parameter is the default setting. Table 14. Register Format Table 15. Register Addresses and Functions
0 PLL and Clock Control 0
1 PLL and Clock Control 1
2 DAC Control 0
3 DAC Control 1
4 DAC Control 2
5 DAC individual channel mutes
6 DAC 1L volume control
7 DAC 1R volume control
8 DAC 2L volume control
9 DAC 2R volume control
10 DAC 3L volume control
11 DAC 3R volume control
12 DAC 4L volume control
13 DAC 4R volume control
14 Reserved
15 Auxiliary TDM Port Control 0
16 Auxiliary TDM Port Control 1
Table 16. PLL and Clock Control 0
1 Power-down
11 Off
01 DLRCLK
10 AUXTDMLRCLK
11 Reserved
1 Enable: DAC active
Table 17. PLL and Clock Control 1
1 MCLK
1 Disabled
1 Locked
Table 18. DAC Control 0
101 Reserved
110 Reserved
111 Reserved
01 TDM (daisy chain)
10 DAC aux mode (DAC-, TDM-coupled)
11 Dual-line TDM
Table 19. DAC Control 1
1 Latch in at end of cycle (pipeline)
1 Left high
1 Master
1 Internally generated
1 Inverted
Table 20. DAC Control 2
1 Mute
10 Reserved
Table 21. DAC Individual Channel Mutes Table 22. DAC Volume Controls
255 Full attenuation
Table 23. Auxiliary TDM Control 0
01 Reserved
10 DAC aux mode
Table 24. Auxiliary TDM Control 1
1 Pulse (32 BCLK/channel)
1 Drive out on rising edge
PLL with the DLRCLK as the PLL reference frequency. effectively dedicates the entire BCLK period to the setup time. Both the BLCK-less and pipeline modes are available.
Figure 19. Serial DAC Data Transmission in TDM Format Without DBCLK (Applicable Only If PLL Locks to DLRCLK) Figure 20. I2S Pipeline Mode in DAC Serial Data Transmission (Applicable in Stereo and TDM Useful for High Frequency TDM Transmission)
master clock as the PLL reference are shown in Figure 21. Figure 23 for the noninverting and inverting cases, respectively. Figure 21. Recommended Loop Filters for LRCLK or MCLK PLL Reference
2 OP275
Figure 22. Typical DAC Output Filter Circuit (Single-Ended, Noninverting)
3 OP275
Figure 23. Typical DAC Output Filter Circuit (Single-Ended, Inverting)
Figure 24. 48-Lead Low Profile Quad Flat Package [LQFP] 2 W = Qualified for Automotive Applications. ordering information and to obtain the specific Automotive Reliability reports for these models.
Rev. D | Page 27 of 28 NOTES
Rev. D | Page 28 of 28 NOTES ©2007–2013 Analog Devices, Inc. All rights reserved. Trademark s and registered trademarks are the property of their respective owners. D06106-0-2/13(D)