AD1674KR

AD1674JRZ AD | Alldatasheet

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2.5k 2.5k AD1674 AGND BIP OFF REF IN 20VIN 10VIN IDAC CONTROL CE CS R/C A 0 10k /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines SAR /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines CLOCK /LiteDiagLines /LiteDiagLines 10V REF /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines REGISTERS / 3-STATE OUTPUT BUFFERS DAC STS DB11 (MSB) DB0 (LSB) REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a 12-Bit 100 kSPS A/D Converter AD1674* Tel: 617/329-4700 Fax: 617/326-8703

FEATURES

Complete Monolithic 12-Bit 10 ms Sampling ADC On-Board Sample-and-Hold Amplifier Industry Standard Pinout 8- and 16-Bit Microprocessor Interface AC and DC Specified and Tested Unipolar and Bipolar Inputs

65 V, 610 V, 0 V–10 V, 0 V–20 V Input Ranges

Commercial, Industrial and Military Temperature Range Grades MIL-STD-883 and SMD Compliant Versions Available PRODUCT DESCRIPTION The AD1674 is a complete, multipurpose, 12-bit analog-to- digital converter, consisting of a user-transparent onboard sample-and-hold amplifier (SHA), 10 volt reference, clock and three-state output buffers for microprocessor interface. The AD1674 is pin compatible with the industry standard AD574A and AD674A, but includes a sampling function while delivering a faster conversion rate. The on-chip SHA has a wide input bandwidth supporting 12-bit accuracy over the full Nyquist bandwidth of the converter. The AD1674 is fully specified for ac parameters (such as S/(N+D) ratio, THD, and IMD) and dc parameters (offset, full-s cale error, etc.). With both ac and dc specifications, the AD1674 is ideal for use in signal processing and traditional dc measure- ment applications. The AD1674 design is implemented using Analog Devices’ BiMOS II process allowing high performance bipolar analog cir- cuitry to be combined on the same die with digital CMOS logic. Five different temperature grades are available. The AD1674J and K grades are specified for operation over the 0 °C to +70°C temperature range. The A and B grades are specified from –40°C to +85°C; the AD1674T grade is specified from –55 °C to +125°C. The J and K grades are available in both 28-lead plastic DIP and SOIC. The A and B grade devices are available in 28-lead hermetically sealed ceramic DIP and 28-lead SOIC. The T grade is available in 28-lead hermetically sealed ceramic DIP. *Protected by U. S. Patent Nos. 4,962,325; 4,250,445; 4,808,908; RE30586 . PRODUCT HIGHLIGHTS 1. Industry Standard Pinout: The AD1674 utilizes the pinout established by the industry standard AD574A and AD674A. 2. Integrated SHA: The AD1674 has an integrated SHA which supports the full Nyquist bandwidth of the converter. The SHA function is transparent to the user; no wait-states are needed for SHA acquisition. 3. DC and AC Specified: In addition to traditional dc specifica- tions, the AD1674 is also fully specified for frequency do- main ac parameters such as total harmonic distortion, signal-to-noise ratio and input bandwidth. These parameters can be tested and guaranteed as a result of the onboard SHA. 4. Analog Operation: The precision, laser-trimmed scaling and bipolar offset resistors provide four calibrated ranges:

0 V to +10 V and 0 V to +20 V unipolar, –5 V to +5 V and

–10 V to +10 V bipolar. The AD1674 operates on +5 V and ± 12 V or ± 15 V power supplies. 5. Flexible Digital Interface: On-chip multiple-mode three-state output buffers and interface logic allow direct connection to most microprocessors.

AD1674–SPECIFICATIONS DC SPECIFICATIONS AD1674J AD1674K Parameter Min Typ Max Min Typ Max Unit RESOLUTION 12 12 Bits INTEGRAL NONLINEARITY (INL) ± 1 ± 1/2 LSB DIFFERENTIAL NONLINEARITY (DNL) (No Missing Codes) 12 12 Bits UNIPOLAR OFFSET 1 @ +25°C ± 3 ± 2 LSB BIPOLAR OFFSET1 @ +25°C ± 6 ± 4 LSB FULL-SCALE ERROR 1, 2 @ +25°C (with Fixed 50 Ω Resistor from REF OUT to REF IN) 0.1 0.25 0.1 0.25 % of FSR TEMPERATURE RANGE 0 +70 0 +70 °C TEMPERATURE DRIFT 3 Unipolar Offset 2 ± 2 ± 1 LSB Bipolar Offset 2 ± 2 ± 1 LSB Full-Scale Error 2 ± 6 ± 3 LSB POWER SUPPLY REJECTION VCC = 15 V ± 1.5 V or 12 V ± 0.6 V ± 2 ± 1 LSB VLOGIC = 5 V ± 0.5 V ± 1/2 ± 1/2 LSB VEE = –15 V ± 1.5 V or –12 V ± 0.6 V ± 2 ± 1 LSB ANALOG INPUT Input Ranges Bipolar –5 +5 –5 +5 Volts –10 +10 –10 +10 Volts Unipolar 0 +10 0 +10 Volts 0 +20 0 +20 Volts Input Impedance

10 Volt Span 357357 k Ω

20 Volt Span 6 10 14 6 10 14 k Ω

VLOGIC +4.5 +5.5 +4.5 +5.5 Volts VCC +11.4 +16.5 +11.4 +16.5 Volts VEE –16.5 –11.4 –16.5 –11.4 Volts Operating Current ILOGIC 58 58 m A ICC 10 14 10 14 mA IEE 14 18 14 18 mA POWER DISSIPATION 385 575 385 575 mW Output Current (Available for External Loads) 4 2.0 2.0 mA (External Load Should Not Change During Conversion NOTES 1Adjustable to zero. 2Includes internal voltage reference error. 3Maximum change from 25 °C value to the value at T MIN or TMAX. 4Reference should be buffered for ± 12 V operation. All min and max specifications are guaranteed. Specifications subject to change without notice. REV. C–2– (TMIN to TMAX, VCC = +15 V 6 10% or +12 V 6 5%, VLOGIC = +5 V 6 10%, VEE = –15 V 6 10% or –12 V 6 5% unless otherwise noted)

REV. C –3– AD1674 AD1674A AD1674B AD1674T Parameter Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 12 12 12 Bits INTEGRAL NONLINEARITY (INL) ± 1 ± 1/2 ± 1/2 LSB ± 1 ± 1/2 ± 1 LSB DIFFERENTIAL NONLINEARITY (DNL) (No Missing Codes) 12 12 12 Bits UNIPOLAR OFFSET 1 @ +25°C ± 2 ± 2 ± 2 LSB BIPOLAR OFFSET1 @ +25°C ± 6 ± 3 ± 3 LSB FULL-SCALE ERROR 1, 2 @ +25°C TEMPERATURE RANGE –40 +85 –40 +85 –55 +125 °C TEMPERATURE DRIFT 3 Unipolar Offset 2 ± 2 ± 1 ± 1 LSB Bipolar Offset2 ± 2 ± 1 ± 2 LSB Full-Scale Error 2 ± 8 ± 5 ± 7 LSB POWER SUPPLY REJECTION VCC = 15 V ± 1.5 V or 12 V ± 0.6 V ± 2 ± 1 ± 1 LSB VLOGIC = 5 V ± 0.5 V ± 1/2 ± 1/2 ± 1/2 LSB VEE = –15 V ± 1.5 V or –12 V ± 0.6 V ± 2 ± 1 ± 1 LSB ANALOG INPUT Input Ranges Bipolar –5 +5 –5 +5 –5 +5 Volts –10 +10 –10 +10 –10 +10 Volts Unipolar 0 +10 0 +10 0 +10 Volts 0 +20 0 +20 0 +20 Volts Input Impedance

10 Volt Span 357357357 k Ω

20 Volt Span 6 10 14 6 10 14 6 10 14 k Ω

POWER DISSIPATION 385 575 385 575 385 575 mW Output Current (Available for External Loads) 4 2.0 2.0 2.0 mA (External Load Should Not Change During Conversion

AD1674–SPECIFICATIONS AC SPECIFICATIONS AD1674J/A AD1674K/B/T Parameter Min Typ Max Min Typ Max Units Signal to Noise and Distortion (S/N+D) Ratio 2, 3 69 70 70 71 dB Total Harmonic Distortion (THD) 4 –90 –82 –90 –82 dB 0.008 0.008 % Peak Spurious or Peak Harmonic Component –92 –82 –92 –82 dB Full Power Bandwidth 1 1 MHz Full Linear Bandwidth 500 500 kHz Intermodulation Distortion (IMD) Second Order Products –90 –80 –90 –80 dB Third Order Products –90 –80 –90 –80 dB SHA (Specifications are Included in Overall Timing Specifications) Aperture Delay 50 50 ns Aperture Jitter 250 250 ps Acquisition Time 1 1 µs DIGITAL SPECIFICATIONS Parameter Test Conditions Min Max Units LOGIC INPUTS VIH High Level Input Voltage +2.0 V LOGIC +0.5 V V VIL Low Level Input Voltage –0.5 +0.8 V IIH High Level Input Current (V IN = 5 V) V IN = VLOGIC –10 +10 µA IIL Low Level Input Current (V IN = 0 V) V IN = 0 V –10 +10 µA CIN Input Capacitance 10 pF LOGIC OUTPUTS VOH High Level Output Voltage I OH = 0.5 mA +2.4 V VOL Low Level Output Voltage I OL = 1.6 mA +0.4 V IOZ High-Z Leakage Current V IN = 0 to VLOGIC –10 +10 µA COZ High-Z Output Capacitance 10 pF NOTES 1fIN amplitude = –0.5 dB (9.44 V p-p) 10 V bipolar mode unless otherwise noted. All measurements referred to –0 dB (9.997 V p-p) input signal unless otherwise noted. 2Specified at worst case temperatures and supplies after one minute warm-up. 3See Figures 12 and 13 for other input frequencies and amplitudes. 4See Figure 11. 5fa = 9.08 kHz, fb = 9.58 kHz with f SAMPLE = 100 kHz. See Definition of Specifications section and Figure 15. All min and max specifications are guaranteed. Specifications subject to change without notice. –4– REV. C (TMIN to TMAX, with VCC = +15 V 6 10% or +12 V 6 5%, VLOGIC = +5 V 6 10%, VEE = –15 V 610% or –12 V 6 5%, fSAMPLE = 100 kSPS, fIN = 10 kHz, stand-alone mode unless otherwise noted) 1 (for all grades TMIN to TMAX, with VCC = +15 V 6 10% or +12 V 6 5%, VLOGIC = +5 V 6 10%, VEE = –15 V 6 10% or –12 V 6 5%)

REV. C –7– PIN DESCRIPTION Symbol Pin No. Type Name and Function AGND 9 P Analog Ground (Common). A0 4 DI Byte Address/Short Cycle. If a conversion is started with A0 Active LOW, a full 12-bit conversion cycle is initiated. If A 0 is Active HIGH during a convert start, a shorter 8-bit conversion cycle results. During Read (R/ C = 1) with 12/8 LOW, A0 = LOW enables the 8 most significant bits (DB4–DB11), and A0 = HIGH enables DB3–DB0 and sets DB7–DB4 = 0. BIP OFF 12 AI Bipolar Offset. Connect t hrough a 50 Ω resistor to REF OUT for bipolar operation or to Analog Common for unipolar operation. CE 6 DI Chip Enable. Chip Enable is Active HIGH and is used to initiate a convert or read operation. CS 3 DI Chip Select. Chip Select is Active LOW. DB11–DB8 27–24 DO Data Bits 11 through 8. In the 12-bit format (see 12/ 8 and A0 pins), these pins provide the up- per 4 bits of data. In the 8-bit format, they provide the upper 4 bits when A 0 is LOW and are disabled when A0 is HIGH. DB7–DB4 23–20 DO Data Bits 7 through 4. In the 12-bit format these pins provide the middle 4 bits of data. In the 8-bit format they provide the middle 4 bits when Ao is LOW and all zeroes when A 0 is HIGH. DB3–DB0 19–16 DO Data Bits 3 through 0. In the 12-bit format these pins provide the lower 4 bits of data. In the 8-bit format these pins provide the lower 4 bits of data when A 0 is HIGH, they are disabled when A0 is LOW. DGND 15 P Digital Ground (Common). REF OUT 8 AO +10 V Reference Output. C 5 DI Read/Convert. In the full control mode R/C is Active HIGH for a read operation and Active LOW for a convert operation. In the stand-alone mode, the falling edge of R/ C initiates a conversion. REF IN 10 AI Reference Input is connected through a 50 Ω resistor to +10 V Reference for normal operation. STS 28 DO Status is Active HIGH when a conversion is in progress and goes LOW when the conversion is completed. VCC 7 P +12 V/+15 V Analog Supply. VEE 11 P –12 V/–15 V Analog Supply. VLOGIC 1 P +5 V Logic Supply. 10 VIN 13 AI 10 V Span Input, 0 V to +10 V unipolar mode or –5 V to +5 V bipolar mode. When using the AD1674 in the 20 V Span 10 V IN should not be connected. 20 VIN 14 AI 20 V Span Input, 0 V to +20 V unipolar mode or –10 V to +10 V bipolar mode. When using the AD1674 in the 10 V Span 20 V IN should not be connected. 12/8 2 DI The 12/ 8 pin determines whether the digital output data is to be organized as two 8-bit words (12/8 LOW) or a single 12-bit word (12/ 8 HIGH). TYPE: AI = Analog Input AO = Analog Output DI = Digital Input DO = Digital Output P = Power FUNCTIONAL BLOCK DIAGRAM REF OUT SHA COMP20k 10k 2.5k 2.5k AD1674 AGND BIP OFF REF IN 20VIN 10VIN IDAC CONTROL CE CS R/C A 0 10k /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines SAR /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines CLOCK /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 10V REF /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines REGISTERS / 3-STATE OUTPUT BUFFERS DAC STS DB11 (MSB) DB0 (LSB) PIN CONFIGURATION TOP VIEW (Not to Scale) AD1674 VLOGIC CE VCC A 0 REF OUT AGND REF IN VEE BIP OFF 10VIN 20VIN CS R/C STS DB11(MSB) DB8 DB7 DB6 DB10 DB9 DB5 DB4 DB3 DB2 DB1 DB0(LSB) DGND

REV. C–8– DEFINITION OF SPECIFICATIONS INTEGRAL NONLINEARITY (INL) The ideal transfer function for an ADC is a straight line drawn between “zero” and “full scale.” The point used as “zero” occurs 1/2 LSB before the first code transition. “Full scale” is defined as a level 1 1/2 LSB beyond the last code transition. Integral nonlinearity is the worst-case deviation of a code from the straight line. The deviation of each code is measured from the middle of that code. DIFFERENTIAL NONLINEARITY (DNL) A specification which guarantees no missing codes requires that every code combination appear in a monotonic increasing sequence as the analog input level is increased. Thus every code must have a finite width. The AD1674 guarantees no missing codes to 12-bit resolution; all 4096 codes are present over the entire operating range. UNIPOLAR OFFSET The first transition should occur at a level 1/2 LSB above ana- log common. Unipolar offset is defined as the deviation of the actual transition from that point at 25 °C. This offset can be adjusted as shown in Figure 11. BIPOLAR OFFSET In the bipolar mode the major carry transition (0111 1111 1111 to 1000 0000 0000) should occur for an analog value 1/2 LSB below analog common. The bipolar offset error specifies the deviation of the actual transition from that point at 25 °C. This offset can be adjusted as shown in Figure 12. FULL-SCALE ERROR The last transition (from 1111 1111 1110 to 1111 1111 1111 ) should occur for an analog value 1 1/2 LSB below the nominal full scale (9.9963 volts for 10 volts full scale). The full-scale error is the deviation of the actual level of the last transition from the ideal level at 25°C. The full-scale error can be adjusted to zero as shown in Figures 11 and 12. TEMPERATURE DRIFT The temperature drifts for full-scale error, unipolar offset and bipolar offset specify the maximum change from the initial (25°C) value to the value at T MIN or TMAX. POWER SUPPLY REJECTION The effect of power supply error on the performance of the device will be a small change in full scale. The specifications show the maximum full-scale change from the initial value with the supplies at various limits. FREQUENCY-DOMAIN TESTING The AD1674 is tested dynamically using a sine wave input and a 2048 point Fast Fourier Transform (FFT) to analyze the resulting output. Coherent sampling is used, wherein the ADC sampling frequency and the analog input frequency are related to each other by a ratio of integers. This ensures that an integral multiple of input cycles is captured, allowing direct FFT pro- cessing without windowing or digital filtering which could mask some of the dynamic characteristics of the device. In addition, the frequencies are chosen to he “relatively prime” (no common factors) to maximize the number of different ADC codes that are present in a sample sequence. The result, called Prime Coherent Sampling, is a highly accurate and repeatable measure of the actual frequency-domain response of the converter. NYQUIST FREQUENCY An implication of the Nyquist sampling theorem, the “Nyquist Frequency” of a converter is that input frequency which is one- half the sampling frequency of the converter. SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO S/(N+D) is the ratio of the rms value of the measured input sig- nal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in decibels. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of a full-scale input signal and is ex- pressed as a percentage or in decibels. For input signals or harmonics that are above the Nyquist frequency, the aliased component is used. INTERMODULATION DISTORTION (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products, of order (m+n), at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3. . . . Intermodulation terms are those for which m or n is not equal to zero. For example, the second order terms are (fa + fb) and (fa – fb) and the third order terms are (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). The IMD products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the distortion terms. The two signals are of equal amplitude and the peak value of their sums is –0.5 dB from full scale. The IMD products are normalized to a 0 dB input signal. FULL-POWER BANDWIDTH The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3 dB for a full-scale input. FULL-LINEAR BANDWIDTH The full-linear bandwidth is the input frequency at which the slew rate limit of the sample-hold-amplifier (SHA) is reached. At this point, the amplitude of the reconstructed fundamental has degraded by less than –0.1 dB. Beyond this frequency, dis- tortion of the sampled input signal increases significantly. APERTURE DELAY Aperture delay is a measure of the SHA’s performance and is measured from the falling edge of Read/Convert (R/ C) to when the input signal is held for conversion. APERTURE JITTER Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D.

Figure 5. Harmonic Distortion vs. LOW going edge to allow for acquisition to 12-bit accuracy. command anytime during the SHA acquisition interval. 5 kΩ resistor from the input signal voltage held by the SHA. available and thus not requiring full bus interface capability. trates the internal logic circuitry.

0 X X X X None

Figure 7. S/(N+D) vs. Input Amplitude Figure 9. IMD Plot for f IN = 9.08 kHz (fa), 9.58 kHz (fb) Figure 8. Nonaveraged 2048 Point FFT Figure 6. S/(N+D) vs. Input Frequency

0 TO +20V

0 TO +10V

5 R/C

10 REF IN

8 REF OUT

12 BIP OFF

9 ANA COM

Figure 11. Unipolar Input Connections with Gain and error will be approximately 1%.

1. Either or both of the trimming potentiometers can be

tions may be necessary for convergence. 0000 0000). Then perform the gain error trim as outlined above. Figure 12. Bipolar Input Connections with Gain and Offset broad-band noise contributions from the voltage reference. attention to board layout. Trace impedance is a significant issue. using an anti-aliasing filter at the analog input of the AD1674. Analog and digital signals should not share a common path. should cross them (if necessary) only at right angles. nated by the return current for DB11–DB0. spikes which can induce noise in the analog system. provides adequate decoupling over a wide range of frequencies.

REV. C–12– C1425b–10–3/94PRINTED IN U.S.A. GROUNDING If a single AD1674 is used with separate analog and digital ground planes, connect the analog ground plane to AGND and the digital ground plane to DGND keeping lead lengths as short as possible. Then connect AGND and DGND together at the AD1674. If multiple AD1674s are used or the AD1674 shares analog supplies with other components, connect the analog and digital returns together once at the power supplies rather than at each chip. This prevents large ground loops which inductively couple noise and allow digital currents to flow through the ana- log system. GENERAL MICROPROCESSOR INTERFACE CONSIDERATIONS A typical A/D converter interface routine involves several opera- tions. First, a write to the ADC address initiates a conversion. The processor must then wait for the conversion cycle to com- plete, since most ADCs take longer than one instruction cycle to complete a conversion. Valid data can, of course, only be read after the conversion is complete. The AD1674 provides an out- put signal (STS) which indicates when a conversion is in progress. This signal can be polled by the processor by reading it through an external three-state buffer (or other input port). The STS signal can also be used to generate an interrupt upon completion of a conversion, if the system timing requirements are critical (bear in mind that the maximum conversion time of the AD1674 is only 10 microseconds) and the processor has other tasks to perform during the ADC conversion cycle. An- other possible time-out method is to assume that the ADC will take 10 microseconds to convert, and insert a sufficient number of “no-op” instructions to ensure that 10 microseconds of pro- cessor time is consumed. Once it is established that the conversion is finished, the data can be read. In the case of an ADC of 8-bit resolution (or less), a single data read operation is sufficient. In the case of convert- ers with more data bits than are available on the bus, a choice of data formats is required, and multiple read operations are needed. The AD1674 includes internal logic to permit direct in- terface to 8-bit or 16-bit data buses, selected by the 12/ 8 input. In 16-bit bus applications (12/ 8 HIGH) the data lines (DB11 through DB0) may be connected to either the 12 most signifi- cant or 12 least significant hits of the data bus. The remaining four bits should be masked in software. The interface to an 8-bit data bus (12/

8 LOW) contains the 8 MSBs (DB11 through

DB4). The odd address (A 0 HIGH) contains the 4 LSBs (DB3 through DB0) in the upper half of the byte, followed by four trailing zeroes, thus eliminating bit masking instructions. AD1674 Data Format for 8-Bit Bus

PACKAGE INFORMATION

Dimensions shown in inches and (mm). 28-Pin Ceramic DIP Package (D-28) 0.050 ±0.010 (1.27 ±0.254) SEATING PLANE 1.42 (36.07) 1.40 (35.56) 0.047 ±0.007 (1.19 ±0.178) (0.43 ±0.076) 0.145 ±0.02 (3.68 ±0.51) 0.125 (3.17) MIN 0.6 (15.24) 0.010 ±0.002 (0.254 ±0.05) 0.095 (2.41) 0.085 (2.16) 0.59 ±0.01 (14.98 ±0.254) PIN 1 0.505 (12.83) 28-Lead Plastic DIP Package (N-28) PIN 1 0.550 (13.97) 0.530 (13.462) 1 14 1528 SEATING PLANE 1.450 (38.83) 1.440 (35.576) 0.200 (5.080) MAX 0.020 (0.508) 0.015 (0.381) 0.160 (4.06) 0.140 (3.56) 0.175 (4.45) 0.120 (3.05) 0.105 (2.67) 0.095 (2.41) 0.065 (1.65) 0.045 (1.14) 0.606 (15.39) 0.594 (15.09) 0.012 (0.305) 0.008 (0.203) 15° 28-Lead Wide-Body SO Package (R-28) PIN 1 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 28 15 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 0.0291 (0.74) 0.0098 (0.25) x 45° 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) BSC 0.1043 (2.65) 0.6969 (17.70) 0.0118 (0.30) 0.0040 (0.10)