AD1671 AD | Alldatasheet
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2.5V REFREF OUT REF IN LATCHES CORRECTION LOGIC 8-BIT LADDER MATRIX AD1671 3-BIT FLASH REF COM AIN2 VCC ACOM VEE VLOGIC DCOM 3-BIT FLASHDAC FINE 4-BIT FLASH COARSE 4-BIT FLASH DAC MSB DAVBIT 1 –12 RANGE SELECT REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Complete 12-Bit 1.25 MSPS Monolithic A/D Converter AD1671 Tel: 617/329-4700 Fax: 617/326-8703
FEATURES
Conversion Time: 800 ns
1.25 MHz Throughput Rate
Complete: On-Chip Sample-and-Hold Amplifier and Voltage Reference Low Power Dissipation: 570 mW No Missing Codes Guaranteed Signal-to-Noise Plus Distortion Ratio f IN = 100 kHz: 70 dB Pin Configurable Input Voltage Ranges Twos Complement or Offset Binary Output Data 28-Pin DIP and 28-Pin Surface Mount Package Out of Range Indicator PRODUCT DESCRIPTION The AD1671 is a monolithic 12-bit, 1.25 MSPS analog-to- digital converter with an on-board, high performance sample- and-hold amplifier (SHA) and voltage reference. The AD1671 guarantees no missing codes over the full operating tempera- ture range. The combination of a merged high speed bipolar/ CMOS process and a novel architecture results in a combi- nation of speed and power consumption far superior to pre- viously available hybrid implementations. Additionally, the greater reliability of monolithic construction offers improved system reliability and lower costs than hybrid designs. The fast settling input SHA is equally suited for both multi- plexed systems that switch negative to positive full-scale voltage levels in successive channels and sampling inputs at frequencies up to and beyond the Nyquist rate. The AD1671 provides both reference output and reference input pins, al- lowing the on-board reference to serve as a system reference. An external reference can also be chosen to suit the dc accu- racy and temperature drift requirements of the application. The AD1671 uses a subranging flash conversion technique, with digital error correction for possible errors introduced in the first part of the conversion cycle. An on-chip timing gen- erator provides strobe pulses for each of the four internal flash cycles. A single ENCODE pulse is used to control the converter. The digital output data is presented in twos complement or offset binary output format. An out-of-range signal indicates an overflow condition. It can be used with the most significant bit to determine low or high overflow. The performance of the AD1671 is made possible by using high speed, low noise bipolar circuitry in the linear sections and low power CMOS for the logic sections. Analog Devices’ ABCMOS-1 process provides both high speed bipolar and 2-micron CMOS devices on a single chip. Laser trimmed thin-film resistors are used to provide accuracy and temperature stability. The AD1671 is available in two performance grades and three temperature ranges. The AD1671J and K grades are available over the 0°C to +70°C temperature range. The AD1671A grade is available over the –40°C to +85°C temperature range. The AD1671S grade is available over the –55 °C to +125°C tempera- ture range. PRODUCT HIGHLIGHTS The AD1671 offers a complete single chip sampling 12-bit,
1.25 MSPS analog-to-digital conversion function in a 28-pin
package. The AD1671 at 570 mW consumes a fraction of the power of currently available hybrids. An OUT OF RANGE output bit indicates when the input sig- nal is beyond the AD1671’s input range. Input signal ranges are 0 V to +5 V unipolar or ± 5 V bipolar, selected by pin strapping, with an input resistance of 10 k Ω . The input signal range can also be pin strapped for 0 V to +2.5 V unipolar or ± 2.5 V bipolar with an input resistance of 10 MΩ . Output data is available in unipolar, bipolar offset or bipolar twos complement binary format.
Parameter Min Typ Max Min Typ Max Units RESOLUTION 12 12 Bits CONVERSION TIME 800 800 ns ACCURACY Integral Nonlinearity (INL) ± 1.5 ± 2.5 ± 0.7 ± 2.5 LSB (S Grade) ± 3.0 Differential Nonlinearity (DNL) 11 12 Bits No Missing Codes 11 Bits Guaranteed 12 Bits Guaranteed Unipolar Offsets Bipolar Zero 1 (+25°C) ± 10 ± 10 LSB Gain Error1, 2 (+25°C) 0.1 0.35 0.1 0.35 % FSR TEMPERATURE COEFFICIENTS 3 Unipolar Offset ± 25 ± 25 ppm/ °C (S Grade) ± 25 Bipolar Zero ± 25 ± 25 ppm/ °C (S Grade) ± 30 Gain Error3 ± 30 ± 30 ppm/ °C (S Grade) ± 40 Gain Error4 ± 20 ± 20 ppm/ °C POWER SUPPLY REJECTION 5 VCC (+5 V ± 0.25 V) ± 4 ± 4 LSB (S Grade) ± 5 VLOGIC (+5 V ± 0.25 V) ± 4 ± 4 LSB (S Grade) ± 5 VEE (–5 V ± 0.25 V) ± 4 ± 4 LSB (S Grade) ± 5 ANALOG INPUT Input Ranges Bipolar –2.5 +2.5 –2.5 +2.5 Volts Unipolar 0 +2.5 0 +2.5 Volts 0 +5.0 0 +5.0 Volts Input Resistance (0 V to +2.5 V or ± 2.5 V Range) 10 10 M Ω (0 V to +5.0 V or ± 5 V Range) 8 10 12 8 10 12 k Ω Input Capacitance 10 10 pF Aperture Delay 15 15 ns Aperture Jitter 20 20 ps INTERNAL VOLTAGE REFERENCE Output Current Unipolar Mode +2.5 +2.5 mA Bipolar Mode +1.0 +1.0 mA LOGIC INPUTS High Level Input Voltage, V IH 2.0 2.0 Volts Low Level Input Voltage, V IL 0.8 0.8 Volts High Level Input Current, I IH (VIN = VLOGIC) –10 +10 –10 +10 µA Low Level Input Current , ILL (VIN = 0 V) –10 +10 –10 +10 µA Input Capacitance , CIN 55 p F LOGIC OUTPUTS High Level Output Voltage, V OH (IOH = 0.5 mA) 2.4 2.4 Volts Low Level Output Voltage, VOL (IOL = 1.6 mA) 0.4 0.4 Volts POWER SUPPLIES Operating Voltages VCC +4.75 +5.25 +4.75 +5.25 Volts VLOGIC +4.5 +5.5 +4.5 +5.5 Volts VEE –4.75 –5.25 –4.75 –5.25 Volts Operating Current ICC 55 68 55 68 mA ILOGIC 6 35 3 5 m A IEE –55 –68 –55 –68 mA POWER CONSUMPTION 570 750 570 750 mW TEMPERATURE RANGE (SPECIFIED) J/K 0 +70 0 +70 °C A –40 +85 –40 +85 °C S –55 +125 –55 +125 °C NOTES 1Adjustable to zero with external potentiometers. 2Includes internal voltage reference error. 3+25°C to TMIN and +25°C to TMAX 4Excludes internal reference drift. 5Change in gain error as a function of the dc supply voltage. 6Tested under static conditions. See Figure 15 for typical curve of I LOGIC vs. load capacitance at maximum t C. Specifications subject to change without notice . (TMIN to TMAX with VCC = +5 V 6 5%, VLOGIC = +5 V 6 10%, VEE = –5 V 6 5%, unless otherwise noted) AD1671–SPECIFICATIONS REV. B–2–
REV. B–4– PIN DESCRIPTION Symbol Pin No. Type Name and Function ACOM 27 P Analog Ground. AIN 22, 23 AI Analog Inputs, AIN1 and AIN2. The AD1671 can be pin strapped for four input ranges: Range Pin Strap Signal Input 0 to +2.5 V, ± 2.5 V Connect AIN1 to AIN2 AIN1 or AIN2 0 to +5 V, ± 5 V Connect AIN1 or AIN2 to ACOM AIN1 or AIN2 BIT 1 (MSB) 13 DO Most Significant Bit. BIT 2–BIT 11 12-3 DO Data Bits 2 through 11. BIT 12 (LSB) 2 DO Least Significant Bit. BPO/UPO 26 AI Bipolar or Unipolar Configuration Pin. See section on Input Range Connections for details. DAV 16 DO Data Available Output. The rising edge of DAV indicates an end of conversion and can be used to latch current data into an external register. The falling edge of DAV can be used to latch previous dam into an external register. DCOM 19 P Digital Ground. ENCODE 17 DI The analog input is sampled on the rising edge of ENCODE. MSB 14 DO Inverted Most Significant Bit. Provides twos complement output data format. OTR 15 DO Out of Range is Active HIGH when the analog input is out of range. See Output Data Format, Table III. REF COM 20 AI REF COM is the internal reference ground pin. REF COM should be connected as indicated in the Grounding and Decoupling Rules and Optional External Reference Connection Sections. REF IN 24 AI REF IN is the external 2.5 V reference input. REF OUT 21 AO REF OUT is the internal 2.5 V reference output. SHA OUT 25 AO No C onnect for bipolar input ranges. Connect SHA OUT to BPO/UPO for unipolar input ranges. V CC 28 P +5 V Analog Power. VEE 1 P –5 V Analog Power. VLOGIC 18 P +5 V Digital Power. TYPE: AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Outputs; P = Power. PIN CONFIGURATION ACOM BPO/UPO DCOM ENCODE DAV OTRMSB BIT 12 (LSB) BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (MSB) AIN1 REF COM REF OUT AIN2 SHA OUT 6 23 TOP VIEW (Not to Scale) AD1671 VEE VCC VLOGIC REF IN
REV. B –5– ABSOLUTE MAXIMUM RATINGS* Parameter With Respect to Min Max Units VCC ACOM –0 5 +6.5 Volts VEE ACOM –6.5 +0.5 Volts VLOGIC DCOM –0.5 +6.5 Volts ACOM DCOM –1.0 +1.0 Volts VCC VLOGIC –6.5 +6.5 Volts ENCODE DCOM –0.5 V LOGIC + 0.5 Volts REF IN ACOM –0.5 V CC + 0.5 Volts AIN ACOM –11.0 +11.0 Volts BPO/UPO ACOM –0.5 V CC + 0.5 Volts Junction Temperature +150 °C Storage Temperature –65 +150 °C Lead Temperature (10 sec) +300 °C *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1671 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Temperature Package Model1 Linearity Range Option 2, 3 AD1671JQ ± 2.5 LSB 0 °C to +70°C Q-28 AD1671KQ ± 2 LSB 0 °C to +70°C Q-28 AD1671JP ± 2.5 LSB 0 °C to +70°C P-28A AD1671KP ± 2 LSB 0 °C to +70°C P-28A AD1671AQ ± 2.5 LSB –40 °C to +85°C Q-28 AD1671AP ± 2.5 LSB –40 °C to +85°C P-28A AD1671SQ ± 3 LSB –55 °C to +125°C Q-28 NOTES 1For details on grade and package offerings screened in accordance with MIL-STD-883, refer to Analog Devices’ Military Products Databook or current AD1671/883 data sheet. 2P = Plastic Leaded Chip Carrier, Q = Cerdip. 3Analog Devices reserves the right to ship side brazed ceramic packages in lieu of cerdip.
REV. B–6– DEFINITIONS OF SPECIFICATIONS INTEGRAL NONLINEARITY (INL) Integral nonlinearity refers to the deviation of each individual code from a line drawn from “zero” through “full scale.” The point used as “zero” occurs 1/2 LSB (1.22 mV for a 10 V span) before the first code transition (all zeros to only the LSB on). “Full-scale” is defined as a level 1 1/2 LSB beyond the last code transition (to all ones). The deviation is measured from the low side transition of each particular code to the true straight line. DIFFERENTIAL LINEARITY ERROR (NO MISSING CODES) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from the ideal value. Thus every code has a finite width. Guaranteed no missing codes to 11- or 12-bit resolution indicates that all 2048 and 4096 codes, respec- tively, must be present over all operating ranges. No missing codes to 11 bits (in the case of a 12-bit resolution ADC) also means that no two consecutive codes are missing. UNIPOLAR OFFSET The first transition should occur at a level 1/2 LSB above analog common. Unipolar offset is defined as the deviation of the ac- tual from that point. This offset can be adjusted as discussed later. The unipolar offset temperature coefficient specifies the maximum change of the transition point over temperature, with or without external adjustments. BIPOLAR ZERO In the bipolar mode the major carry transition (0111 1111 1111 to 1000 0000 0000) should occur for an analog value 1/2 LSB be- low analog common. The bipolar offset error and temperature coefficient specify the initial deviation and maximum change in the error over temperature. GAIN ERROR The last transition (from 1111 1111 1110 to 1111 1111 1111) should occur for an analog value 1 1/2 LSB below the nominal full scale (4.9963 volts for 5.000 volts full scale). The gain error is the deviation of the actual level at the last transition from the ideal level. The gain error can be adjusted to zero as shown in Figures 4 through 7. TEMPERATURE COEFFICIENTS The temperature coefficients for unipolar offset, bipolar zero and gain error specify the maximum change from the initial (+25°C) value to the value at T MIN or TMAX. POWER SUPPLY REJECTION One of the effects of power supply error on the performance of the device will be a small change in gain. The specifications show the maximum full-scale change from the initial value with the supplies at the various limits. DYNAMIC SPECIFICATIONS SIGNAL-TO-NOISE PLUS DISTORTION (S/ N+D) RATIO S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components, including har- monics but excluding dc. The value for S/N+D is expressed in decibels. EFFECTIVE NUMBER OF BITS (ENOB) ENOB is calculated from the expression (S/N+D) = 6.02N + 1.76 dB, where N is equal to the effective number of bits. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured input signal and is ex- pressed as a percentage or in decibels. INTERMODULATION DISTORTION (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products of order (m + n), at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3. . . . Intermodulation terms are those for which m or n is not equal to zero. For example, the second order terms are (fa + fb) and (fa – fb), and the third or- der terms are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (2fb – fa). The IMD products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the distor- tion terms. The two signals are of equal amplitude and the peak value of their sum is –0.5 dB from full scale. The IMD products are normalized to a 0 dB input signal. PEAK SPURIOUS OR PEAK HARMONIC COMPONENT The peak spurious or peak harmonic component is the largest spectral component, excluding the input signal and dc. This value is expressed in decibels relative to the rms value of a full- scale input signal. APERTURE DELAY Aperture delay is the difference between thc switch delay and the analog delay of the SHA. This delay represents the point in time, relative to the rising edge of ENCODE input, that the analog input is sampled. APERTURE JITTER Aperture jitter is the variation in aperture delay for successive samples. FULL POWER BANDWIDTH The input frequency at which the amplitude of the recon- structed fundamental is reduced by 3 dB for a full-scale input.
0 V 0000 0000 0000 0
1Voltages listed are with offset and gain errors adjusted to zero. form math on signed integers and assume data is in that format. conversion steps, hence the total system throughput is increased. put dependent currents are modulated at the reference input. for various capacitor loads on the digital outputs. Figure 15. I LOGIC vs. Conversion Rate for Various
REV. B –13– COMPONENT LIST Parts List Type Reference Designator Description R1, R2 Resistor, 5%, 0.5 W, 100 Ω R3, R4, R5 Resistor, 1%, 49.9 Ω R6 100 Ω Trim Potentiometer R7 Resistor 1%, 4.99 k Ω Optional R8 X Ω Trim Potentiometer, Optional R9, R11 Resistor, 1%, 4.99 k Ω R10 Resistor, 1%, 10 k Ω R12 Resistor, 1%, 2.49 k Ω R13 Resistor, 1%, 787 Ω R14 Resistor, 1%, 249 Ω R15–R28 Resistor, 5%, 22 Ω C1, C3, C5 Cap, Tantalum, 22 µF C2, C4, C6, C8, C10 Cap, Ceramic, 0.01 µF C7, C9, C15, C16 Cap, Tantalum, 10 µF C11, C12, C13, C14, C17 Cap, Ceramic, 0.1 µF C18 Cap, Ceramic, 1.0 µF C19–C22 Cap, Ceramic, 0.1 µF C23 Cap, Mica, 100 pF C24 Cap, Ceramic, 0.001 µF U1 78L05 +5 V Regulator U2 79L05 –5 V Regulator U3 AD1671 U4–U5 74HC573 Drivers U6 AD568 W1–W3 BNC Jacks J1–J15 Jumpers and Headers Metal Binding Posts S1 Wide 28-Pin Socket S2 Narrow 20-Pin Socket S3 Narrow 24-Pin Socket SW1–SW3 SECMA SPDT Switch TP1, TP2, TP4–TP6 Test Point, Red TP3, TP7, TP10, TP13 Test Point, Black TP8, TP9, TP11, TP12, TP14 Test Point, White P1 40-Pin Connector Male + Hooks
Figure 18. AD1671/EB PCB Layout—Silkscreen Layer
REV. B–16– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead PLCC (P-28A) Package 28-Pin Cerdip (Q-28) Package C1616a–10–10/93PRINTED IN U.S.A.