AD15700BCA

AD15700 AD | Alldatasheet

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REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD15700

1 MSPS 16-/14-Bit

FEATURES

1 MSPS

S/(N + D): 90 dB Typ @ 250 kHz No Pipeline Delay 14-Bit D/A Converter Settling Time: 1 /H9262s S/N: 92 dB Typ 2 80 MHz Amplifiers

30 V/ /H9262s Slew Rate

Rail-to-Rail Input and Output Output Current 15 mA

2 Gain Setting Center Tapped Resistors

Resistor Ratio Tracking: 2 ppm/ /H11543C Unipolar Operation SPI ® /QSPI™/MICROWIRE™/DSP Compatible 132 mW Typical Power Dissipation

APPLICATIONS

Optical MEMS Mirror Control Industrial Process Control Data Acquisition Instrumentation Communication PRODUCT HIGHLIGHTS 1. Fast Throughput ADC. The AD15700 incorporates a high speed, 1 MSPS, 16-bit SAR ADC. 2. Superior ADC INL. The 16-bit ADC has a maximum integral nonlineariy of 2.5 LSB with no missing codes. 3. Two Precision Resistor Networks with 2 ppm/ ∞C Ratio Tracking for Gain Setting. 4. Low Power Consumption. Typically 132 mW at maximum performance levels. 5. Industrial Temperature Range: –40 ∞C to +85∞C. GENERAL DESCRIPTION The AD15700 is a precision component to interface analog input and output channels to a digital processor. It is ideal for area- limited applications that require maximum circuit density. The AD15700 contains the functionality of a 16-bit,

1 MSPS charge

redistribution SAR analog-to-digital converter that operates from a 5 V power supply. The high speed 16-bit sampling ADC incor- porates a resistor input scaler that allows various input ranges, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. The AD15700 also contains a 14-bit, serial input, voltage output DAC that operates from a 5 V supply and has a settling time of 1 ms. Two single- or split-supply voltage feedback amplifiers with rail-to-rail input and output characteristics featuring 80 MHz of small signal bandwidth and 10 mV/∞C offset drift provide ADC and DAC buffering capability. The center tapped 3 k W resistors are precision resistor networks with 2 ppm/∞C ratio tracking that provide low gain drift when used for scaling. The ADC, DAC, and amp functions are electrically isolated from each other to provide maximum design flexibility. Input and output signal conditioning circuits for the converters can be easily configured with short interconnects under the device at the board level. The AD15700 is available in a 10 mm CSPBGA package. FUNCTIONAL BLOCK DIAGRAM SERIAL PORT PARALLEL INTERFACE R SAR ADC CONTROL LOGIC AND CALIBRA TION CIRCUITRY CLOCK SWITCHED CAP DAC OVDD OGND SER/PAR BUSY D[15:0] CS_ADC RD OB/2C BYTESWAP WARP IMPULSECNVST AVDD AGND_ADC REF REFGND DVDD DGND ADC IND(4R) INC(4R) INB(2R) INA(R) INGND PD RESET SERIAL INPUT REGISTER 14-BIT DA T A LA TCH CONTROL LOGIC 14-BIT DAC VDD_DAC DGND_DAC CS_DAC DIN SCLK VREF VOUT_DAC AGND_DAC –VS2 +VS2 –VS1 +VS1 AD15700 RA1 RB1 RC1 RB2 RC2RA2 +IN2 –IN2 VOUT2 –IN1 +IN1 VOUT1 RP AD2 RP AD1 COMMON 1.5k/H90241.5k/H9024 1.5k/H9024 1.5k/H9024

REV. A–2– AD15700–SPECIFICATIONS Parameter Condition Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range VIND – VINGND ± 4 REF, 0 V to 4 REF, ± 2 REF (See Table I) Common-Mode Input Voltage VINGND –0.1 +0.5 V Analog Input CMRR f IN = 100 kHz 74 dB Input Impedance See Table I THROUGHPUT SPEED Complete Cycle In Warp Mode 1 ms Throughput Rate In Warp Mode 1 1000 kSPS Time between Conversions In Warp Mode 1 ms Complete Cycle In Normal Mode 1.25 ms Throughput Rate In Normal Mode 0 800 kSPS Complete Cycle In Impulse Mode 1.5 ms Throughput Rate In Impulse Mode 0 666 kSPS DC ACCURACY Integral Linearity Error –2.5 +2.5 LSB 1 No Missing Codes 16 Bits Transition Noise 0.7 LSB Bipolar Zero Error 2, TMIN to TMAX ± 5 V Range, Normal or –45 +45 LSB Impulse Modes Other Range or Mode ± 0.1% % of FSR Bipolar Full-Scale Error 2, TMIN to TMAX –0.38 +0.38 % of FSR Unipolar Zero Error 2, TMIN to TMAX –0.18 +0.18 % of FSR Unipolar Full-Scale Error2, TMIN to TMAX –0.76 +0.76 % of FSR Power Supply Sensitivity AVDD = 5 V ± 5% ± 9.5 LSB AC ACCURACY Signal-to-Noise f IN = 20 kHz 89 90 dB 3 fIN = 250 kHz 90 dB Spurious-Free Dynamic Range f IN = 250 kHz 100 dB Total Harmonic Distortion f IN = 20 kHz –100 –96 dB fIN = 250 kHz –100 dB Signal-to-(Noise + Distortion) f IN = 20 kHz 88.5 90 dB fIN = 250 kHz, –60 dB Input 30 dB –3 dB Input Bandwidth 9.6 MHz SAMPLING DYNAMICS Aperture Delay 2n s Aperture Jitter 5 ps rms Transient Response Full-Scale Step 250 ns REFERENCE External Reference Voltage Range 2.3 2.5 3.0 V External Reference Current Drain 1 MSPS Throughput 200 mA DIGITAL INPUTS Logic Levels VIL –0.3 +0.8 V VIH +2.0 DVDD + 0.3 V IIL –1 +1 mA IIH –1 +1 mA 16-BIT ADC ELECTRICAL CHARACTERISTICS (–40 /H11543C to +85/H11543C, AVDD = DVDD = 5 V, 0VDD = 2.7 V to 5.25 V, unless otherwise noted.)

REV. A AD15700 –3– Parameter Condition Min Typ Max Unit DIGITAL OUTPUTS Data Format Parallel or Serial 16-Bit Pipeline Delay Conversion Results Available Immediately after Completed Conversion VOL ISINK = 1.6 mA 0.4 V VOH ISOURCE = –570 mA OVDD – 0.6 V POWER SUPPLIES Specified Performance AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V OVDD 2.7 5.25 V Operating Current AVDD 15 mA DVDD5 7.2 mA OVDD5 37 mA Power Dissipation5, 6 666 kSPS Throughput7 84 95 mW

100 SPS Throughput7 15 mW

1 MSPS Throughput4 112 125 mW

Specified Performance T MIN to TMAX –40 +85 ∞C NOTES 1LSB means Least Significant Bit. With the ± 5 V input range, one LSB is 152.588 mV. 2These specifications do not include the error contribution from the external reference. 3All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 4In Warp Mode. 5Tested in Parallel Reading Mode. 6Tested with the 0 V to 5 V range and VIN – VINGND = 0 V. 7In Impulse Mode. 8With OVDD below DVDD + 0.3 V and all digital inputs forced to OVDD or OGND, respectively. Specifications subject to change without notice. Table I. Analog Input Configuration Input Voltage Range IND(4R) INC(4R) INB(2R) INA(R) Input Impedance 1 ± 4 REF V IN INGND INGND REF 1.63 k W ± 2 REF V IN VIN INGND REF 948 W ± REF V IN VIN VIN REF 711 W

0 V to 4 REF V IN VIN INGND INGND 948 W

0 V to 2 REF V IN VIN VIN INGND 711 W

0 V to REF V IN VIN VIN VIN Note 2

1Typical analog input impedance. 2For this range, the input is high impedance.

REV. A–4– AD15700 16-BIT ADC TIMING CHARACTERISTICS(–40/H11543C to +85/H11543C, AVDD = DVDD = 5 V, 0VDD = 2.7 V to 5.25 V, unless otherwise noted.) Parameter Symbol Min Typ Max Unit Refer to Figures 14 and 15 Convert Pulsewidth t 1 5n s Time between Conversions t2 1/1.25/1.5 Note 1 ms (Warp Mode/Normal Mode/Impulse Mode) CNVST LOW to BUSY HIGH Delay t 3 30 ns BUSY HIGH All Modes Except in Master Serial Read after t 4 0.75/1/1.25 ms Convert Mode (Warp Mode/Normal Mode/Impulse Mode) Aperture Delay t 5 2n s End of Conversion to BUSY LOW Delay t 6 10 ns Conversion Time (Warp Mode/Normal Mode/Impulse Mode) t 7 0.75/1/1.25 ms Acquisition Time t 8 1 ms RESET Pulsewidth t 9 10 ns Refer to Figures 16, 17, and 18 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay t 10 0.75/1/1.25 ms (Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY LOW Delay t 11 20 ns Bus Access Request to DATA Valid t 12 40 ns Bus Relinquish Time t 13 51 5 n s Refer to Figures 20 and 21 (Master Serial Interface Modes) 2 CS_ADC LOW to SYNC Valid Delay t 14 10 ns CS_ADC LOW to Internal SCLK Valid Delay t 15 10 ns CS_ADC LOW to SDOUT Delay t 16 10 ns CNVST LOW to SYNC Delay (Read During Convert) t 17 25/275/525 ns (Warp Mode/Normal Mode/Impulse Mode) SYNC Asserted to SCLK First Edge Delay 3 t18 4n s Internal SCLK Period 3 t19 25 40 ns Internal SCLK HIGH3 t20 15 ns Internal SCLK LOW3 t21 9n s SDOUT Valid Setup Time 3 t22 4.5 ns SDOUT Valid Hold Time 3 t23 2n s SCLK Last Edge to SYNC Delay 3 t24 3n s CS_ADC HIGH to SYNC HI-Z t 25 10 ns CS_ADC HIGH to Internal SCLK HI-Z t 26 10 ns CS_ADC HIGH to SDOUT HI-Z t 27 10 ns BUSY HIGH in Master Serial Read after Convert 3 t28 See Table II ms CNVST LOW to SYNC Asserted Delay t 29 0.75/1/1.25 ms Master Serial Read after Convert SYNC Deasserted to BUSY LOW Delay t 30 25 ns Refer to Figures 22 and 24 (Slave Serial Interface Modes) External SCLK Setup Time t 31 5n s External SCLK Active Edge to SDOUT Delay t 32 31 6 n s SDIN Setup Time t 33 5n s SDIN Hold Time t 34 5n s External SCLK Period t 35 25 ns External SCLK HIGH t 36 10 ns External SCLK LOW t 37 10 ns NOTES 1In Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 2In Serial Interface Modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise, the load is 60 pF maximum. 3In serial master Read during Convert Mode. See Table II. Specifications subject to change without notice.

REV. A–6– AD15700 14-BIT DAC ELECTRICAL CHARACTERISTICS(TA = –40/H11543C to +85/H11543C, VDD_DAC = 5 V, VREF = 2.5 V, unless otherwise noted.) Parameter Condition Min Typ Max Unit STATIC PERFORMANCE Resolution 1 LSB = V REF/214 = 153 mV when VREF = 2.5 V 14 Bits Relative Accuracy, INL ± 0.15 ± 1.0 LSB Differential Nonlinearity Guaranteed Monotonic ± 0.15 ± 0.8 LSB Gain Error –1.75 –0.3 0 LSB Gain Error Temperature Coefficient ± 0.1 ppm/ ∞C Zero Code Error 0 0.1 0.5 LSB Zero Code Temperature Coefficient ± 0.05 ppm/ ∞C OUTPUT CHARACTERISTICS Output Voltage Range 0 V REF –1 LSB V Output Voltage Settling Time To 1/2 LSB of FS, CL = 10 pF 1 ms Digital-to-Analog Glitch Impulse 1 LSB Change around the Major Carry 10 nV–s Digital Feedthrough All 1s Loaded to DAC, VREF = 2.5 V 0.05 nV–s DAC Output Impedance Tolerance Typically 20% 6.25 k W Power Supply Rejection Ratio DVDD ± 10% ± 1.0 LSB DAC REFERENCE INPUT Reference Input Range 2 V DD V Reference Input Resistance * 9k W LOGIC INPUTS Input Current ± 1.0 mA VINL, Input Low Voltage 0.8 V VINH, Input High Voltage 2.4 V Input Capacitance 10 pF Hysteresis Voltage 0.4 V REFERENCE Reference –3 dB Bandwidth All 1s Loaded 1.3 MHz Reference Feedthrough All 0s Loaded, VREF = 1 V p-p at 100 kHz 1 mV p-p Signal-to-Noise Ratio 92 dB Reference Input Capacitance Code 0000 H 75 pF Code 3FFFH 120 pF POWER REQUIREMENTS VDD 4.5 5.50 V IDD 0.3 1.1 mA Power Dissipation 1.5 6.05 mW *Reference input resistance is code-dependent, minimum at 2555 H. Specifications subject to change without notice.

TA = TMIN to TMAX, unless otherwise noted). 1Guaranteed by design. Not production tested. of 3 V and timed from a voltage level of 1.6 V). Specifications subject to change without notice. Figure 3. Timing Diagram

REV. A–8– AD15700 AMPLIFIER ELECTRICAL CHARACTERISTICS [5 V Supply (TA = 25/H11543C, VS = 5 V, RL = 1 k/H9024 to 2.5 V, RF = 2.5 k/H9024, unless otherwise noted.)] Parameter Condition Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth G = +1, V O < 0.4 V p-p 54 80 MHz Slew Rate G = –1, V O = 2 V Step 27 32 V/ ms Settling Time to 0.1% G = –1, V O = 2 V Step, CL = 10 pF 125 ns DISTORTION/NOISE PERFORMANCE Total Harmonic Distortion f C = 1 MHz, VO = 2 V p-p, G = +2 –62 dBc fC = 100 kHz, VO = 2 V p-p, G = +2 –86 dBc Input Voltage Noise f = 1 kHz 15 nV/÷Hz Input Current Noise f = 100 kHz 2.4 pA /÷Hz f = 1 kHz 5 pA /÷Hz Differential Gain R L = 1 kW 0.17 % Differential Phase R L = 1 kW 0.11 Degrees DC PERFORMANCE Input Offset Voltage V CM = VCC/2; VOUT = 2.5 V ± 1 ± 6m V TMIN to TMAX ± 6 ± 10 mV Offset Drift V CM = VCC/2; VOUT = 2.5 V 5 mV/∞C Input Bias Current V CM = VCC/2; VOUT = 2.5 V 0.45 1.2 mA TMIN to TMAX 2.0 mA Input Offset Current 50 350 nA Open-Loop Gain V CM = VCC/2; VOUT = 1.5 V to 3.5 V 76 82 dB TMIN to TMAX 74 dB INPUT CHARACTERISTICS Common-Mode Input Resistance 40 M W Differential Input Resistance 280 k W Input Capacitance 1.6 pF Input Voltage Range –0.5 to +5.5 V Input Common-Mode Voltage Range –0.2 to +5.2 V Common-Mode Rejection Ratio V CM = 0 V to 5 V 56 70 dB VCM = 0 V to 3.8 V 66 80 dB Differential/Input Voltage 3.4 V OUTPUT CHARACTERISTICS Output Voltage Swing Low R L = 10 kW 0.05 0.02 V Output Voltage Swing High 4.95 4.98 V Output Voltage Swing Low R L = 1 kW 0.2 0.1 V Output Voltage Swing High 4.8 4.9 V Output Current 15 mA Short Circuit Current Sourcing 28 mA Sinking –46 mA Capacitive Load Drive G = +2 15 pF POWER SUPPLY Operating Range 2.7 12 V Quiescent Current per Amplifier 800 1400 mA Power Supply Rejection Ratio V S– = 0 V to –1 V or 75 86 dB VS+ = 5 V to 6 V OPERATING TEMPERATURE RANGE –40 +85 ∞C Specifications subject to change without notice.

REV. A AD15700 –9– AMPLIFIER ELECTRICAL CHARACTERISTICS [/H115505 V Supply (TA = 25/H11543C, VS = /H115505 V, RL = 1 k/H9024 to 0 V, RF = 2.5 k/H9024, unless otherwise noted.)] Parameter Condition Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth G = +1, V O < 0.4 V p-p 54 80 MHz Slew Rate G = –1, V O = 2 V Step 30 35 V/ ms Settling Time to 0.1% G = –1, V O = 2 V Step, CL = 10 pF 125 ns DISTORTION/NOISE PERFORMANCE Total Harmonic Distortion f C = 1 MHz, VO = 2 V p-p, G = +2 –62 dBc fC = 100 kHz, VO = 2 V p-p, G = +2 –86 dBc Input Voltage Noise f = 1 kHz 15 nV /÷Hz Input Current Noise f = 100 kHz 2.4 pA /÷Hz f = 1 kHz 5 pA /÷Hz Differential Gain R L = 1 kW 0.15 % Differential Phase R L = 1 kW 0.15 Degrees DC PERFORMANCE Input Offset Voltage V CM = 0 V; VOUT = 0 V ± 1 ± 6 m V TMIN to TMAX ± 6 ± 10 mV Offset Drift V CM = 0 V; VOUT = 0 V 5 mV/∞C Input Bias Current V CM = 0 V; VOUT = 0 V 0.45 1.2 mA TMIN to TMAX 2.0 mA Input Offset Current 50 350 nA Open-Loop Gain V CM = 0 V; VOUT = ± 2 V 76 80 dB TMIN to TMAX 74 dB INPUT CHARACTERISTICS Common-Mode Input Resistance 40 M W Differential Input Resistance 280 k W Input Capacitance 1.6 pF Input Voltage Range –5.5 to +5.5 V Input Common-Mode Voltage Range –5.2 to +5.2 V Common-Mode Rejection Ratio V CM = –5 V to +5 V 60 80 dB VCM = –5 V to +3.5 V 66 90 dB Differential/Input Voltage 3.4 V OUTPUT CHARACTERISTICS Output Voltage Swing Low R L = 10 kW –4.94 –4.98 V Output Voltage Swing High +4.94 +4.98 V Output Voltage Swing Low R L = 1 kW –4.7 –4.85 V Output Voltage Swing High +4.7 +4.75 V Output Current 15 mA Short Circuit Current Sourcing +35 mA Sinking –50 mA Capacitive Load Drive G = +2 15 pF POWER SUPPLY Operating Range ± 1.35 ± 6 V Quiescent Current per Amplifier 900 1600 mA Power Supply Rejection Ratio V S– = –5 V to –6 V or 76 86 dB VS+ = +5 V to +6 V OPERATING TEMPERATURE RANGE –40 +85 ∞C Specifications subject to change without notice.

REV. A–10– AD15700 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD15700 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS * Analog Inputs ADC Ground Voltage Differences ADC Supply Voltages DAC Digital Input Voltage to DAC Input Current to Any DAC Pin Except Supplies . .± 10 mA RESISTOR DIVIDER ELECTRICAL CHARACTERISTICS(@ TA = 25/H11543C, unless otherwise noted.) Parameter Condition Min Typ Max Unit Resistance 2.97 3.00 3.03 k W Temperature Coefficient of Resistance 50 ppm/ ∞C Resistance Ratio of Two Halves 0.99 1.0 1.01 Resistance Ratio Tracking 2 ppm/∞C Power Dissipation T A = 70∞C 250* mW *At higher temperatures, linearly derates to 0 mW at 175 ∞C. Specifications subject to change without notice. S ± 0.5 V Amplifier Output Short Circuit Thermal Resistance /H9258JA *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Package Option AD15700BCA –40 ∞C to +85∞C 144-Lead CSPBGA AD15700/PCB 25 ∞C Evaluation Board ADDS-2191-EZLITE™ 25∞C Evaluation Kit* ADDS-21535-EZLITE ADDS-21160M-EZLITE ADDS-21161N-EZLITE *One of the DSP Evaluation Kits is required for operation of the AD15700/PCB Evaluation Board.

REV. A AD15700 –11– ADC PIN FUNCTION DESCRIPTIONS (See Pinout, page 42) Pin No. Mnemonic Type Description H9, J8, AGND_ADC P Analog Power Ground Pin J9, M12 M6 AVDD P Input Analog Power Pin. Nominally 5 V. L7 BYTESWAP DI Parallel Mode Selection (8-/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. L8 OB/ 2C DI Straight Binary/Binary Twos Complement. When OB/ 2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register. M7 WARP DI Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the minimum conversion rate. L9 IMPULSE DI Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. M8 SER/ PAR DI Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the Serial Interface Mode is selected and some bits of the DATA bus are used as a serial port. M9, L10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/ PAR is HIGH, these outputs are in high impedance. M10, L11 D[2:3] or DI/O When SER/ PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the DIVSCLK[0:1] serial master read DIVSCLK[0:1] after Convert Mode. These inputs, part of the Serial Port, are used to slow down, if desired, the internal serial clock that clocks the data output. In the other serial modes, these inputs are not used. M11 D[4] or EXT/ INT DI/O When SER/ PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital select input for choosing the internal or an external data clock, called, respectively, Master and Slave Mode. With EXT/ INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input and the external clock is gated by CS_ADC. L12 D[5] or INVSYNC DI/O When SER/ PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. K11 D[6] or INVSCLK DI/O When SER/ PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal. It is active in both Master and Slave Mode. K12 D[7] or RDC/SDIN DI/O When SER/ PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a read mode selection input, depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/ INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the previous data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. J10 OGND P Input/Output Interface Digital Power Ground J11 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (5 V or 3.3 V). J12 DVDD P Digital Power. Nominally at 5 V.

REV. A–12– AD15700 ADC PIN FUNCTION DESCRIPTIONS (continued) Pin No. Mnemonic Type Description H10 DGND_ADC P Digital Power Ground H12 D[8] or SDOUT DO When SER/ PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The ADC provides the conversion result, MSB first, from its internal shift register. The DATA format is determined by the logic level of OB/ 2C. In Serial Mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In Serial Mode, when EXT/INT is HIGH: If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge. H11 D[9] or SCLK DI/O When SER/ PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used as a serial data clock input or output, dependent upon the logic state of the EXT/ INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. G12 D[10] or SYNC DO When SER/ PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital output frame synchronization for use with the internal data clock (EXT/ INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while SDOUT output is valid. When a read sequence is initiated and INVSYNC is High, SYNC is driven LOW and remains LOW while SDOUT output is valid. G11 D[11] or RDERROR DO When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus. When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is used as an incomplete read error flag. In Slave Mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed high. F12, F11, D[12:15] DO B it 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/ PAR is HIGH, E12, E11 these outputs are in high impedance. G10 BUSY DO Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal. G9 DGND_ADC P Must be Tied to Digital Ground E10 RD DI Read Data. When CS_ADC and RD are both LOW, the interface parallel or serial output bus is enabled. K10 CS_ADC DI Chip Select. When CS_ADC and RD are both LOW, the interface parallel or serial output bus is enabled. CS_ADC is also used to gate the external serial clock. D12 RESET DI Reset Input. When set to a logic HIGH, reset the ADC. Current conversion, if any, is aborted. If not used, this pin could be tied to DGND. K9 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. E7 CNVST DI Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. In impulse mode (IMPULSE HIGH and WARP LOW), if CNVST is held low when the acquisition phase (t 8) is complete, the internal sample/hold is put into the hold state and a conversion is immediately started. H8 AGND_ADC P Must be Tied to Analog Ground G5 REF AI Reference Input Voltage H5 REFGND AI Reference Input Analog Ground J7 INGND P Analog Input Ground J5, K5, INA, INB, AI Analog Inputs. Refer to Table I for input range configuration. L5, M5 INC, IND

REV. A AD15700 –13– DAC PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Type Description A6 VOUT_DAC AO Analog Output Voltage from the DAC A3, C3, C4 AGND_DAC P Ground Reference Point for Analog Circuitry A2 VREF AI This is the voltage reference input for the DAC. Connect to external reference ranges from 2 V to VDD. B1 CS_DAC DI This is an active low logic input signal. The chip select signal is used to frame the serial data input. E1 SCLK DI Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. E2 DIN DI Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on the rising edge of SCLK. E3 DGND_DAC P Digital Ground. Ground reference for digital circuitry. C6 VDD_DAC P Analog Supply Voltage, 5 V ± 10% AMPLIFIER PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Type Description C9 (J1) +IN1(2) AI Positive Input Voltage A9 (G1) –IN1(2) AI Negative Input Voltage B12 (K4) VOUT1(2) AO Amplifier Output Voltage A11 (F3) +VS1(2) P Analog Positive Supply Voltage B10, B11 –VS1(2) P Analog Negative Supply Voltage (G3, H3) RESISTOR PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Type Description B9 (L4) RA1(2) AI/O Resistor End Terminal A8 (M4) RB1(2) AI/O Resistor Center Tap D9 (L1) RC1(2) AI/O Resistor End Terminal A7 (M3) RPAD1(2) P Resistor Die Pad. Tie to Analog Ground. COMMON PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Type Description A1, A4, A5, A10, A12, B2–B8, C1, COMMON P Common Floating Net Connecting 69 Pins. Not electrically C2, C5, C7, C8, C10–C12, D1–D8, connected within the module. Tie at least one of these pins D10, D11, E4–E6, E8, E9, F1, F2, to Analog Ground. F4–F10, G2, G4, G6–G8, H1, H2, H4, H6, H7, J2–J4, J6, K1–K3, K6–K8, L2, L3, L6, M1, M2 NOTES AI = Analog Input AI/O = Bidirectional Analog AO = Analog Output DI = Digital Input DI/O = Bidirectional Digital DO = Digital Output P = Power

REV. A–14– AD15700 ADC DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Full-Scale Error ment coding) should occur for an analog voltage 1 1/2 LSB below the nominal full scale (2.499886 V for the ± 2.5 V range). The full-scale error is the deviation of the actual level of the last transition from the ideal level. Bipolar Zero Error The difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. Unipolar Zero Error In unipolar mode, the first transition should occur at a level 1/2 LSB above analog ground. The unipolar zero error is the deviation of the actual transition from that point. Spurious Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) A measurement of the resolution with a sine wave input. It is related to S/(N + D) by the following formula: and is expressed in bits. Total Harmonic Distortion (THD) The rms sum of the first five harmonic components to the rms value of a full-scale input signal; expressed in decibels. Signal-to-Noise Ratio (SNR) The ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-(Noise + Distortion) Ratio (S/[N + D]) The ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N + D) is expressed in decibels. Aperture Delay A measure of the acquisition performance, measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Transient Response The time required for the ADC to achieve its rated accuracy after a full-scale step function is applied to its input. DAC DEFINITION OF SPECIFICATIONS Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. A typical INL versus code plot can be seen in TPC 16. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB maximum ensures monotonicity. TPC 19 illustrates a typical DNL versus code plot. Gain Error Gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. It is the deviation in slope of the DAC transfer characteristic from ideal. Gain Error Temperature Coefficient This is a measure of the change in gain error with changes in temperature. It is expressed in ppm/ ∞C. Zero Code Error Zero code error is a measure of the output error when zero code is loaded to the DAC register. Zero Code Temperature Coefficient This is a measure of the change in zero code error with a change in temperature. It is expressed in mV/ ∞C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV–s and is measured when the digital input code is changed by 1 LSB at the major carry transition. A plot of the glitch impulse is shown in Figure 28. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. CS_DAC is held high, while the CLK and DIN signals are toggled. It is specified in nV–s and is measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa. A typical plot of digital feedthrough is shown in Figure 27. Power Supply Rejection Ratio This specification indicates how the output of the DAC is affected by changes in the power supply voltage. Power supply rejection ratio is quoted in terms of percent change in output per percent change in V DD for full-scale output of the DAC. V DD is varied by ± 10%. Reference Feedthrough This is a measure of the feedthrough from the V REF input to the DAC output when the DAC is loaded with all 0s. A 100 kHz, 1V p-p is applied to V REF. Reference feedthrough is expressed in mV p-p.

REV. A AD15700 –15– 16-BIT D/A CONVERTER CODE 1.5 0 16384 32768 49152 65536 INL – LSB 1.0 0.0 –0.5 –1.5 –2.5 0.5 –1.0 –2.0 2.0 2.5 TPC 1. Integral Nonlinearity vs. Code CODE 1.25 0 16384 32768 49152 65536 DNL – LSB 0.75 0.25 0.00 –0.50 –1.00 0.50 –0.25 –0.75 1.50 1.75 1.00 TPC 2. Differential Nonlinearity vs. Code POSITIVE INL – LSB 0.0 0.3 NUMBER OF UNITS TPC 3. Typical Positive INL Distribution (314 Units) Typical Performance Characteristics– NEGA TIVE INL – LSB –3.0 –2.7 NUMBER OF UNITS TPC 4. Typical Negative INL Distribution (314 Units) CODE IN HEXADECIMAL 7000 7FFD 7FFE COUNTS 6000 5000 2000 4000 3000 8000 7FFF 8000 8001 8002 8003 8004 8005 8006 8007 1000 1297 1700 7029 7039 986 0025 TPC 5. Histogram of 16,384 Conversions of a DC Input at the Code Transition CODE IN HEXADECIMAL 9000 7FFC 7FFD COUNTS 8000 7000 4000 6000 5000 10000 7FFE 8001 8002 8003 8004 8005 80068000 3000 0 2000 01 2000 1000 7FFF 8007 3296 9503 3344 106132 TPC 6. Histogram of 16,384 Conversions of a DC Input at the Code Center

REV. A–16– AD15700 FREQUENCY – kHz AMPLITUDE – dB of Full Scale –20 –40 –100 –60 –80 –120 –180 –140 –160 100 200 300 400 500 FS = 1 MSPS fIN = 45.5322kHz SNR = 89.45dB THD = –100.05dB SFDR = 100.49dB SINAD = 89.1dB TPC 7. FFT Plot FREQUENCY – kHz SNR AND S/[N + D] – dB 10 100 1000 100 SNR SINAD ENOB 15.5 ENOB – Bits 15.0 14.5 14.0 13.0 13.5 16.0 TPC 8. SNR, S/(N + D), and ENOB vs. Frequency FREQUENCY – kHz SNR AND S/[N + D] – dB 10 100 1000 100 SNR SINAD ENOB 15.5 ENOB – Bits 15.0 14.5 14.0 13.0 13.5 16.0 TPC 9. SNR vs. Input Frequency TEMPERA TURE – /H11543C –55 SNR – dB –102 THD – dB –104 –98 –100 –106 52 5 4 5 6 58 5 105 125–15–35 TPC 10. SNR, THD vs. Temperature FREQUENCY – kHz –65 THD, HARMONICS – dB –70 –75 –80 –90 –85 10 100 1000 –60 105 SFDR – dB 115 –95 –100 –110 –105 –115 110 100 SFDR THD THIRD HARMONIC SECOND HARMONIC TPC 11. THD, Harmonics, and SFDR vs. Frequency INPUT LEVEL – dB –70 –60 THD, HARMONICS – dB –80 –90 –150 –100 –110 –60 –130 –140 –120 THDSECOND HARMONIC THIRD HARMONIC TPC 12. THD, Harmonics vs. Input Level

REV. A AD15700 –17– CL – pF t12 DELA Y – ns 05 0 100 150 200 TPC 13. Typical Delay vs. Load Capacitance C L SAMPLING RA TE – SPS 10000 OPERA TING CURRENTS – mA 1000 0.001 100 100000 01 0 100 1000 10000 0.1 0.01 100000 1000000 AVDD, WARP/NORMAL DVDD, WARP/NORMAL AVDD, IMPULSE DVDD, IMPULSE OVDD, ALL MODES TPC 14. Operating Currents vs. Sample Rate TEMPERA TURE – /H11543C 1000 –55 POWER-DOWN OPERA TING CURRENTS – nA 900 700 400 600 500 300 200 100 –35 –15 5 25 45 800 65 85 105 DVDD OVDD AVDD TPC 15. Power-Down Operating Currents vs. Temperature

REV. A–18– AD15700 14-BIT D/A CONVERTER CODE – Decimal 0.25 0 2048 INL – LSB –0.50 –0.25 0.50 4096 6144 8192 10240 12288 14336 16384 TA = 25/H11543C VDD = 5V VREF = 2.5V TPC 16. Integral Nonlinearity vs. Code TEMPERA TURE – /H11543C 0.50INL – LSB 0.25 –0.50 –0.25 –60 20 60 100 140–20 VDD = 5V VREF = 2.5V TPC 17. Integral Nonlinearity vs. Temperature SUPPL Y VOL T AGE – V 0.75 LINEARITY ERROR – LSB 0.50 0.25 –1.00 1.00 34 567 –0.50 –0.75 –0.25 DNL INL VDD = 2.5V TA = 25/H11543C TPC 18. Linearity Error vs. Supply Voltage CODE – Decimal 0.25 0 2048 DNL – LSB –0.50 –0.25 0.50 4096 6144 8192 10240 12288 14336 16384 TA = 25/H11543C VDD = 5V VREF = 2.5V TPC 19. Differential Nonlinearity vs. Code TEMPERA TURE – /H11543C 0.50DNL – LSB 0.25 –0.50 –0.25 –60 20 60 100 140–20 VDD = 5V VREF = 2.5V TPC 20. Differential Nonlinearity vs. Temperature REFERENCE VOL T AGE – V 0.50 LINEARITY ERROR – LSB 0.25 –0.50 –0.25 02 3 4 5 16 VDD = 5V TA = 25/H11543C DNL INL TPC 21. Linearity Error vs. Reference Voltage

REV. A AD15700 –19– TEMPERA TURE – /H11543C 0.75 –50 –25 GAIN ERROR – LSB 0.50 0.25 –0.50 –0.25 1.00 02 5 5 0 7 5 100 125 150 –0.75 –1.00 VDD = 5V VREF = 2.5V TPC 22. Gain Error vs. Temperature TEMPERA TURE – /H11543C –40 –20 SUPPL Y CURRENT – mA 200 250 02 04 06 08 0 100 120 150 VDD = 5V VLOGIC = 5V VREF = 2.5V TPC 23. Supply Current vs. Temperature DIGIT AL INPUT VOL T AGE – V SUPPL Y CURRENT – mA 350 400 2345 150 VDD = 5V VREF = 2.5V TA = 25/H11543C 250 300 200 TPC 24. Supply Current vs. Digital Input Voltage TEMPERA TURE – /H11543C –50 –25 ZERO-CODE OFFSET ERROR – LSB 0.75 02 5 5 0 7 5 VDD = 5V VREF = 2.5V 0.50 0.25 100 125 150 TPC 25. Zero-Code Error vs. Temperature VOLTAG E – V SUPPL Y CURRENT – mA 350 400 2345 150 250 300 200 450 REFERENCE VOLTAG E VDD = 5V SUPPL Y VOLTAG E V REF = 2.5V TA = 25/H11543C TPC 26. Supply Current vs. Reference Voltage or Supply Voltage CODE – Decimal 250 0 2048 REFERENCE CURRENT – mA 200 100 150 300 4096 6144 8192 10240 12288 14336 16384 TA = 25/H11543C VDD = 5V VREF = 2.5V TPC 27. Reference Current vs. Code

REV. A–20– AD15700 VDS – mV –5 –4 NUMBER OF P ARTS IN BIN –3 012345–1 –2 6 N = 250 TPC 28. Typical V OS Distribution @ VS = 5 V TEMPERA TURE – /H11543C 2.3 –40 0 OFFSET VOL T AGE – mV 2.1 1.9 1.5 1.7 2.5 10 30 40 50 60 70 80 9020–30 –10–20 VS = 5V VS = 65V TPC 29. Input Offset Voltage vs. Temperature TEMPERA TURE – /H11543C 0.95 –40 0 INPUT BIAS – mA 0.90 0.85 0.75 0.80 1.00 10 30 40 50 60 70 80 9020–30 –10–20 VS = 5V 0.65 0.60 0.55 0.50 0.70 TPC 30. Input Bias Current vs. Temperature COMMON-MODE VOL T AGE – V 600 INPUT BIAS CURRENT – nA 400 –200 200 800 2 56 7 894 –800 –400 –600 31 0 VS = 10V VS = 5V VS = 2.7V TPC 31. Input Bias Current vs. Common-Mode Voltage COMMON-MODE VOL T AGE – V –0.1 0 0.5 OFFSET VOL T AGE – mV –0.2 –0.3 –0.6 –0.4 –0.5 VS = 5V TPC 32. V OS vs. Common-Mode Voltage TEMPERA TURE – /H11543C 950 –40 0 SUPPL Y CURRENT/AMPLIFIER – mA 900 850 750 800 1000 10 30 40 50 60 70 80 9020–30 –10–20 650 600 700 /H11550IS = /H115505V /H11545IS = /H115455V /H11545IS = /H115452.7V TPC 33. Supply Current vs. Temperature

REV. A AD15700 –21– AMPLIFIER RLOAD – /H9024 DIFFERENCE FROM VCC – V –0.5 –2.5 –1.0 –1.5 100 1k 10k –2.0 VCC = 2.7V VCC = 5V VCC = 10V VCC VIN VCC VEE RLOAD VOUT TPC 34. +Output Saturation Voltage vs. R LOAD @ 85∞C RLOAD – /H9024 DIFFERENCE FROM VCC – V –0.5 –2.5 –1.0 –1.5 100 1k 10k –2.0 VCC VIN VCC VEE RLOAD VCC = 2.7V VCC = 5V VCC = 10V VOUT TPC 35. +Output Saturation Voltage vs. R LOAD @ 25∞C RLOAD – /H9024 DIFFERENCE FROM VCC – V –0.5 –2.5 –1.0 –1.5 100 1k 10k –2.0 VCC VIN VCC VEE RLOAD VCC = 2.7V VCC = 5V VCC = 10V VOUT TPC. 36 +Output Saturation Voltage vs. R LOAD @ –40∞C RLOAD – /H9024 1.2 DIFFERENCE FROM VEE – V 1.0 0.8 0.6 100 1k 10k 0.4 VCC VIN VCC VEE RLOAD VCC = 2.7V VCC = 5V VCC = 10V VOUT 0.2 TPC 37. –Output Saturation Voltage vs. R LOAD @ 85∞C RLOAD – /H9024 1.2 DIFFERENCE FROM VEE – V 1.0 0.8 0.6 100 1k 10k 0.4 VCC VIN VCC VEE RLOAD VCC = 2.7V VCC = 5V VCC = 10V VOUT 0.2 TPC 38. –Output Saturation Voltage vs. R LOAD @ 25∞C RLOAD – /H9024 1.2 DIFFERENCE FROM VEE – V 1.0 0.8 0.6 100 1k 10k 0.4 VCC VIN VCC VEE RLOAD VCC = 2.7V VCC = 5V VCC = 10V VOUT 0.2 TPC. 39 –Output Saturation Voltage vs. R LOAD @ –40∞C

REV. A–22– AD15700 RLOAD – /H9024 110GAIN – dB 105 100 2k 4k 6k 8k 10k0 VS = 5V –AOL +AOL TPC 40. Open-Loop Gain (A OL) vs. RLOAD TEMPERA TURE – /H11543C –40 0 GAIN – dB 10 30 40 50 60 70 80 9020–30 –10–20 VS = 5V RL = 1k/H9024 –AOL +AOL TPC 41. Open-Loop Gain (A OL) vs. Temperature VOUT – V 100 0 0.5 AOL – dB 110 VS = 5V RLOAD = 10k/H9024 RLOAD = 1k/H9024 TPC 42. Open-Loop Gain (A OL) vs. VOUT INPUT VOL T AGE – V –1.5 INPUT BIAS CURRENT – mA –10 0.5 2.5 4.5 6.5 100 500mV 500mV VS = 5V TPC 43. Differential Input Voltage 1 V Characteristics 0.00 1ST 2ND DIFF PHASE – Degrees –0.05 –0.10 0.10 –0.15 0.05 3RD 6TH 7TH 8TH 9TH 10TH 11TH5TH 0.05 –0.10 0.00 –0.05 4TH 1ST 2ND 3RD 6TH 7TH 8TH 9TH 10TH 11TH5TH4TH DIFF GAIN – % TPC 44. Differential Gain and Phase @ V S = ±5 V; RL = 1 kW FREQUENCY – Hz INPUT VOL T AGE NOISE – nV/ Hz 0.3 100 10 100 1k 10k 100k 10M1M 100 0.1 VOLTAGE NOISE CURRENT NOISE INPUT CURRENT NOISE – pA/ Hz VS = 5V TPC 45. Input Voltage Noise vs. Frequency

REV. A AD15700 –23– FREQUENCY – MHz 0.1 1 10 100 NORMALIZED GAIN – dB VS = 5V G = +1 RL = 1k/H9024 TPC 46. Unity Gain, –3 dB Bandwidth FREQUENCY – MHz 0.1 1 10 100 NORMALIZED GAIN – dB VOUT 50/H9024 2k/H9024 VS VIN VS = 5V VIN = –16dBm +85/H11543C +25/H11543C –40/H11543C TPC 47. Closed-Loop Gain vs. Temperature FREQUENCY – Hz CLOSED-LOOP GAIN – dB VS = 5V RL + CL TO 2.5V G = +1 CL = 5pF RL = 1k/H9024 VS = –2.7V RL + CL TO 1.35V VS = 65V 10k 1M 10M 100M TPC 48. Closed-Loop Gain vs. Supply Voltage FREQUENCY – MHz PHASE – Degree –90 –180 –135 –225 0.3 11 0 100 –10 –20 OPEN-LOOP GAIN – dB GAIN PHASE TPC 49. Open-Loop Frequency Response FUNDAMENT AL FREQUENCY – Hz –30 TOTAL HARMONIC DISTORTION – dBc –40 –70 –50 –60 –20 –80 1k 10k 100k 10M1M G = +1, RL = 2k/H9024 TO VCC 2.5V p-p VS = 2.7V 1.3V p-p VS = 2.7V 4.8V p-p VS = 5V 2V p-p VS = 2.7V TPC 50. Total Harmonic Distortion vs. Frequency; G = +1 FUNDAMENT AL FREQUENCY – Hz –30 TOTAL HARMONIC DISTORTION – dBc –40 –70 –50 –60 –20 –80 1k 10k 100k 10M1M –90 –100 G = +2 VS = 5V RL = 1k/H9024 TO VCC 4.6V p-p 4.8V p-p 4V p-p 1V p-p TPC 51. Total Harmonic Distortion vs. Frequency; G = +2

REV. A–24– AD15700 FUNDAMENT AL FREQUENCY – Hz OUTPUT – V p-p 1k 10k 100k 10M1M VS = 65V VS = 5V VS = 2.7V TPC 52. Large Signal Response FREQUENCY – MHz 0.1 1 10 100 ROUT – /H9024 0.1 100 VOUTRB– RBT = 50/H9024 RBT = 0 200 TPC 53. R OUT vs. Frequency FREQUENCY – Hz COMMON-MODE REJECTION RA TIO – dB –40 –20 –60 –80 –100 VS = 5V 1k 10k 100k 10M1M100 TPC 54. CMRR vs. Frequency FREQUENCY – Hz POWER SUPPL Y REJECTION RA TIO – dB –40 –20 –60 –80 –100 1k 10k 100k 10M1M100 100M –120 VS = 5V TPC 55. PSRR vs. Frequency 10/H9262s/DIV 1V/DIV 2.5 4.5 3.5 1.5 0.5 –0.5 5.5 VS = 5V RL = 10k/H9024 TO 2.5V VIN = 6V p-p G = +1 TPC 56. Output Voltage 10/H9262s/DIV 1V/DIV 2.5 4.5 3.5 1.5 0.5 –0.5 5.5 INPUT BEYOND RAILS VS = 5V G = +1 INPUT = 650mV TPC 57. Output Voltage Phase Reversal Behavior

REV. A AD15700 –25– 10/H9262s/DIV 500mV/DIV VS = 5V RL = 1kV G = –1 RL TO 2.5V RL TO GND TPC 58. Output Swing 50ns/DIV 200mV/DIV 2.5 2.9 2.7 2.3 2.1 1.9 3.1 G = +2 RF = RG = 2.5k/H9024 RL = 2k/H9024 CL = 5pF VS = 5V TPC 59. 1 V Step Response 10/H9262s/DIV 500mV/DIV 1.35 2.35 1.85 0.85 0.35 2.85 VS = 27V RL = 1k/H9024 G = –1 RL TO GND RL TO 1.35V TPC 60. Output Swing 50ns/DIV 20mV/DIV 2.50 2.54 2.52 2.48 2.44 2.56 2.46 G = +1 RF = 0 RL = 2k/H9024 TO 2.5V CL = 5pF TO 2.5V VS = 5V TPC 61. 100 mV Step Response

capacitor array at a 16-bit level (0.0015%). any is used (0 V to 2.5 V range). FSR is the full-scale span (i.e., 5 V for ± 2.5 V range). a 3.2 MHz RC filter, the SNR degrades by about 1.3 dB. frequency that the driver should preferably exceed. reference input REF of the ADC has a dynamic input impedance. REF and REFGND inputs with minimum parasitic inductance. tempco of the reference changes the full scale by ± 1 LSB/∞C. provide low total noise within the input bandwidth of the ADC. direct interface with any logic working between 2.7 V and 5.25 V. range, as shown in Figure 12.

40 PSRR – dB

Figure 12. PSRR vs. Frequency ideal for very low power battery applications. range, 0 V to 5 V or 0 V to 10 V, is used. should not exceed DVDD by more than 0.3 V.

The layout of the decoupling of the reference voltage is important. with short and large traces to minimize parasitic inductances. Figure 27. Digital Feedthrough Figure 28. Digital-to-Analog Glitch Impulse Figure 29. Large Signal Settling Time Figure 30. Small Signal Settling Time The DAC architecture consists of two matched DAC sections.

15 EQUAL SEGMENTS

Figure 31. DAC Architecture the equation simplifies to the following. full scale loaded to the DAC. The LSB size is VREF/16,384.

CS_DAC transfers the contents of the shift register to the DAC. Data can only be loaded to the part while CS_DAC is low. The DAC is capable of driving unbuffered loads of 60 k W. Figure 32. Unipolar Output be calculated from the following equation. unless the application does not use codes near zero. impedance (approximately 6 kW) will add to the zero code error. effective settling time of the combined DAC and amplifier. ferred to be able to handle dynamic currents of up to ± 20 mA. outlines the analog output voltage for particular digital codes. contains all zeros, until data is loaded from the serial register. tantalum capacitor in parallel with a 0.1 nF ceramic capacitor. may be done automatically when all the data is clocked in.

REV. A–42– AD15700 AD15700 PINOUT (TOP VIEW) COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON A B C D E F G H J K L 12 34 567 8 9 1 0 1 1 1 2 COMMON COMMON COMMON 1234 5678 9 1 0 1 1 1 2 A B C D E F G H COMMON COMMON COMMONCOMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON VREF AGND DAC VOUT RP AD1 RB1 –IN1 +VS1 CS_DAC RA1 –VS1 –VS1 VOUT1 AGND DAC AGND DAC VDD DAC +IN1 RC1 SCLK DIN DGND DAC CNVST RD D15 D14 RESET +VS2 D13 D12 –IN2 –VS2 REF TEST1 BUSY D11 RDERROR D10 SYNC –VS2 +IN2 RC2 COMMON REFGND INA RP AD2 RB2 IND AVDD WARP SER/PAR D0 D2 DIVSCLK0 EXT/INT AGND ADC RA2 INC BYTE SWAP OB/2C IMPULSE D1 D3 DIVSCLK1 INVSYNC VOUT2 INB PD CS_ADC D6 INVSCLK RDC/SDN INGND AGND ADC AGND ADC OGND OVDD DVDD TEST0 AGND ADC DGND ADC SCLK SDOUT M J K L M

REV. A AD15700 –43– OUTLINE DIMENSIONS 144-Lead Chip Scale Ball Grid Array [CSPBGA] (BC-144) Dimensions shown in millimeters SEATING PLANE

0.25 MIN

0.55 0.50 0.45 BALL DIAMETER

0.12 MAX

1.70 MAX DETAIL A 0.80 BSC

8.80 BSC

A B C D E F G H J K L M 12 11 10 9 8 7 6 5 4 3 2 1 TOP VIEW

10.00 BSC SQ

COMPLIANT TO JEDEC STANDARDS MO-205AC NOTES 1. THE ACTUAL POSITION OF THE BALL POPULATION IS WITHIN 0.15 OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES 2. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.08 OF ITS IDEAL POSITION RELATIVE TO THE BALL POPULATION

0.85 MIN

REV. A C03025–0–2/03(A) PRINTED IN U.S.A. –44– AD15700

Revision History

2/03—Data Sheet changed from REV. 0 to REV. A.