AD1555/56-REF

AD1555APZRL AD | Alldatasheet

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REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD1555/AD1556 Tel: 781/329-4700www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 FUNCTIONAL BLOCK DIAGRAM MUX PGA REF DIVIDER DAC MODE CONTROL LOGIC OVERVOLTAGE DETECTION CLOCK GENERATION LOOP FILTER REFIN REFCAP2 REFCAP1 AGND3 DGNDVL–VA+VAAGND2MODINPGAOUTAGND1 CLKIN SYNC BW0...BW2 RESET PWRDN GND V L AIN (+) AIN (–) TIN (+) TIN (–) AD1555 CB0...CB4 PGA CONTROL CONFIGURATION REGISTER STATUS REGISTER INPUT MUX MFLG MDATA TDATA CSEL MCLK INPUT SHIFT REGISTER DIN SCLK CS R/W DOUT DRDY RSELCLOCK DIVIDER DATA OUTPUT MUX DATA REGISTER AD1556 H/S ERRORPGA0...PGA4 DIGITAL FILTER 24-Bit /H9018-/H9004 ADC with Low Noise PGA

FEATURES

Fourth Order /H9018-/H9004 Modulator Large Dynamic Range 116 dB Min, 120 dB Typical @ 1 ms 117 dB Typical @ 0.5 ms Low Input Noise: 80 nV rms @ 4 ms with Gain of 34,128 Low Distortion: –111 dB Max, –120 dB Typical Low Intermodulation: 122 dB Sampling Rate at 256 kSPS Very High Jitter Tolerance No External Antialias Filter Required Programmable Gain Front End Input Range: /H115502.25 V Robust Inputs Gain Settings: 1, 2.5, 8.5, 34, 128 Common-Mode Rejection (DC to 1 kHz) 93 dB Min, 101 dB Typical @ Gain of 1 77 mW Typical Low Power Dissipation Standby Modes AD1556 FIR Digital Filter/Decimator Serial or Parallel Selection of Configuration Output Word Rates: 250 SPS to 16 kSPS 6.2 mW Typ Low Power Dissipation 70 /H9262W in Standby Mode Reference Design and Evaluation Board with Softwar e Available

APPLICATIONS

Seismic Data Acquisition Systems Chromatography Automatic Test Equipment GENERAL DESCRIPTION The AD1555 is a complete sigma-delta modulator, combined with a programmable gain amplifier intended for low frequency, high dynamic range measurement applications. The AD1555 outputs a ones-density bitstream proportional to the analog input. When used in conjunction with the AD1556 digital filter/ decimator, a high performance ADC is realized. The continuous-time analog modulator input architecture avoids the need for an external antialias filter. The programmable gain front end simplifies system design, extends the dynamic range, and reduces the system board area. Low operating power and standby modes makes the AD1555 ideal for remote battery-pow- ered data acquisition systems. The AD1555 is fabricated on Analog Devices’ BiCMOS process that has high performance bipolar devices along with CMOS transistors. The AD1555 and AD1556 are packaged, respectively, in 28-lead PLCC and 44-lead MQFP packages and are specified from –55°C to +85°C (AD1556 and AD1555 B Grade) and from 0°C to 85°C (AD1555 A Grade). FREQUENCY – Hz –120 –200 0 50 AMPLITUDE – dBr 100 150 200 250 300 –20 –100 –140 –180 –60 –80 –160 –40 350 400 450 500 fIN = 24.4Hz SNR = 116.7dB THD = –120.6dB Figure 1. FFT Plot, Full-Scale AIN Input, Gain of 1

REV. B AD1555/AD1556 –2– AD1555BP AD1555AP Parameter Notes Min Typ Max Min Typ Max Unit PGA Gain Settings 1, 2.5, 8.5, 34, 128 AC ACCURACY Dynamic Range1 PGA Gain of 1 116.5 120 116 120 dB PGA Gain of 2.5 116 119.5 115.5 119.5 dB PGA Gain of 8.5 114 117.5 114 117.5 dB PGA Gain of 34 104.5 109.5 104.5 109.5 dB PGA Gain of 128 98 98 dB Total Harmonic Distortion

2 PGA Gain of 1 –120 –111 –120 –107 dB

PGA Gain of 2.5 –116 –108 –116 –107 dB PGA Gain of 8.5 –116 –106 –116 –105 dB PGA Gain of 34 –115 –101 –115 –101 dB PGA Gain of 128 –108 –108 dB Jitter Tolerance 3 300 300 ps Intermodulation Distortion 4 PGA Gain of 1 122 122 dB DC ACCURACY PGA Gain of 34 –10 +10 –10 +10 % Gain Stability Over Temperature 5 ± 15 ± 15 ppm/ °C Offset5, 6 All PGA Gain –60 –60 mV Offset Drift5, 6 66 µV/°C ANALOG INPUT Full-Scale Nondifferential Input MODIN ± 2.25 ± 2.25 V Input Impedance MODIN 20 20 k /H9024 Full-Scale Differential Input PGA Gain of 1 ± 2.25 ± 2.25 V Other PGA Gain Settings See Table I See Table I Differential Input Impedance AIN, TIN Inputs 140 140 M Ω Common-Mode Range ± 2.25 ± 2.25 V Common-Mode Rejection Ratio V CM = ±2.25 V, fIN = 200 Hz PGA Gain of 1 93 101 91 101 dB PGA Gain of 2.5 95 102 91.5 102 dB PGA Gain of 8.5, 34 95.5 108 94.5 108 dB PGA Gain of 128 108 108 dB Power Supply Rejection Ratio 7 50 50 dB AIN to TIN Crosstalk Isolation f IN = 200 Hz 130 130 dB Differential Input Current 130 130 nA TEMPERATURE RANGE 8 Specified Performance T MIN to TMAX –55 +85 0 85 °C REFERENCE INPUT 9 Input Current 130 130 µA DIGITAL INPUTS OUTPUTS VIH 2.0 V L + 0.3 2.0 V L + 0.3 V IIL –10 +10 –10 +10 µA IIH –10 +10 –10 +10 µA VOL ISINK = +2 mA 0.4 0.4 V VOH ISOURCE = –2 mA 2.4 2.4 V AD1555–SPECIFICATIONS (+VA = +5 V; –V A = –5 V; V L = 5 V; AGND = DGND = 0 V; MCLK = 256 kHz; T A = TMIN to TMAX, unless otherwise noted.)

REV. B –3– AD1555/AD1556 AD1556–SPECIFICATIONS AD1556AS Parameter Notes Min Typ Max Unit FILTER PERFORMANCES Pass-Band Ripple –0.05 +0.05 dB Stop-Band Attenuation All Filters Except F O =16 kHz –135 dB FO =16 kHz –86 dB Filters Characteristics See Table II DIGITAL INPUTS OUTPUTS VIL –0.3 +0.8 V VIH +2.0 V L + 0.3 V IIL –10 +10 µA IIH –10 +10 µA VOL ISINK = +2 mA +0.5 V VOH ISOURCE = –2 mA V L – 0.6 V POWER SUPPLIES Specified Performance VL 2.85 5.25 V Quiescent Currents I(VL) 45 m A Power Dissipation V L = 3.3 V, FO = 1 kHz 6.2 8.5 mW In Power-Down Mode 70 µW TEMPERATURE RANGE* Specified Performance, T MIN to TMAX –55 +85 °C *Contact factory for extended temperature range. Specifications subject to change without notice. AD1555BP AD1555AP Parameter Notes Min Typ Max Min Typ Max Unit POWER SUPPLIES Recommended Operating Conditions +VA 4.75 5 5.25 4.75 5 5.25 V VL 4.75 5 5.25 4.75 5 5.25 V Quiescent Currents I(+VA)10 81 0 81 0 m A I(–VA)10 8 9.5 8 9.5 mA I(VL) 30 42 30 42 µA Power Dissipation 10 77 96 77 96 mW PGA in Standby Mode 11 56 70 56 70 mW In Power-Down Mode 11, 12 Reference Input = 3 V 650 650 µW Reference Input = 0 V 250 250 µW NOTES 1Tested at the output word rate F O = 1 kHz. FO is the AD1556 output word rate, the inverse of the sampling rate. See Tables I, Ia, Ib for other output word rates. 2Tested with a full-scale input signal at approximately 24 Hz. 3This parameter is guaranteed by design. 4Tested at the output word rate F O = 1 kHz with input signals of 30 Hz and 50 Hz, each 6 dB down full scale. 5This specification is for the AD1555 only and does not include the errors from external components as, for instance, the extern al reference. 6This offset specification is referred to the modulator output. 7Characterized with a 100 mV p-p sine wave applied separately to each supply. 8Contact factory for extended temperature range. 9Recommended Reference: AD780BR. 10Specified with analog inputs grounded. 11See Table III for configuration conditions. 12Specified with MCLK input grounded. Specifications subject to change without notice. (VL = 2.85 V to 5.25 V; CLKIN = 1.024 MHz; T A = TMIN to TMAX unless otherwise noted.)

REV. B AD1555/AD1556 –4– Table I. Dynamic and Noise Typical Performances Input and Gain MODIN PGA = 1 (0 dB) PGA = 2.5 (8 dB) PGA = 8.5 (19 dB) PGA = 34 (31 dB) PGA = 128 (42 dB) Input Range 1.6 V rms 1.6 V rms 636 mV rms 187 mV rms 47 mV rms 12.4 mV rms Dynamic Range FO = 16 kHz (1/16 ms) 40 d B4 0 d B 4 0d B 4 0d B 4 0d B 4 0d B FO = 8 kHz (1/8 ms) 69 dB 69 dB 69 dB 69 dB 69 dB 69 dB FO = 4 kHz (1/4 ms) 98 dB 98 dB 98 dB 98 dB 97 dB 91 dB FO = 2 kHz (1/2 ms) 117 dB 117 dB 116.5 dB 114.5 dB 106.5 dB 95 dB FO = 1 kHz (1 ms) 120 dB 120 dB 119.5 dB 117.5 dB 109.5 dB 98 dB FO = 500 Hz (2 ms) 123 dB 123 dB 122.5 dB 120 dB 112.5 dB 101 dB FO = 250 Hz (4 ms) 126 dB 126 dB 125.5 dB 123 dB 115.5 dB 104 dB Equivalent Input Noise FO = 16 kHz (1/16 ms) 15.5 mV rms 15.5 mV rms 6.17 mV rms 1.84 mV rms 470 µV rms 138 µV rms FO = 8 kHz (1/8 ms) 560 µV rms 560 µV rms 220 µV rms 65.5 µV rms 16.4 µV rms 4.5 µV rms FO = 4 kHz (1/4 ms) 20 µV rms 20 µV rms 8 µV rms 2.36 µV rms 661 nV rms 351 nV rms FO = 2 kHz (1/2 ms) 2.25 µV rms 2.25 µV rms 952 nV rms 353 nV rms 225 nV rms 223 nV rms FO = 1 kHz (1 ms) 1.59 µV rms 1.59 µV rms 674 nV rms 250 nV rms 159 nV rms 159 nV rms FO = 500 Hz (2 ms) 1.13 µV rms 1.13 µV rms 477 nV rms 187 nV rms 113 nV rms 111 nV rms FO = 250 Hz (4 ms) 797 nV rms 797 nV rms 338 nV rms 133 nV rms 80 nV rms 79 nV rms Table Ia. Minimum Dynamic Performances (AD1555AP Only) * Input and Gain MODIN PGA = 1 (0 dB) PGA = 2.5 (8 dB) PGA = 8.5 (19 dB) PGA = 34 (31 dB) FO = 1 kHz (1 ms) 116 116 115.5 114 104.5 FO = 500 Hz (2 ms) 119 119 118.5 117 107.5 FO = 250 Hz (4 ms) 122 122 121.5 120 110.5 *Not tested in production. Guaranteed by design. Table Ib. Minimum Dynamic Performances (AD1555BP Only) * Input and Gain MODIN PGA = 1 (0 dB) PGA = 2.5 (8 dB) PGA = 8.5 (19 dB) PGA = 34 (31 dB) FO = 1 kHz (1 ms) 116.5 116.5 116 114 104.5 FO = 500 Hz (2 ms) 119.5 119.5 119 117 107.5 FO = 250 Hz (4 ms) 122.5 122.5 121 120 110.5 *Not tested in production. Guaranteed by design. Table II. Filter Characteristics Output Word Rate FO Pass Band –3 dB Frequency Stop Band Group Delay (Sampling Rate in ms) (Hz) (Hz) (Hz) (ms) 16000 Hz (1/16 ms) 6000 6480 8000 0.984 8000 Hz (1/8 ms) 3000 3267.5 4000 3

4000 Hz (1/4 ms) 1500 1634 2000 6

2000 Hz (1/2 ms) 750 816.9 1000 12 1000 Hz (1 ms) 375 408.5 500 24 500 Hz (2 ms) 187.5 204.2 250 48 250 Hz (4 ms) 93.75 101.4 125 93

1The gain of the modulator is proportional to f CLKIN and MCLK frequency. 2With DRDYBUF low only. When DRDYBUF is high, this timing also depends on the value of the external pull-down resistor. Specifications subject to change without notice. Figure 2. Load Circuit for Digital Interface Timing

REV. B AD1555/AD1556 –8– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1555/AD1556 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ABSOLUTE MAXIMUM RATINGS 1 Analog Inputs Supply Voltages Ground Voltage Differences Internal Power Dissipation 2 Lead Temperature Range NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Specification is for device in free air: 28-lead PLCC: θJA = 36°C/W, θJC = 20°C/W 44-lead MQFP: θJA = 36°C/W, θJC = 14°C/W ORDERING GUIDE Temperature Package Package Model Range * Description Option AD1555AP 0 °C to 85°C Plastic Lead Chip Carrier P-28A AD1555APRL 0 °C to 85°C Plastic Lead Chip Carrier P-28A AD1555BP –55 °C to +85 °C Plastic Lead Chip Carrier P-28A AD1555BPRL –55 °C to +85 °C Plastic Lead Chip Carrier P-28A AD1556AS –55 °C to +85 °C Plastic Quad Flatpack S-44A AD1556ASRL –55 °C to +85 °C Plastic Quad Flatpack S-44A EVAL-AD1555/AD1556EB Evaluation Board AD1555/56-REF Reference Design *Contact factory for extended temperature range.

REV. B AD1555/AD1556 –9– PIN CONFIGURATION 28-Lead PLCC (P-28A) 4 3 2 1 28 27 26 PIN 1 TOP VIEW (Not to Scale) 12 13 14 15 16 17 18 REFIN REFCAP2 AGND3 –VA –VA VL AIN(+) AIN(–) TIN(+) NC CB0 CB1 –VA +VA PGAOUT AGND1 MODIN AGND2 +VA CB2 CB3 CB4 MFLG DGND MDATA MCLK NC = NO CONNECT (DO NOT CONNECT THIS PIN) AD1555 TIN(–) REFCAP1 44-Lead MQFP (S-44A) 40 39 3841424344 36 35 34 37 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) 12 13 14 15 16 17 18 19 20 21 22ERROR NC VL NC CLKIN SYNC TDATA CSEL NC NC AD1556 R/W DGND SCLK DOUT DRDY CS RSEL NC PGA0 PGA1 PGA2 PGA3 PGA4 BW0 NC = NO CONNECT BW1 BW2 H/S V L PWRDN RESET DGND DGND DIN VL CB0 CB1 CB2 CB3 CB4 MFLG RESETD MDATA MCLK DGND

REV. B AD1555/AD1556 –10– AD1555 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description

1 AGND1 Analog Ground

2 PGAOUT Programmable Gain Amplifier Output. The output of the on-chip programmable gain amplifier is available at this pin. Refer to Table III for PGA gain settings selection. 3, 26 +V A Positive Analog Supply Voltage. +5 V nominal. 4, 20, 21 –V A Negative Analog Supply Voltage. –5 V nominal. 5 AIN(+) Mux Input. Noninverting signal to the PGA mux input. Refer to Table III for input selection. 6 AIN(–) Mux Input. Inverting signal to the PGA mux input. Refer to Table III for input selection. 7 TIN(+) Mux Input. Noninverting test signal to the PGA mux input. Refer to Table III for input selection. 8 TIN(–) Mux Input. Inverting test signal to the PGA mux input. Refer to Table III for input selection. 9N CP in for Factory Use Only. This pin must be kept not connected for normal operation. 10–14 CB0–CB4 Modulator Control. These input pins control the mux selection, the PGA gain settings, and the standby modes of the AD1555. When used with the AD1556, these pins are generally directly tied to the CB0–CB4 output pins of the AD1556. CB0–CB2 are generally used to set the PGA gain or cause it to enter in the PGA standby mode (refer to Table III). CB3 and CB4 select the mux input voltage applied to the PGA as described in Table III. 15 MFLG Modulator Error. Digital output that is pulsed high if an overrange condition occurs in the modulator.

16 DGND Digital Ground

17 MDATA Modulator Output. The bitstream generated by the modulator is output in a return-to-zero data format. The data is valid for approximately one-half a MCLK cycle. Refer to Figure 3. 18 MCLK Clock Input. The clock input signal, nominally 256 kHz, provides the necessary clock for the Σ-∆ modulator. When this input is static, AD1555 is in the power-down mode. 19 V L Positive Digital Supply Voltage. 5 V Nominal. 22 AGND3 Analog Ground. Used as the ground reference for the REFIN pin. 23 REFCAP1 DAC Reference Filter. The reference input is internally divided and available at this pin to provide the reference for the /H9018-/H9004 modulator. Connect an external 22 µF (5 V min) tantalum capacitor from REFCAP1 to AGND3 to filter the external reference noise. 24 REFCAP2 Reference Filter. The reference input is internally divided and available at this pin. 25 REFIN Reference Input. This input accepts a 3 V level that is internally divided to provide the reference for the Σ-∆ modulator. 27 AGND2 Analog Ground. 28 MODIN Modulator I nput. Analog input to the modulator. Normally, this input is directly tied to PGAOUT output. AD1556 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1, 21, 27, 28, NC No Connect 2–6 PGA0–PGA4 PGA and MUX Control Inputs. Sets the logic level of CB0-CB4 output pins respectively and the state of the corresponding bit in the configuration register upon RESET or when in hardware mode. Refer to Table III. 7–9 BW0–BW2 Output Rate Control Inputs. Sets the digital filter decimation rate and the state of the correspond- ing bit in the configuration register upon RESET or when in hardware mode. Refer to the Filter Specifications and Table VI. 10 H/ S Hardware/Software Mode Select. Determines how the device operation is controlled. In hardware mode, H/S is high, the state of hardware pins set the mode of operation. When H/ S is low, a write sequence to the Configuration Register or a previous write sequence sets the device operation. 11, 22, 44 V L Positive Digital Supply Voltage. 3.3 V or 5 V nominal. 12, 23, 24, 34 DGND Digital Ground 13 SCLK Serial Data Clock. Synchronizes data transfer to either write data on the DIN input pin or read data on the DOUT output pin.

REV. B AD1555/AD1556 –11– AD1556 PIN FUNCTION DESCRIPTIONS (continued) Pin No. Mnemonic Description 14 DOUT Serial Data Output. DOUT is used to access the conversion results or the contents of the Status Register, depending on the logic state of the RSEL pin. At the beginning of a read operation, the first data bit is output (MSB first). The data changes on the rising edge of SCLK and is valid on the SCLK falling edge. 15 DRDY Data Ready. A logic high output indicates that data is ready to be accessed from the Output Data Register. DRDY goes low once a read operation is complete. When selected, the DRDY output pin has a type buffer that allows wired-OR connection of multiple AD1556s. 16 CS Chip Select. When set low the serial data interface pins DIN, DOUT, R/ W, and SCLK are active; a logic high disables these pins and sets the DOUT pin to Hi-Z. 17 R/ W Read/Write. A read operation is initiated if R/ W is high and CS is low. A low sets the DOUT pin to Hi-Z and allows a write operation to the device via the DIN pin. 18 RSEL Register Select. When set high, the Conversion Data Register contents are output on a read opera- tion. A low selects the Status Register. 19 DIN Serial Data Input. Used during a write operation. Loads the Configuration Register via the Input Shift Register. Data is loaded MSB first and must be valid on the falling edge of SCLK. 20 ERROR Error Flag. A logic low output indicates an error condition occurred in the modulator or digital filter. When ERROR goes low the ERROR bit in the status register is set high. The ERROR output pin has an open drain type buffer with an internal 100 k Ω typical pull-up that allows wired-OR connection of multiple AD1556s. 25 RESET Chip Reset. A logic high input clears any error condition in the status register and sets the configuration register to the state of the corresponding hardware pins. On power-up, this reset state is entered. 26 PWRDN Power-Down Hardware Control. A logic high input powers down the filter. The convolution cycles in the digital filter and the MCLK signal are stopped. All registers retain their data and the serial data interface remains active. The power-down mode is entered on the first falling edge of CLKIN after PWRDN is taken high. When exiting the power-down mode, a SYNC must be applied to resume filter convolutions. 29 CSEL Filter Input Select. Selects the source for input to the digital filter. A logic high selects the TDATA input, a low selects MDATA as the filter input. 30 TDATA Test Data. Input to digital filter for user test data. 31 SYNC Synchronization Input. The SYNC input clears the AD1556 filter in order to synchronize the start of the filter convolutions. The SYNC event is initiated on the first CLKIN rising edge after the SYNC pin goes high. The SYNC input can also be applied synchronously to the AD1556 decima- tion rate without resetting the convolution cycles. 32 CLKIN Clock Input. The clock input signal, nominally 1.024 MHz, provides the necessary clock for the AD1556. This clock frequency is divided by four to generate the MCLK signal for the AD1555. 35 MCLK Modulator Clock. Provides the modulator sampling clock frequency. The modulator always samples at one-fourth the CLKIN frequency. 36 MDATA Modulator Data. This input receives the ones-density bit stream from the AD1555 for input to the digital filter. 37 RESETD Decimator Reset. A logic high resets the decimator of the digital filter. 38 MFLG Modulator Error. The MFLG input is used to detect if an overrange condition occurred in the modulator. Its logic level is sensed on the rising edge of CLKIN. When overrange condition detected, ERROR goes low and updates the status register. 43–39 CB0–CB4 M odulator Control. These output control pins represent a portion of the data loaded into the AD1556 Configuration Register. CB0–CB2 are generally used to set the PGA gain or cause it to enter in the PGA standby mode (Refer to Table III). CB3 and CB4 select the mux input voltage applied to the PGA as described in Table III.

REV. B AD1555/AD1556 –12– TERMINOLOGY DYNAMIC RANGE Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together in the bandwidth from 3 Hz to the Nyquist frequency F O/2. The value for dynamic range is expressed in decibels. SIGNAL-TO-NOISE RATIO (SNR) SNR is the ratio of the rms value of the full-scale signal to the total rms noise in the bandwidth from 3 Hz to the Nyquist fre- quency F O/2. The value for SNR is expressed in decibels. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of all the harmonic components up to Nyquist frequency F O/2 to the rms value of a full-scale input signal. The value for THD is expressed in decibels. INTERMODULATION DISTORTION (IMD) IMD is the ratio of the rms sum of two sine wave signals of

30 Hz and 50 Hz which are each 6 dB down from full scale to

the rms sum of all intermodulation components within the bandwidth from 1 Hz to the Nyquist frequency F O/2. The value for IMD is expressed in decibels. OFFSET The offset is the difference between the ideal midscale input volt- age (0 V) and the actual voltage producing the midscale output code (code 000000H) at the output of the AD1556. The o ffset specification is referred to the output. This offset is intentionally set at a nominal value of –60 mV (see Sigma-Delta Modulator section). The value for offset is expressed in mV. OFFSET ERROR DRIFT The change of the offset over temperature. It is expressed in mV. GAIN ERROR The gain error is the ratio of the difference between the actual gain and the ideal gain to the ideal gain. The actual gain is the ratio of the output difference obtained with a full-scale analog input (± 2.25 V) to the full-scale span (4.5 V) after correction of the effects of the external components. It is expressed in %. GAIN ERROR STABILITY OVER TEMPERATURE The change of the gain error over temperature. It is expressed in %.

REV. B AD1555/AD1556 –13– Typical Performance Characteristics– FREQUENCY – Hz 0 50 100 150 200 250 300 350 400 450 500 –120 –200 AMPLITUDE – dBr –20 –100 –140 –180 –60 –80 –160 –40 fIN = 24.4Hz SNR = 116.7dB THD = –120dB TPC 1. FFT (2048 Points) Full-Scale MODIN Input –120AMPLITUDE – dBr –20 –100 –140 –180 –60 –80 –160 –40 FREQUENCY – Hz 50 100 150 200 250 300 350 400 450 500 –200 fIN = 24.4Hz SNR = 105.8dB THD = –114.9dB TPC 2. FFT (2048 Points) Full-Scale AIN Input, Gain of 34 FREQUENCY – Hz –120 –200 0 500 AMPLITUDE – dBr 1000 –20 –100 –140 –180 –60 –80 –160 –40 3500 40001500 2000 2500 3000 fIN = 24.4Hz SNR = 68.2dB THD = –120dB TPC 3. FFT (16384 Points) Full-Scale AIN Input, Gain of 1 130 TEMPERATURE – /H11543C 100 –55 –35 DYNAMIC RANGE – dB –15 110 120 85 10552 5 4 5 6 5 125 G = 1 G = 2.5 G = 8.5 G = 34 G = 128 TPC 4. Dynamic Range vs. Temperature DYNAMIC RANGE – dB –122 NUMBER OF UNITS –117 –121 –119 –118 –116 TPC 5. Dynamic Range Distribution (272 Units) TEMPERATURE – /H11543C –55 CMRR – dB 110 100 120 130 140 150 –35 5 45 125–15 25 65 85 105 G = 34 G = 2.5 G = 8.5 G = 1 G = 128 TPC 6. Common-Mode Rejection vs. Temperature

REV. B AD1555/AD1556 –14– CMRR – dB –128 NUMBER OF UNITS –98 –120 –113 –105 –90 TPC 7. Common-Mode Rejection Distribution (272 Units) FREQUENCY – Hz CMRR – dB 100 105 110 115 120 100 200 300 1000 500 800 900400 600 700 G = 8.5 G = 34 G = 2.5 G = 1 G = 128 TPC 8. Common-Mode Rejection vs. Frequency FREQUENCY – Hz –0.20 AMPLITUDE – dB 0.00 0.05 0.10 12525 50 75 100 –0.15 –0.10 –0.05 0.15 0.20 TPC 9. AD1556 Pass Band Ripple, F O = 250 Hz (4 ms) FREQUENCY – Hz –0.20 AMPLITUDE – dB 0.00 0.05 0.10 25050 100 150 200 –0.15 –0.10 –0.05 0.15 0.20 TPC 10. AD1556 Pass Band Ripple, F O = 500 Hz (2 ms) FREQUENCY – Hz –0.20 AMPLITUDE – dB 0.00 0.05 0.10 500100 200 300 400 –0.15 –0.10 –0.05 0.15 0.20 TPC 11. AD1556 Pass Band Ripple, F O = 1 kHz (1 ms) FREQUENCY – Hz –0.20 AMPLITUDE – dB 0.00 0.05 0.10 1000200 400 600 800 –0.15 –0.10 –0.05 0.15 0.20 TPC 12. AD1556 Pass Band Ripple, F O = 2 kHz (1/2 ms)

REV. B AD1555/AD1556 –15– FREQUENCY – Hz –0.20 AMPLITUDE – dB 0.00 0.05 0.10 500 1000 1500 2000 –0.15 –0.10 –0.05 0.15 0.20 TPC 13. AD1556 Pass Band Ripple, F O = 4 kHz (1/4 ms) FREQUENCY – Hz –0.20 AMPLITUDE – dB 0.00 0.05 0.10 1000 2000 3000 4000 –0.15 –0.10 –0.05 0.15 0.20 TPC 14. AD1556 Pass Band Ripple, F O = 8 kHz (1/8 ms) FREQUENCY – Hz –0.20 AMPLITUDE – dB 0.00 0.05 0.10 2000 4000 6000 8000 –0.15 –0.10 –0.05 0.15 0.20 TPC 15. AD1556 Pass Band Ripple, F O = 16 kHz (1/16 ms)

to avoid excessive power dissipation. interface of the AD1556 (H/ S pin low). action, allows various combinations. Figure 8. Simplified AD1555 Input Multiplexer resistor as a noise reference. and TIN(–) inputs and with PGA Gain of 1. AIN(–) input tied to TIN(–) input and with PGA Gain of 1.

tion, the gain setting is forced to be the gain of 1. PGA inputs, nominally 66 Ω, slightly affects these measurements. the PGA inputs is nominally 116 Ω. could be used to test the sensor isolation. Figure 9. Sigma-Delta Modulator Block Diagram benefits of both design techniques. switched-current feedback DAC. input range by adding an external series resistor at MODIN. high frequency noise is attenuated by the AD1556 digital filter. an OWR of 2 kHz or lower is generally preferred. band of interest and filtered out by the digital filter. is forced high. After 1.5 MCLK cycles, MFLG returns low.

the dynamic range performance of the AD1555/AD1556 chipset. a bitstream generated by other /H9018-/H9004 modulators. given in Figure 10. The basic architecture is a two-stage filter.

1. Each filter is a linear phase equiripple FIR implemented by

ing by multiplication and accumulation. multiplied by the 26-bit wide coefficients tallied in Table IV. which truncates the accumulator result to 24 bits. The second-stage filter architecture is similar to the first stage. Figure 10. AD1556 Filter Functional Block Diagram

REV. B AD1555/AD1556 –20– RESET Operation The RESET pin initializes the AD1556 in a known state. RESET is active on the next CLKIN rising edge after the RESET input is brought high as shown in Figure 4. The reset value of each bit of the configuration and the status registers are indicated in Table V and Table VIII. The filter memories are not cleared by the reset. Filter convolutions begin on the next CLKIN rising edge after the RESET input is returned low. A RESET operation is done on power-up, independent of the RESET pin state. In multiple ADCs applications where absolute synchroniza- tion—even below the noise floor—is required, RESETD, which resets the decimator, can be tied to RESET to ensure this synchronization. Power-Down Operation The PWRDN pin puts the AD1556 in a power-down state. PWRDN is active on the next CLKIN rising edge after the PWRDN input is brought high. While in this state, MCLK is held at a fixed level and the AD1555 is therefore powered down too. The serial interface remains active allowing read and write operations of the AD1556. The configuration and status registers maintain their content during the power-down state. SYNC Operation SYNC is used to create a relationship between the analog input signal and the output samples of the AD1556. The SYNC event does two things:

• It synchronizes the AD1555 clock, MCLK, to the AD1556 clock, CLKIN, as shown in Figure 3.
• It clears the filter and then initiates the filter convolution. Exactly one sampling rate delay later, the DRDY pin goes high. A SYNC event occurs on the next CLKIN rising edge after the SYNC input is brought high as shown in Figure 3. The D RDY output goes high on the next falling edge of CLKIN. SYNC may be applied once or kept high, or applied synchronously at the output word rate, all with the same effect. Configuring and Interfacing the AD1556 The AD1556 configuration can be loaded either by hardware (H/S pin high) or via the serial interface of the AD1556 (H/ S pin low). To operate with the AD1556, the CLKIN clock must be kept running at the nominal frequency of 1.024 MHz. Table V gives the description of each bit of the configuration register and Table VI defines the selection of the filter bandwidth. When the software mode is selected (H/S pin low), the configuration register is loaded using the pins DIN, SCLK, CS, and R/W. In this mode, when RESET is active, the configuration register mimics the selec- tion of the hardware pins. The AD1556 and the AD1555 can be put in power-down by software. The DRDYBUF bit controls the operating mode of the DRDY output pin. When the DRDYBUF bit is low, the DRDY is a con- ventional CMOS push-pull output buffer as shown in Figure 11. When the DRDYBUF bit is high, the DRDY output pin is an open drain PMOS pull-up as shown in Figure 11. Many DRDY pins may be connected with an external pull-down resistor in a wired OR to minimize the interconnection between the AD1556s and the microprocessor in multichannel applications. The DRDY pin is protected against bit contention. By connecting DRDY to RSEL directly, and applying 48 SCLK cycles, both data and status can be read sequentially, data register first. Table VI. Filter Bandwidth Selection BW2 BW1 BW0 Output Rate (ms) 00 0 4 00 1 2 01 0 1 01 1 1/2 10 0 1/4 10 1 1/8 11 0 1/16 11 1R eserved Table V. Configuration Register Data Bits Bit Number Name Description RESET State DB15 (MSB) X X DB14 X X DB13 X X DB12 X X DB11 PWRDN Power-Down Mode PWRDN DB10 CSEL Select TDATA Input CSEL DB9 X X DB8 BW2 Filter Bandwidth Selection BW2 DB7 BW1 Filter Bandwidth Selection BW1 DB6 BW0 Filter Bandwidth Selection BW0 DB5 DRDYBUF DRDY Output Mode 0 (Push-Pull) DB4 CB4 PGA Input Select PGA4 DB3 CB3 PGA Input Select PGA3 DB2 CB2 PGA Gain Select PGA2 DB1 CB1 PGA Gain Select PGA1 DB0 (LSB) CB0 PGA Gain Select PGA0

Figure 11. DRDY Output Pin Configuration input voltage from –2.25 V to +2.25 V on the MODIN pin. tial error conditions and readback the configuration settings. The status register mapping is defined in Table VIII. RESET. The ERROR bit is the inverse of the ERROR output pin. register, the OVWR bit is set high. has occurred in the digital filter. status bits will not change. facilitates the use of ground planes that can be easily separated. duce the effect of feedthrough through the board. up against these pins and their corresponding ground pins. the vicinity of the ADC to further reduce low frequency ripple.

REV. B AD1555/AD1556 –22– Table VIII. Status Register Data Bits Bit Number Name Description RESET State DB23 (MSB) ERROR Detects One of the Following Errors 0 DB22 OVWR Read Sequence Overwrite Error 0 DB21 MFLG Modulator Flag Error MFLG DB20 X X DB19 ACC Accumulator Error 0 DB18 DRDY Data Ready 0 DB17 FLSTL Filter Settled 0 DB16 DRNG Output Data Not within AD1555 Range 0 DB15 X X DB14 X X DB13 X X DB12 X X DB11 PWRDN Power-Down Mode PWRDN DB10 CSEL Select TDATA Input CSEL DB9 X X DB8 BW2 Filter Bandwidth Selection BW2 DB7 BW1 Filter Bandwidth Selection BW1 DB6 BW0 Filter Bandwidth Selection BW0 DB5 X X DB4 CB4 PGA Input Select PGA4 DB3 CB3 PGA Input Select PGA3 DB2 CB2 PGA Gain Select PGA2 DB1 CB1 PGA Gain Select PGA1 DB0 (LSB) CB0 PGA Gain Select PGA0 The AD1555 has three different ground pins: AGND1, AGND2, and AGND3 plane, depending on the configuration. AGND1 should be a star point and be connected to the analog ground point. AGND2 should be directly tied to AGND1. A low impedance trace should connect in the following order: AGND3, the low side of the reference decoupling capacitor on REFCAP1, the ground of the reference voltage, and return to AGND1. Evaluating the AD1555/AD1556 Performance Performances of the AD1555/AD1556 can be evaluated with the evaluation board EVAL-AD1555/AD1556EB. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the PC printer port.

REV. B AD1555/AD1556 –23– OUTLINE DIMENSIONS Dimensions shown in inches and (mm) 28-Lead PLCC (P-28A) PIN 1 IDENTIFIER TOP VIEW (PINS DOWN) 0.495 (12.57) 0.485 (12.32)SQ 0.456 (11.58) 0.450 (11.43) SQ 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.020 (0.50) R 0.050 (1.27) BSC 0.021 (0.53) 0.013 (0.33) 0.430 (10.92) 0.026 (0.66) 0.180 (4.57) 0.165 (4.19) 0.040 (1.01) 0.025 (0.64) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.110 (2.79) 0.085 (2.16) 44-Lead MQFP (S-44A) TOP VIEW (PINS DOWN) 1 33 3444 0.530 (13.45) 0.510 (12.95)SQ 0.031 (0.80) BSC 0.018 (0.45) 0.012 (0.30) 0.398 (10.10) 0.390 (9.90) SQ 0.315 (8.00) REF 0.083 (2.10) 0.077 (1.95) 0.010 (0.25) MAX 0.009 (0.23) 0.005 (0.13) SEATING PLANE 0.096 (2.45) MAX 0.041 (1.03) 0.029 (0.73)

–24– C02053–0–5/02(B) PRINTED IN U.S.A.