AD1362 AD | Alldatasheet
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Gg ANALOG 16-Channel, 12-Bit DEVICES Data Acquisition System FEATURES FUNCTIONAL BLOCK DIAGRAM Pin and Functional Replacement for ADS62: coe toy aD Lower Power Dissipation O—OE-—-@)—-@—) Lower Noise on Gea v Internal Hold Capacitor on Gm)
16 Single-Ended or 8 Differential Channels with aga Qo oxo
Switchable Mode Control om True 12-Bit Precision: Nonlinearity <0.005% bot Oe High Speed: 10s Acquisition Time to 0.01% bot emousors tr> > rs gp asco Complete and Calibrated: No Additional Parts on eines Required on G- Versatile: Simple Interface to Popular Analog-to-Digital bad = Converters on @-4 LU High Differential Input Impedance (107°) and om Ga {owns | ‘Common Mode Rejection (80d8) on Cr a: Fully Protected Multiplexer Inputs @—@ O40) PRODUCT DESCRIPTION ge Gamer Se The AD1362 is a complete, precision16-channel data acquisition system. The device contains two 8-channel multiplexers, a dif- PRODUCT HIGHLIGHTS ferential amplifier, a sample-and-hold with high-speed ouput 1, The AD1362, when used with a precision analog to digital amplifier, a channel address latch and control logic. The multi- converter, forms a compictc, accurate, high-speed data plexers may be connected to the differential amplifier in either acquisition system. an 8-channel differential or 16-channel single-ended configura- 2. The 16-input channels may be configured in single-ended, tion, A unique feature of the AD1362 is an internal user- differential or a mixture of both modes. Mode switching is controllable analog switch that connects the multiplexers in provided by a user controllable internal analog switch. ereneonaen ot Se ite oa single 43. Multiplexers, differential amplifier, sample-and-hold and “ program- . . . ming and permits a mixture of single-ended and differential high-speed ‘output buffer provide complete analog interfacing sources to be interfaced by dynamically switching the input capabilities. mode control. 4. Internal channel address latches are provided to facilitate ‘The sample-and-hold mode control is designed to t interfacing the AD1362 to data, address or control buses. directly to the ‘‘Starus” output of an analog-to-digital converter 5, The AD1362 is specified over the entire military temperature so that a convert command to the ADC will automatically put range, —55°C to + 125°C. Processing to MIT.-STD-883, Class the sample-and-hold into the “Hold” mode. An internal preci- B is available. sion hold capacitor is included with cach AD1362. The AD1362 output amplifier is capable of driving the unbuffered analog input of most high speed, 12-bit successive-approximation ADCs. The interface is thereby reduced to two simple connec- tions with no additional components required. ‘The AD1362KD is specified for operation over a 0 to +70°C temperature range while the ADI362SD operates to specification from 55°C to + 125°C. Processing to MIL-STD-883, Class B is available for the AD1362SD. Both grades ure pickaged in 2 hermetic 32-pin ceramic dual-in-line package. REV.A : Information furnished by Analog Devices is baiaved to be sccurate and . , sibility is assum ices for it which may result from its use. No license is granted by implication or Tel: 617/329-4700 Fax: 617/326-8703 Tw: 710/394-6577 otherwise under sny patent or patent rights of Analog Devices. Telex: 924491 Cable: ANALOG NORWOOOMASS
AD1362—SPECIFICATIONS trea c +t, 151 an +5 V miss starsat AD1362KD AD1362SD Parameter Test Condition Mia Typ Max Min Typ Max | Units ANALOG INPUTS Input Voltage Range Tain 10 Trax -10 +10 v Toput Bias Current Per Channel =50 nA Input Impedance On Channel 10 Ga 100 pF Off Channel 0 Go 10 pF Input Fault Current Power Off or On 20 mA Common Mode Rejection Diff Mode, 1kHz, 20V p-p | 70 80 dB Mux Crosstalk, Any Off Ch to Any On Ch IkHz, 20V p-p -80 -90 dB Ch to Ch Offset 22.5 mV ACCURACY Gain Error Trin 80 Tmax 20.02 % FSR Offset Error Tio 10 Trax 24 mV Linearity Error @ 25°C 0,005 % Train tO Trae 20.01 % Noise Error 25°C, 0.1 to IMHz 05 mV pp Trin 10 Trnaxs 0-1 to IMH2 1.0 mV pp TEMPERATURE COEFFICIENTS Gain Train 10 Tyoax +4 42 ppm/PC Offset £10V Range, Tria tO Tmax +2 =1.5 | ppm*C SAMPLE AND HOLD DYNAMICS Aperture Delay 150 200 ns Aperture Uncertainty 100 500 ps Acquisition Time 20V Step to 20.01% 10 18 us Feedthrough kHz -80 -70 dB Droop Rate 1 2 mV/ms Pedestal Voltage 15 be +15 mV POWER SUPPLY REQUIREMENTS +V, Analog Voltage +14,28 +15.75 v -V, Analog Voltage -14.25 -1475 Vv +V, Digital Voltage $4.75 $5.25 Vv +V, Analog Current 30 mA ~V, Analog Current 30 mA +V, Digital Current 40 mA Total Power Dissipation 05 Ld Ww TEMPERATURE RANGE Specification 0 +70 -35 +125 | °C Storage -55 +85 —55 +1504 °C DIGITAL INPUT SIGNALS TT Signal Pins Loads Logic High Logic Low Input Channel Select 28-31 ILS (4-Bit Binary Address) ‘Channel Select Latch 32 8Ls ‘Transparent Latched Single Ended/Diff Mode Setect 1 3LS Differencial Single Ended Sample-and-Hold Command 13 2LS Hold Sample NOTE Tyg 20KA max @ Viy72.7V. \\ “Specifications same as ADI362KD. | d- REV. A
4+V, Digital Supply 0... eee eee eee ee PSSM Vyyy Signal 00.2 eee eee eee ss #V Analog Supply ORDERING GUIDE PIN ASSIGNMENTS Temperature Max Gain | Package saver conmmon [1] © [a2] waten sect Model Range Tc Option* vono [2 | pe] ADI362KD Oto +70°C 24ppm/C | DH-32E wD) [3] 1 AD1362SD 58°C w +125°C | *2ppm"C | DH-32E on (2) [23] a0 AD1362SD/883B | -S5°C to +128°C | +2ppm/C | DH-32E ow G] [ze] ae *DH-32E = Bottom Brazed Ceramic DIP. os GY [22] one oF] [as] ie cn oC] 202 lowe ova [a] Mette Seale) 150) corns in on Le] [as] cone iw ow G5] [22] cwsa ey wo commer [17] fay} +ssv wacuo [1] [20] -13v. onset aower [ia] [73] crass orract anwust [7] [ra] curs anaxoa ourrut [is] [72] sono Function | Number | Description Single/Diff Control 1 Mode Select, Differential or Single Ended DGND 2 Digital Ground +5V 3 Digital Power Supply, +5V de Ch7 4 “High” Analog Input Channel 7 Ch6 5 “High” Analog Input Channel 6 Chs 6 “High” Analog Input Channel $ Ch4 7 “High” Analog Input Channel 4 Ch3 8 | “High” Analog Input Channel 3 ch2 9 “High” Analog Input Channel 2 Gil 10 “High” Analog Input Channel 1 cho i “High” Analog Input Channel 0 NC R No Connect SHA Cmd 13 Sample/Hold Control Input to SHA Offset Adjust 4 Offset Adjusunent Input #1 Offset Adjust 1S Offset Adjustment Input #2 Analog Output 16 Analog Output to ADC. AGND 7 Analog Ground Chis 18 “High” (“Low”) Analog Input Channel 15 (7) Ch lt 9 “High” (“Low”) Analog Input Channel 14 (6) -15V 20 | Negative Analog Power Supply -15V de +15V 2 Positive Analog Power Supply +15V dc Ch 13 2 “High” (“Low”) Analog Input Channel 15 (5) ch i2 23 “High” (“Low”) Analog Input Channel 14 (4) Chil 4 “High” (“Low”) Analog Input Channel! 13 (3) Ch 10 2s “High” (“Low”) Analog Input Channel 12 (2) cho 2% “High” (“Low”) Analog Input Channel 11 (1) chs 27 “High” (“Low”) Analog Input Channel 10 (0) AE 28 Input Channel Address MSB AQ 2 Input Channel Address Bit 0 AL 30 Input Channel Address Bit 1 A2 31 Input Channel Address Rit 2 Latch Select 32 Channel Select Latch Control Input REV. A +
| tial amplifier, a sample-and-hold with high specd output buffer, input mode control. cout external hard-wire interconnections. Of more significance is addresses the multiplexers accordingly. AD1362 Block Diagram without loss of accuracy. ADI362 with ADC DAS application. handle than larger packages with higher pin counts.
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Figure 1. AD1362 with ADC as a Complete Data Acquisition System
oo 11 3 None AD1362, the circuit shown in Figure 3 is recommended.
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Figure 3. AD1362 Offset Voltage Adjustment input channel select address information is passed through to ADC Section. microseconds must be allowed for the sample-and-hold to offset voltage. the final value before a new Convert Start command is issued. leaving the sample-and-hold in a continuous Sample mode. Figure 4. Ground-Feult Protection Diodes
. in with a 0,039.F . it complete, two-package system. ‘analog to digital converters; often no additional components are perature range.
- The ADC Status output must be positive-true Logic (‘‘1” In this case, one of the above req:ir:ments is not met:
- Transition from “0” to “1” must occur at least 200ns before 2. DR does not indicate that a conversion is in progress until
the most significant bit decision is made (successive approxi- 1,Sys after conversion starts. 3, Status must not return to “0” before the LSB decision is more than 1,Sps so that DR may ‘hen assume control of Hold.
- If Status is being used to latch output data, it must not ne ronen
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a. 12-Bit DAS Using AD1362 and AD ADC80 b. 10-Bit Using AD *2=2 end AD573. Figure 5. Data Acquisition Systsems Based on the AD1362 and Popular ~°Cs
Figure 6. High Speed Data Acquisition Systems Based on AD1362 and Fast ADCs.