AD1334

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ANALOG DEVICES fAX-ON-DEMAND HOTLINE - Page 20 r. ANALOG L8II DEVICES

FEATURES

Four-ChannelAID ConverterforDSP Includes: Simultaneous or Independent Sampling Capability 12-8itAccurateAID Converter 2-8itChannellD Tags Each ConversionResult 32-Word FIFO Memory FullyAsynchronous, High Speed DigitalInterface Single-ChannelSample Rate Up to 67 kHz Four-ChannelSimultaneous Sample Rate Up to 28 kHz EntireSystem DynamicallyCharacterized Minimal EffectiveApertureDelay Mismatch from Channel-to-ChannelBeDevice-to-Device 15 ns Data Access Time Allows "'NoWait Staten Interfaceto: ADSp.2100 (A),TMS32OC25 DSP56000. NECp.PD77230 Low Power, 250 mW/Channel APPUCA TlONS Sonar SignalProcessing Robotics/MachineControl Disk-DriveHead Positioning VIbrationAnalysis PRODUCT DESCRIPTION The AD1334 isa four-channel,12-bit,sampling ND convener system optimizedforuse inmultichanneldigitalsignalprocess- ing (DSP) applications.The deviceconsistsof fourindependent sample-and-holdamplifiers,a multiplexer,an ND converter,a controller,a 32-word FIFO memory and a fullyasynchronous high speed digitalinterface.The product ispackaged in a 4O-pin hermeticDIP. The channelcontrollerenablesthe AD 1334 toappear as four independentchannelsof analoginputby generatingallof the timingnecessaryto ensurethatthe sampled channelisdigitized to 12-bitaccuracy.Upon receiptof a sample command, the con- trollerwillimmediatelyplacethe sample-and-holdamplifierinto hold mode and then prioritizeand schedulethe held valuefor ND conversion.At the appropriatetime,the sampled inputis gatedthrough themultiplexerand, aftersettling,isdigitizedby the ND convener. The sample-and-holdamplifieristhen re- turned to sample mode so thatitcan acquirethenext sample. REV. A Informationfurnishedby Analog Devices isbelievedto be accurateand reliable.However. no responsibilityisassumed by Analog Devicesforits use,nor forany infringementsof patentsor otherrightsofthirdparties which may resultfrom itsuse. No licenseisgranted by implicationor otherwise under any patentor patentrightsof Analog Devices. Four-Channel 12-BitSamplingAIDConverter forDigitalSignalProce~ing AD1334 I BLOCK DIAGRAM RE'OUT CHANC IN IRQ CHANI IN oC -013 CHAr;> IN OS ifST CHAN3 IN ill Wi< AD1334 SIMUL. 3 2 1 . ClK READY CONTROL SAMf'LE IN EN8 For effectiveuse in simultaneoussampling applications,the sample-and-holdamplifiersaredesignedtoprovidea minimum amount ofapenure delaytime mismatch from channel-to- channeland device-to-device. The 12-bitAID convertercan convert :t5 V fullscalesignalsat sample ratesup to67 kHz forsingle-channeloperation.In the simultaneousmode, the AD1334 has a four-channelsample rate up to 28 kHz. The entireconvertersystem isspecifiedand testedforsignal-to-noiseratio,rotalharmonic distortionand channel-to-channelisolation. The digitalinterfaceprovidesa trueasynchronouslinkbetween the ND and a high speed microprocessor.Data transferiscon- trolledby generatingan interruptsignalwhen dataisavailable. Interruptscan be generatedwhen the FIFO isfull(32words), half-full(16 words),or when a singleword of dataisready (FIFO bypassed).The AD1334 can alsogeneratean interrupt when the ND conversionresultsareoverrange. The AD1334 providesa completelyspecifiedand testedsystem thatbridgesthe interfaceand specificationgap between ND convertersand high speed DSP. Tel: 617/329-4700 Fax: 611/326-8703 Twx: 710/394-6577 Telex: 924491 Cable: ANALOG NORWOODMASS OBSOLETE

ANALOG DEVICES fAX-ON-DEMAND HOTLINE - Page 21 AD1334-SPECIFICATIONS(fA = +25°C. Vs = ::!:15V, YOO = +5 V and fCl~= 2.5 MHz unless noted) -2- REV. A ~ -~- - AD1334BD AD1334TD MiD Typ Max Min Typ Max Units Sill,MUX & AiD CONVERTER! InpUt Impedance 2 2.5 2 2.5 kll VoltageRange -S to +S -S to +5 V Output Coding OffsetBinary OffsetBinary CLK IN Frequency,(fcu) 1.0 2.5 1.0 2.S MHz High Time 200 200 ns Low Time 200 200 ns Sampling Rate Per Channel (fs) SimultaneousMode (SIMUL T = LOW)

1 Channel 67 67 kHz

2 Channels 46 46 kHz

3 Channels 35 35 kHz

4 Channels 28 28 kHz

IndependentMode (SIMULT = HIGH) I Channel 67 67 kHz

2 Channels 67 67 kHz

3 Channels 44 44 kHz

4 Channels 33 33 kHz

Droop Rate 0.2 1.0 0.2 1.0 mV/ms Over Temperature Doubles Every 10°C Doubles Every lOoC - 3 dB SmallSignalBandwidth 200 200 kHz Group Delay2 (fIN<lO kHz) 785 785 ns Aperture Delay3 0 10 15 0 10 15 fiS EffectiveApertureDelay4 (fIN<10 kHz) -700 -775 -850 -700 -775 -850 fiS StaticCharacteristics IntegralLinearity Error '"':112 +1 ::!:112 +1 LSB Over Temperature '"':I :tI 1/2 LSB DifferentialLinearity Error ::!:I :tl LSB Over Temperature ::!:1 '"':2 LSB - Full-ScaleError :t2 '"':4 '"':2 :t4 LSB Over TemperatUre :t4 :t8 :t4 :t13 LSB + Full-ScaleError :t2 '"':4 :t2 :t4 LSB Over TemperatUre :t4 '"':8 '"':4 :::13 LSB PSRR, :tVs :t1/2 ::t1/2 LSBN Dynamic Characteristics5.6 Signal-to-NoiseRatio, fIN = 13.6kHz 70 72 70 72 dB TotalHarmonic Distortion,fIN = 13.6kHz -86 -76 -86 -76 dB IntermodulationDistortion,fIN! = 13.1 kHz & flN2 = 13.6 kHz -86 -76 -86 -76 dB Channel-to-ChannelIsolation7,fu..:= 8.009kHz SIMULT = LOW 70 78 70 78 dB SIMUL T =:HIGH 74 74 dB ReferenceVoltage -5.05 -4.95 -5.05 -4.95 V Output Current :!::1 :t2 ::1::1 :::2 mA Drift ::1::10 :t30 :t1O :t30 ppml"C OBSOLETE

ANALOG DEVICES fAX-ON-DEMAND HOTLINE - Page 22 AD1334 NOTES 'Specifi,ationsare per ,hanne! in 4 Channel Simultaneous Mode (SAMPLE 0-3 'onne'ted togetherand SIMUL T & CONTROL ENB = LOW), at fs = 28 kHz, and with SAMPLE 0-3 having an 80% duty cycJeunless noted. lGroup delay isthe negativeof the 1stderivativeof phase with respe,tto frequency and isa measure of the analog time delay through the S/H. 'Aperture delay isthe time delay fmm the SAMPLE input to SIR switch opening and isa measure of the digitaltime delay through the S/H. 'Effectiveaperturedelay isthe differencebetween analog and digitaltime delays described in (2) and (3). 'THD of harmonics 2-7 of the fundament..J.SNR of fundamental lessharmonks 2-7. "Guaranteed over operating temperatUre and power supply voltagerange. 7Isoladonof anyone channel from remaining three channels which have near maximum amplitUde ac signalsat theirinputs. 8IoL = 4 mA for AD1334BD, IoL = 3.2 mA for AD1334TD; loB = -4 mA for AD1334BD, Iou = -3.2 mA for AD1334TD. 9RD, CS, AO = LOW; WR, RST = HIGH. Specificationssubject to change without notice. ORDERING GUIDE *D = Hermet;' Ceramic DIP. REV. A -3- AD 1334BD AD 1334TD MiD Typ Max Min Typ Max Units DIGITAL INPUTS6 VoltageInpUt,LOW +0.8 +0.8 V HIGH +2.0 +2.25 V Input Current ::t250 ::t250 j.LA Input Capacitance 5 5 pF RST LOW PulseWidth 10 10 ns... DIGITAL OUTPUTS6 I DO-DB, READY Ourpm Voltage,Logic LOWs +0.4 +0.4 V Output Voltage,Logic HIGHs +2.4 +2.4 V 3-StateLeakage Current ::t2S0 =250 f1A IRQ, CONTROL ENB Outpm Voltage,Logic LOWs +0.4 +0.4 V IRQ Off-StateLeakage ::t1O =10 j.LA Output Capacitance 5 5 pF FIFO Fall-ThruTime 400 800 400 800 fiS IRQ LOW toDO-DB Valid9 0 0 fiS POWER REQUIREMENTS OperatingRange Supply Current +V 47 60 47 60 mAs -Vs 39 50 39 50 mA +VDD 7 15 7 15 mA Consumption TEMPERATURE RANGE Operatingand Specified -40 +85 -55 + 125 °C Storage -65 +150 -65 d50 °C ... Temperature Package Model Range Option* AD1334BD -40°C to +8S0C DH-40A AD1334TD/883B - 55°C to + 125°C DH-40A OBSOLETE

ANALOG DEVICES fAX-ON-DEMAND HOTLINE - Page c3 AD1334 SW ITCHINGCHARACTERISTICS (~eroperatingtemperatureandpowersupplyvoltagerange, withCOUT= 30 pF or100pF exceptwherenoted) Specificationssubjectto change without notice. All specificacionsare guaranteed but Dot tested. ABSOLUTE MAXIMUM RATINGS. +VstoAPWRlASIGGND +l8V -VstoAPWRlASIGGND -18V VootoDGND +7V Analog Input to APWRIASIG GND -Vs 10 +Vs DigitalInput toAPWR GND SAMPLEo-SAMPLE3, CLK IN, SIMULT, CONTROL ENB -0.3 V to +7 V DigitalInput to DGND DO-DB, RD, WR, CS, AD, RST .. -0.3 V toVoo+O.3 V Output ShortCircuitDuration REFOUT,TP Indefinite Lead Temperature Range, .Stressesabove those listedunder "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stresseatingonly and functional operation of the device at these or any other conditions above those indi. cated in the operationalsectionsof thisspecificationisnot implied.Exposure to absolute maximum conditions for extended periods may affectdevice reliability. CAUTION ESD (electrostaticdischarge)sensitivedevice.The digitalcontrolinputsare diode protected; however, permanent damage may occur on unconnected devicessubjectto high energy electro- staticfields.Unused devicesmust be storedin conductivefoam or shunts.The protectivefoam should be dischargedtothe destinationsocketbeforedevicesareremoved. -4- REV. A Parameter Description Conditions Min Max Units READ CYCLE tRC Read Cycle Time GOUT = 30 pF 25 ns GOUT = 100 pF 35 ns tA Data Access Time GOUT = 30 pF 15 os GOUT = 100pF 25 us tLz Output Low Z Time 2 us 1HZ Output High Z Time GOUT = 30 pF 15 ns CoUT = 100pF 25 ns ToH Output Hold Time 2 ns thoRO AO Validto RD LOW 3 os tROAO RD HIGH toAO Invalid 3 us tAOCS AO ValidtoCS LOW 3 ns tcSAo CS HIGH toAO Invalid 3 os WRITE CYCLE twc Write Cycle Time 15 os twp Write PulseWidth 5 os tsu Data Setup Time 2 os tlR Input Hold Time 4 os tAOWR AO Valid10 WR LOW 3 ns tWRAO WR HIGH toAO Invalid 3 os thOCS AO ValidtoCS LOW 3 os tcSAO CS HIGH 10 AO Invalid 3 ns OBSOLETE

CS ISVALlD8EFORE OR COINCIOENTWITH IiQJiIGH-TO-LOWTAANSITION. WR ISNOT ACTIVE DURING READ CYCLE. CS ISVALID BEFORE OR COINCIDENT WITH ~HIGH' TO-LOW TRANSITION. RD ISNOT ACTIVE DURING WRITE CYCLE. fU!.ISVALID BEFORE OR COINCIDENT WITH qHIGH-TO-LOW TRANSITION. WR IS NOT ACTIVE DURING READ CYCLE. WR ISINVALID AFTER OR COINCIDENT WITH CS LOW- TO-HIGH TRANSITION. RD ISNOT ACTIVE DURING WRITE CYCLE. VT =' 15 V, the voltageto which 3-statedoutputs are forced. Figure 3. Output Load

Figure 4. Maximum Sample Rate vs. Figure 7. AID SNR vs.Frequency Figure 10. Normalized Data

60 SJMULT~I

Figure 5. Maximum Sample Rate vs. Figure 8. AID THD vs.Frequency Figure 12. Change inData

ANALOG DEVICES FAX-ON-DEHAND HOTLINE - Page ~6 AO1334 PIN CONFIGURATION II 28-22 19-13 20,21 CS AO DO-D6 D7-D 13 RD WR RST DGND, VDD REV. A CHANt IN CHANO IN +vs SAMPLE 0 SAMPLE 1 TP REF OUT ASIG OND APWR ONO IRQ CS AD (CHID MSB) 013 (CHID LSB) 012 (AID MSB) 011 010 DONO 01 400 02 390 03 380 04 370 05 360 06 350 01 340 0 8 AD1334 33 0 TOP VIEW 09 (Not to 320 0 10 Scale! 3t 0 011 300 0 12 29 0 0 13 28 0 014 27 0 015 260 016 25 0 0 17 24 0 018 23 0 019 22 0 020 210 CHAN21N CHAN3 IN -V. SAMPLE 3 SAMPLE 2 SIMULT READY CLK IN CONTROL EN'8 RST ViR RO DO (AID LSBI Yoo Function Channel 0 analoginput. Channell analoginput. Channel 2analoginput. Channel 3 analoginput. TestPoint(noconnect). Inputand (opendrain)outputused toenablecontrollerexternallyorthrough jA-Pinterface. Output that,insimultaneousmode, indicatesallchannelshave been successfullyconverted and deviceisreadytosample. Inputthatwhen LOW setscontrollertosimultaneousmode which keepsS/Hs inholdmode until allchannelshave been converted. Analog signalground. - SV referenceoutput. Analog power supplies. Analog power ground. ExternalclockinputtotheA/D converterand channelcontroller. Channel 0 StH controlinput. Channell StH controlinput. Channell sm controlinput. Channe13 S/H controlinput. Open draininterruptrequest.User programmable tobecome activeon anyofthefollowing conditions: One AID ConversionResultAvailable; FIFO HalfFullorFull; AID ConversionResultsOver range. Chip selectinput. Address bitzero.Selectsdatapathfrom FIFO/latch(low)orfrom/toStatus/Controlregister(high). Bidirectional3-statedatalines.D 11isND converterMSB when DO-D 13areoUtputs.D7 isStatus/ ControlregisterMSB. D 12and D 13carrychannelID number. Read controlinput(DO-D 13). Writecontrolinput(DO-D7). Reset.Inresetstate,FIFO istransparent& overrangedetectorisdisabled. Digitalpower supply. -7- PIN DESCRIPTIONS Pin Mnemonic

2 CHAN 0 IN

1 CHAN IIN

4() CHAN 21N

39 CHAN 3 IN

32 CONTROLENB

34 READY

8 ASIG GND

7 REF OUT

3,38 +Vs, -Vs

9 APWR GND

33 CLKIN

4 SAMPLE 0

36 SAMPLE 2

37 SAMPLE 3

10 IRQ

5 HFIF

4 ORNG

Figure 13. Typical InterfaceCircuit(Simultaneous Mode) intotbe FIFO (ifthe FIFO isenabled). intothe FIFO (ifthe FIFO isenabled). overrangeinterruptcapability. LogicalOR of statusBits4 & 6. range condition.Reset by controlBit4.

5 ORUN

ANALOG DEVICES fAX-ON-DEMAND HOTLINE -Page 28 AD1334 SAMPLE-AND-HOLD AMPLIFIERS The four sample-and-holdamplifiersinternaltothe AD1334 combine precisionhigh speed amplifiersand switchestogether with lasertrinunedthin-filmresistorsto offera performanceand power efficientfrontend formultichannelapplications.Each sample-and-holdamplifierisdesignedtominimize the effectsof dc and ac errorsourcesin simultaneousas wellas independent samplingapplications. OperationalDescription The sample-and-holdamplifierarchitectUreisbased on an inte- gratorwhich resultsina relativelylow inputimpedance rorsourcesarespecifiedand controlledthrough the use of preci- sionamplifiers,low leakageswitchesand package-levellaser trimming of thin-filmresistors. Group delayisspecifiedand controlledthrough the use of trimmed thin-filmresistors,tight-tolerancehold capacitorsand high speed amplifiers.Aperture delayisspecifiedand controlled through the use of high speed CMOS logicand DMOS switches.The effectiveaperturedelay,which isthedelayseen by theuser,isthereforecontrolledfrom channelto channeland from devicetodevice.The effectiveaperturedelayisnegative because theheld valuecorrespondsto a valueof inputvoltage thatoccurredbeforethe amplifierwas put intohold mode. In applicationswhere endpoint(+FS and -FS) accuracyiscrit- ical,thesourceimpedance should be minimized becauseeach ohm willtypicallychange thegain of the sample-and-holdam- plifierby 0.04%. This should not be a problem inmost cases becausethe low impedance output of eithera programmable gainamplifieror antialiasingfilterwillbe connected toeach of the AD 1334'sanaloginputs. CHANNEL CONTROLLER The AD 1334 Channel ControllerenablestheAD1334 toappearas fourindependentchannelsof analoginputby generatingallof the timingnecessarytoensurethatthe sampled channel isdigi- tizedto 12-bitaccuracy.Upon receiptof a sample command, thecontrollerwillimmediatelyplacethe sample-and-holdampli- fierintohold mode and then prioritizeand scheduletheheld valueforND conversion.At the appropriatetime,the sampled inputisgatedthrough themultiplexerand, aftersettling,isdig- itizedby theNO converter.The sample-and-holdamplifieristhen returnedtosample mode so thatitcan acquirethe next sample. OperationalDescription Timing isinitiatedon the risingedge of SAMPLE 0-3 control inputs.To minimize the effectsof digitalfeedthroughfrom the controlinputs,itisrecommended thatthe fallingedge occur beforesample-and-holdacquisition(sample-and-holdshave a maximum 7.5 j.J.Sacquisitiontime)but afterthe ND conversion iscomplete.Referto Figures15 and 16. CONTROL ENB functionsasan "on/off'switchforthecontroller and isboth an inputand an open drainoutput.The controller can thereforebe activatedeitherthrough themicroprocessor interface(viacontrolregisterBit7)or externallyby an open draindriver(suchas the 74HCO3). The controllercan alsobe permanentlyenabled by grounding CONTROL ENB. The tim- ing forenablingand disablingthe controlleras describedabove isshown in Figure 14.Controlleroperationisdescribedin greaterdetailinthe applicationnote "Using MultipleAD1334s in Many-Channel Synchronous Sampling Applications." REV. A RST ~f too- 17 -18 CP t .~. RESET PHASE .. . READY Figure 14a. Timing Diagram for Resetting Controller (CONTROL ENS = 0) CONTROL ENB ~. " .IDIJ READY .--17 -18 CP t I~, ' 0,---- RESET PHASE +j ioO-0.5 - 1.5CP I Figure14b. Timing Diagram forDisablingand Enabling ControllerUsing CONTROL ENS (RST = 1) The channelcontrolleralsoadds 2 bits(D12 and DB) of data toeach ND conversionresultforchannelidentification.Table I summarizes thisrelationship. DB I AID Conversion ResultsFrom Channel 0 I D12 I TableJ. Two timingmodes areavailableforsamplingand converting each or allof the analoginpms. (Note - The timingdiagrams shown referto Channels "A,B,C,D" ratherthan "0,1,2,3."This isdone becauseeach channel iscompletelyindependentof the otherthreechannelsand, in fact,Channel A can be any of Channels 0, 1,2 or 3,Channel B can be any of the remaining channels,etc.) Simultaneous Mode Simultaneousmode isselectedby connectingthe SlMUL T pin tologiclow. This mode should be used when any 2, 3 or all4 channelsaretobe sampled simultaneously(i.e.,atthesame in- stantin time).This mode keeps the sample-and-holdamplifiers on the sampled channelsin hold mode untilallthe sampled in- puts have been digitizedand willnormallyresultin better channel-to-channelisolationrelativeto independentmode. The timingdiagram forthismode isshown in Figure 15.Note that IRQ becomes activeon the completionof everyND conversion sincethe FIFO isnot beingused in thisexample. Prioritizinglogicinternalto the channel controllercan be used to ensurethatthe channelsareconvertedin a predetermined sequence.Synchronizingthe sample controlsignal(risingedge of SAMPLE 0-3)to eitherthe risingor fallingedge of theclock willresultin Channel 0 beingconvertedbeforeChannel 1, Channel I beforeChannel 2,and Channel 2 beforeChannel 3. An obviousadvantageto thisisthatthe usercan choose to ig- nore data Bits12 and 13 (D12 and DB) which carrythechan- nelidentification. -9- OBSOLETE

2 CHANNELS

3 CHANNELS

Figure 15. Timing Simultaneous Sampling (SIMUL T = Low, FIFO Not Used)

1 CHANNEL

Figure 16. Timing for Independent Sampling (SIMUL T = High, FIFO Not Used)

ANALOG DEVICES fAX-ON-DEMAND HOTLINE - Page 31 AD1334 Ifthe FIFO isused,the fallingedge of'the.READY signal,can be used as an interruptsignalto notifya processorthatthe I,2, 3 or 4 channelshave been successfullyconvertedand have been shiftedintothe FIFO. Allconversionresultscan be read from the FIFO with the exceptionof the lastone, which must fall through tothe output (fall-throughtime istypically400 ns). READY can alsobe used as a signalto the devicegenerating the sample command thatthe previousgroup of samples have been convertedand thatthe next group of samples arebeing acquired. The applicationnote "Simultaneousand Independent Sampling of Analog Signalswith the AD 1334" describesthisoperating mode ingreaterdetail. Independent~ode Independent mode isselectedby connectingthe SIMUL T pin to logichigh.This mode should be used when any number of channelsaresampled independently.In contrasttosimultaneous mode, thismode returnsthe sample-and-holdamplifieron the sampled channelto sample mode when the channelinpUthas been digitized.This mode allowsthe AD1334 to emulateup to fourindependent.samplingAiD converters,each of which can accommodate differentsample ratesand hence differentsignal bandwidths.The timingdiagram forthismode isshown in Fig- ure 16.Note thatIRQ becomes activeon the completionof ev- ery AiD conversionsincethe FIFO isnor being used. The READY signalhas no implicitdefinitionin thismode, otherthan the fallingedge indicatingthatthe controllerhas no conversionspending. The applicationnote "Simultaneousand Independent Sampling of Analog Signalswith the ADB34" describesthisoperating mode ingreaterdetail. AID CONVERTER The analoginputvoltagerangegoes from -5 V to +5 V and thedigitaloUtpUt coding isOffsetBinary (seeTable II).Twos complement coding can be obtainedby invertingthe MSB (DB). Center of Code Voltage (V) -5.000000 -0.002441 0.000000 +4.997559 Output Code 000 .. .000 011...111 100 . . .000 111...111 Table II.ND Conversion Relationship OperationalDescription Analog signalinformationisconvertedto a 12-bitdigitalword by sampling thewaveform and digitizingitusingthe successive- approximationconversiontechnique.Sincethe clockdoes not definetheamount of time between samples,itneed not be crys- talcontrolled.Best performancewillbe obtainedby operating theclockatthe maximum 2.5 MHz clockfrequency. HIGH SPEED DIGITAL INTERF;\\CE The AD1334 completesthe solutionforA/D conversionin DSP applicationsby providingthe system'sdesignera direct,high speed paralleldigitalinterface.The prime featureof thisinter- facearchitectureisthatitoperatescompletelyasynchronously from theAID converterand thereforeallowstheAD 1334 toap- pearas "memory" toa microprocessor. The combinationoffullyasynchronousoperationwith respectto theAiD conversionprocessand fastdataaccesstime allowsthe ADB34 user toupgrade tofasterversions,or even different vendors,of DSP hardware without having toadd synchroniza- tionor wait statelogic.In addition,by virtueof hybridcircuit technology,theuser isnot requiredto add externalcircuitryto preventdigitalfeedthrough intothe analogsection. The ADB34 data transferisaccomplishedby employing an in- terruptdrivenarchitectUre.Interruptscan be programmed by themicroprocessortobe generatedwhen the FIFO isfull(32 conversionresults),half-full(16 conversionresults)or afterev- ery conversion(FIFO isbypassed).The AD1334 digitalinter- facealsoincludesan overrangedetectcircuit,which can generatean interruptifthe sampled analoginputsignalexceeds positiveor negativefullscale,to alertthe system thata conver- sionresulthas been generatedthatwillresultina nonlinearity in thesubsequentsignalprocessing. OperationalDescription The AD1334 can interfacedirectlyto a microprocessorviastan- dard data (DO-DB), address(AO) and controllinesread (RD, WR, CS, IRQ and RST). Data Transfer The data linesDO-DB are bidirectionalI/O thatareTTL com- patibleand have 4mA drivecapability.The data linesareused totransfercontrolinformationinto,and AiD conversionresults with statUsinformationand channel identificationout of the AD1334. Address lineAO isan inputthatisused to selectas the data path eitherAiD conversionresultswith channelID (AO=O) or the Control/StatUsRegisters(AO= 1)and would typicallybe the leastsignificantaddressbitin the system ifthe AD 1334 is "mapped" toadjacentmemory locations.Chip Select(CS) is used todefinea unique locationinmemory fortheAD 1334 and should be formed by decoding the upper addressbits.Read (RD) and Write (WR) definethe type ofdata transfer. Figures 17-22 illustratehow the AD1334 interfacesroa number of popularsinglechip digitalsignalprocessors. Interrupts InterruptRequest (IRQ) isan open drainoutput thatcan be used to interrupttheprocessoron any ofthe conditionspro- grammed in the controlregister.READY can be used in simul- taneousapplicationsas an alternativeprocessorinterruptsignal asdescribedabove.In eithercase,the processorshouldbe pro- grammed tointerrupton the fallingedge of itsInterruptRe- questinpuI. FIFO The AD1334 containsa high speed 32-word asynchronousfall- through FIFO which may be enabledunder user controlwhen databufferingisrequired.The FIFO may be programmed to produce interruptson eitherthe half-fullor fullconditionas wellas on certainerrors.Itsboundary conditionbehaviorisde- signedto minimize the possibilityof lostdata.This behavioris describedindetailin the applicationnote "FIFO Operationand Boundary Conditionsin the AD1332 and AD1334." -12- REV. A OBSOLETE

ANALOG DEVICES fAX-ON-DEHAND HOTLINE - Page 35 AD1334 Power Supply Decoupling The power supplydecouplingcapacitorssupplytheinstantaneous currentto the AD1334 and alsoprovidesome high frequency filtering.The filteringaspectof the capacitorsshould not be counted on however, and the usershould make everyeffortto supply quiet,wellregulatedpower suppliestothe AD1334. Switchingmode power suppliesare not recommended forthe analogpower supplies::!:V s. Decoupling capacitorsshould be placedas dose to thedeviceas possibleto minimize inductancesin power supply traces.A 2.2~F (orgreater)solidtantalum capacitorinparallelwith a O.I~F ceramic capacitorshould be used fordecouplingeach + V s and - V s.A I.O~F (orgreater)solidtantalumcapacitor should be used fordecouplingV DD- T{'ansmissionLine Effects The digitalinterfacehas IOK ECL speed and with ISpF loading exhibitsa typicaledge rareof lAns- High speed CMOS systems thatincorporatethe AD1334 must use carefulPCB layoutand impedance matching techniquesto reduce crosstalkand voltage reflections. Crosstalk The fastedge rateswith largevoltageswings ofCMOS systems can resultincapacitiveand inductivecoupling(crosstalk)between adjacentPCB signaltracesand may compromise signalintegrity and reduce noisemargins.The effectcan be most severeon data linesthatarenear "docked" controllines,such as Read, Write and Chip Selectlines,when they actuallychange their logicstateas a resultof crosstalk. To reducecrosstalk,the PCB layoUtshould minimize long paralleltraces.Ifthiscan not be avoided,clocklinesshouldbe shieldedfrom data and addresslinesby running ground traces along sidethem. Voltage Reflections The grossimpedance mismatch between high impedance CMOS inputsand low impedance CMOS outpUtsinvitesunwanted voltagereflectionsand "ringing"thatcan alsocompromise signalintegrityand reduce noisemargins.This levelofmismatch causesa nearlyequaland oppositenegativepulseto be reflected back from the load tothe sourcewhen the round tripdelayof the lineexceedsthe riseor falltime of the drivingsignal.For a typicallinedelayof O.OSSns/cm with a IAns edge rate,this translatestoonly Bcm (5 inches)fortheADB34. Providedthe signallinesareover a ground plane,thismay neverbe a problem sincethe added capacitancewilJreduce theedge rate. The effectwillbe most severeon "clock" linesin synchronous systems such asRead, Write and Chip Selectlines.For example, should the AD1334 Read controlinput(RD) be double clocked as a resultof a reflectionwhile in a read cycle,in most casesthe digitalinterfacechip willbe fastenough to respond.Ifthe FIFO isbeing read from, a second shiftout willoccurand AID conversionresultswillbe lost. SinceCMOS outpUt stagesarenot capableofdeliveringenough currentto the loadwhen a transmissionline(PCB trace)is terminatedin itscharacteristicimpedance, seriesdamping is recommended when reflectionsmust be reduced or eliminated. Here, a smallresistor(typicallyIOn to 7SH) isinsertedin series with the transmissionlineas closeto the sourceas possible.The goalistomatch theseriesresistanceplusdriveroUtpUtimpedance to the transmissionlineimpedance. This willkeep thewave that isreflectedback from the load tosourcefrom reflectingback to the load. 'I'"NNN U The primary disadvantageof seriesterminationisthatdue to the voltagedividerformed by the sourceresistanceand line impedance, thevoltageatthe inputtothelineismidway between logiclevelsduring the two-way propagationdelaytime.This means thatalthoughany number ofdeviceinputsmay be attached atthe loadend, otherdeviceinpUtscannot be distributedalong the transmissionline. REFERENCES Cypress SemkoMlU:tor, CMOS Dali.lBook, Cypress Semiconductor, 1987. OUTLINE DIMENSIONS Dimensions shown in inches and (nun) 4O-Pin Bottom Brazed Ceramic DIP (DH-40A) PIN 1 SEATING PLANE MIN G.OD5 (O.13) MIN 0023/0581 0.100 (2.54) 0.014 (0.36) asc 0.05011.27) 0.030(0.76) 0.035 10.8l) lli " 0 15(0.38) H 0.180 P (4.57) MIN 0.098 (2.49) MAX ~.01510.38) 1 +~.OO8 (0.20) 1-:.620115.7ll 0.580 (14.73) vi ::) CI UJ r-;z~(l. -16- REV. A 2140 G.225 (5.72) MAX OBSOLETE