AD1316

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ANALOG Complete, High Speed DEVICES 16-Bit A/D Converters FEATURES | tion applications requiring moderate speed and high accuracy or Complete 16-Bit Converters with Reference stability over commercial (0°C to +70°C) temperature ranges and Clock — (for extended temperature ranges, the pin compatible AD1378 £0.003% Maximum Nonlinearity is recommended.) Typical applications include medical and ana- No Missing Codes to 14 Bits over Temperature lytic instrumentation, precision measurement for industrial Fast Conversion robotics, automatic test equipment (ATE), and multichannel 17 ps to 16 Bit (AD1376) data acquisition systems, servo control systems, or anywhere 10 ps to 16 Bits (AD1377) wide dynamic range is required. A proprietary monolithic DAC Short Cycle Capability and laser-trimmed thin-film resistors guarantee a maximum non- Adjustable Clock Rate linearity of +0.003% (1/2 LSB,,.) The converters may be short Parallel and Serial Outputs cycled to achieve faster conversion times—15 us to 14-bits for Low Power: 645 mW Typical {AD1376) the AD1376, or 8 ps to 14 bits for the AD1377. 585 mW Typical (AD1377) Industry Standard Pin Out PRODUCT HIGHLIGHTS 1. The AD1376 and AD1377 provides 16-bit resolution with a PRODUCT DESCRIPTION maximum linearity error of +0.003% (1/2 LSB,,) at +25°C. The AD1376 and AD1377 are high resolution, 16-bit analog-to- 2. AD1376 conversion time is 14 us (typical) short cycled to 14 digital converters with internal reference, clock and laser- bits, and 16 ys to 16 bits, trimmed thin-film applications resistors. They are packaged in a ; Compact 32-pin, ceramic seam sealed (hermetic) dual-in-line 3. AD1377 conversion time is 8 ws (typical) short cycled to 14 packages (DIP). Thin-film scaling resistors provide bipolar input bits, and 9 ps to 16 bits. ranges of +2.5 V, +5 V, +10 V and unipolar input ranges of 0 4. Two binary codes are available on the digital output. They to +5 V, 0 to +10 V, and 0 to +20 V. are CSB (Complementary Straight Binary) for unipolar input Digital output data is provided in parallel and serial form with voltage ranges and COB (Complementary Offset Binary) for corresponding clock and siatus outputs. All digital inputs and bipolar input ranges. Complementary Twos Complement outputs are TTL compatible. (CTC) coding may be obtained by inverting Pin 1 (MSB). 5. The AD1376 and AD1377 include internal reference and APPLICATIONS clock, with external clock rate adjust pin, and serial and par- ‘The AD1376 and AD1377 are excellent for use in high resolu- allel digital outputs. FUNCTIONAL BLOCK DIAGRAM mse) errs 1 [7 } [a2] sont cvoue a2 (2H [i] convert commano we fe ADIa76/AD1377 Re] a) aversumry, ara [el [3] can aovust ara] tH |B £1876 SPL Ve weft Hoth s Fr} comneron L! HoH § [ {loa on 7 [a] Hoe Fa] emotan orrser wh TS 8 || et ws CY i Prete ao an oft [ SH +4 Fis) cux rare crm, on 1 fat TTT [iz}anasoa common sur 2 [a] [i] - tev ae SUPPLY Vx use ror 13 as) arr 13 [13} FZ] crock our connunneruia — | <tc ons [is] Fis] sravus aa 16 [76] {77} senia. our REV. B Information furnished by Anslog Devices is believed to be sccurate and which may result from its use-No license is granted by implication or Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-8577 otherwise under any patent or patent rights of Analog Devices. Telex: 924491 ‘Cable: ANALOG NORWOODMASS

AD 1 376/AD1 377-SPECIFI CATIONS (typical at T, = +25°C, V, = +15, +5 V unless otherwise noted) Model AD1376JD/AD1377JD AD1376KD/AD1377KD Units RESOLUTION 16 (max) * Bits ANALOG INPUTS Voltage Ranges Bipolar 22.5, 25, =10 * Volts Unipolar | Oto +5, 0 to +10, 0 to +20 * Volts Impedance (Direct Input) Oto +10 V, +5.0V 3.75 * ka Oto +20V, +10V 7.50 * ko DIGITAL INPUTS" | Convert Command Positive Pulse 50 ns Wide (min) Trailing Edge Initiates Conversion Logic Loading 1 * LS TTL Load TRANSFER CHARACTERISTICS? ACCURACY Gain Error =0,05? (+0.2 max) * % Offset Error Unipolar =0.05 (+0.1 max) * % of FSR* Bipolar £0.05? (+0.2 max) * % of FSR Linearity Error (max) =0.006 =0.003 % of FSR Inherent Quantization Error =12 * LSB Differential Linearity Error =0,003 * % of FSR POWER SUPPLY SENSITIVITY £15 V de (+0.75 V) 0.0015 % of FSR% AVs +5 V de (+0.25 V) 0.001 % of FSR% AVs CONVERSION TIME® 12 Bits (AD1376) 11.5 (13 max) bs 14 Bits (AD1376) 13.5 (15 max) us 16 Bits (AD1376) 15.5 (17 max) bs 14 Bits (AD1377) 8.75 max bs

16 Bits (AD1377) 10 max bs

Rated Voltage, Analog +15, +0.5 (max) * . Vide Rated Voltage, Digital +5, 0.25 (m,ax) * Vide AD1376 Power Consumption 645 (850 max) * mW +15 V Supply Drain +16 * mA ~15 V Supply Drain 21 * mA +5 V Supply Drain +18 * mA AD1377 Power Consumption 600 (800 max) * mW +15 V Supply Drain +10 * mA =15 V Supply Drain ~23 * mA +5 V Supply Drain +18 * mA WARM-UP TIME T minute * minutes DRIFT® Gain £15 (max) +5 (+15 max) ppm/°C Offset Unipolar +2 (+4 max) | #2 (=4 max) ppm of FSR/°C Bipolar 10 (max) +3 (+10 max) ppm of FSR/°C Linearity £2 (£3 max) +0.3 (+2 max) ppm of FSR/°C Guaranteed No Missing Code Temperature Range 0 to 70 (13 Bits) 0 to 70 (14 Bits) °C DIGITAL OUTPUT’ (All Codes Complementary) Parallel & Serial Output Codes’ Unipolar CSB * Bipolar CoB, CTC* * Output Drive 5 * LSTTL Loads Status Logic “1” During Conversion Status Output Drive 5 (max) * LSTTL Loads Internal Clock? Clock Output Drive 5 (max) * LSTTL Loads Frequency 1040/1750 * kHz -2- REV. B

*Tested on +10 V and 0 to +10 V ranges. “Guaranteed but not 100% production tested. “Conversion time may be shortened with “Short Cycle” set for lower resolution. 7CSB-Complementary Straight Binary. COB-Complementary Offset Binary CTC-Complementary Twos Complement. SCTC coding obtained by inverting MSB (Pin 1). “With Pin 23, clock rate controls tied to digital ground. *Specifications same as AD1376JD/AD1377JD. Specifications subject to change without notice. Figure 1. Linearity Error vs. Temperature Figure 3. Gain Drift Error vs. Temperature

If no external trim adjustment is desired, Pin 27 (offset adj) and next conversion. vey positive-going clock edge. **Figure 4. Gain Adjustment Circuit (0.2% FSR) ons - *t —_ rH - -** tempco contributes a worst-case offset tempco of 32 LSB,, x ona our == RASS TSU RLS TNT BUR UROL.

1860 Tame @) AD1376/ Both parallel and serial data from TTL storage registers is in

100k AD1377 negative true form (Logic “1” = 0 V and Logic “0” = 2.4 V). Figure 5. Offset Adjustment Circuit (0.3% FSR) allel data becomes valid at least 20 ns before the STATUS flag offset tempco if metal film resistors (tempco <100 ppmv°C) are Figure 8). Figure 6. Low Tempco Zero Adjustment Circuit

ranges. Serial output is by bit (MSB first, LSB last) in NRZ the conversion period. Figure 9. Clock High to Serial Out Valid The ADC (ADC) inputs should be scaled as close to the maxi- cycle. The first negative edge shifts an invalid bit into the regis- signal as shown in Table Il. See Figure 10 for circuit details. ter, which is shifted out on the last negative-going clock edge.

Code Under Test Low Side Transition Values _ MSB -LSB_| Range +10V 45V £25V |OVto+10V (OVt0+5V 000... 000* + Full Scale | +10 V +5V +25V | +10V +5V -3/2 LSB | -3/2 LSB | -3/2 LSB | -3/2 LSB -3/2 LSB ou... Mid Scale | 0-1/2 LSB | 0-1/2 LSB | 0-1/2 LSB | +5 V-1/2 LSB | +2.5 V-1/2 LSB M1... 10 | = Full Scale | -10 V -5V -25V | 0V ov _ +1/2 LSB | +1/2 LSB | +1/2 LSB | + 1/2 LSB +1/2 LSB *Voltages given are the nominal value for transition to the code specified. Note: For LSB value for range and resolution used, see Table IV. Table Ill.Transition Values vs. Calibration Codes Analog Input Voltage Range | +10V | +5V +25V | OVw+10V | OVIOt+SV Code COB* COB* COB* One Least FSR | 20V 10V sv 10V Tsv Significant P e oa ae P e Bit (LSB) n=10| 19,53mV | 9.77mV_ | 4.88 mV 9.77 mV 4.88 mV NOTES *COB = Complementary Offset Binary. CTC = Complementary Twos Complement — achieved by using an inverter to complement the most significant bit to product (MSB). *CSB = Complementary Straight Binary . Table IV. Input Voltage Range and LSB Values 10v SPAN Zero is now calibrated. Set analog input to +FSR — 2 LSB = 7 Oz + 9.99878 V. Adjust Gain for 0000000000001 digital output L-@— aw code; full scale (Gain) is now calibrated. Half scale calibration 20V SPAN Ba check: set analog input to +5.00000 V; digital output code comp in @) > should be OMI. TOSAR FROM D/A CONVERTER = ase COMPARATOR ow CH BIPOLAR AAV rose frome ite . ttl Pitti e v Figure 10, Input Scaling Circuit a EP 3 ; WED % FLY CALIBRATION ®) (14-Bit Resolution Examples) O—-O-@-O OW) External ZERO ADJ and GAIN ADJ potentiometers, connected a Vw drown Otro, as shown in Figures 4 and 5, are used for device calibration. To & Beal Y prevent interaction of these two adjustments, Zero is always re ANALOG (9) AKO DIOHTAL#) GNOS ie adjusted first and then Gain, Zero is adjusted with the analog Anes fa nena ano man input near the most negative end of the analog range (0 for uni- polar and —FS for bipolar input ranges). Gain is adjusted with the analog input near the most positive end of the analog range. = Figure 11. Analog and Power Connections for Unipolar

0 V to + 10 V Range: Set analog input to + 1 LSB,, = OV to +10 V Input Range

0.00061 V. Adjust Zero for digital output = 1111111111110. 6 REV. B

for 0000000000001 digital output (complementary offset binary) measurement errors. Figure 12. Analog and Power Connections for Bipolar oe cedure described above. By summing a small sine or triangular the AD386 to reenter track mode. Many data-acquisition components have two or more ground by the SHA, introducing nonlinearity. the system analog ground point and the ground pins of the we . .