AD1315

AD1315 HANAMICRON | Alldatasheet

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REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD1315 Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 High Speed Active Load with Inhibit Mode FUNCTIONAL BLOCK DIAGRAM PRODUCT DESCRIPTION The AD1315 is a complete, high speed, current switching load designed for use in linear, digital or mixed signal test systems. By combining a high speed monolithic process with a unique surface mount package, this product attains superb electrical performance while preserving optimum packaging densities in an ultrasmall 16-lead, hermetically sealed gull wing package. Featuring current programmability of up to +50 mA, the AD1315 is designed to force the device under test to source or sink the programmed I OHPROG and IOLPROG currents. The IOH and IOL currents are determined by applying a corresponding voltage (5 V = 50 mA) to the I OH and I OL pins. The voltage- to-current conversion is performed within the AD1315 thus allowing the current levels to be set by a standard voltage out digital-to-analog converter. The AD1315’s transition from IOH to IOL occurs when the output voltage of the device under test slews above or below the programmed threshold, or commutation voltage. The commuta- tion voltage is programmable from 2 V to +7 V, covering the large spectrum of logic devices while able to support the large current specifications (48 mA) typically associated with line drivers. To test I/O devices, the active load can be switched into a high impedance state (Inhibit mode) electrically removing the active load from the path through the Inhibit mode feature. The active load leakage current in Inhibit is typically 20 nA. The Inhibit input circuitry is implemented utilizing high speed differential inputs with a common-mode voltage range of 7 volts and a maximum differential voltage of 4 volts. This allows for the direct interface to the precision of differential ECL timing or the simplicity of switching the Active Load from a single ended TTL or CMOS logic source. With switching speeds from IOH or Io~ into Inhibit of less than 1.5 ns, the AD1315 can be electrically removed from the signal path “on-the-fly.” The AD1315 is available in a 16-lead, hermetically sealed gull wing package and is specified to operate over the ambient com- mercial temperature range from 0 °C to +70°C.

FEATURES

+50 mA Voltage Programmable Current Range 1.5 ns Propagation Delay Inhibit Mode Function High Speed Differential Inputs for Maximum Flexibility Hermetically Sealed Small Gull Wing Package Compatible with AD1321, AD1324 Pin Drivers

APPLICATIONS

–2– REV. A AD1315–SPECIFICATIONS (All measurements made in free air at +25 8C. +VS = +10 V, –V S = –5.2 V, unless otherwise noted.) AD1315KZ Parameter Min Typ Max Units Comments DIFFERENTIAL INPUT CHARACTERISTICS INH to INH Input Voltage, Any One Input –3.0 4.0 Volts Differential Input Range 0.4 ECL 4.0 Volts Bias Current –2.0 1.0 2.0 mA Current Program Voltage Range I OH, 0 mA to +50 mA (Sink) 1 0 +5.0 Volts IOL, 0 mA to –50 mA (Source)1 0 +5.0 Volts Input Resistance 50 k Ω IOHRTN, IOCRTN Range2 –2.0 +7.0 Volts VCOM, VDUT Range –2.0 +7.0 Volts IOH, 0 mA to +50 mA 0.5 +7.0 Volts V DUT – VCOM >1 V IOL, 0 mA to –50 mA –2.0 +4.0 Volts V COM – VDUT >1 V OUTPUT CHARACTERISTICS 3 Active (Sink/Source) Mode Transfer Function 10 mA/V See Figure 1 Accuracy See Figure 1 Linearity Error –0.12 +0.12 % FSR Gain Error –2.0 +2.0 % FSR Offset Error –1.0 +1.0 mA Output Current TC 10 µA/°C Inhibit Mode Output Capacitance 3.0 pF Inhibit Leakage –200 20 200 nA DYNAMIC PERFORMANCE3 Propagation Delay See Figure 2 ± IMAX to INHIBIT (tPD1)4 0.5 1.5 ns INHIBIT to ± IMAX (tPD2)4 1.5 3.0 ns POWER SUPPLIES –VS to +VS Difference 15.2 15.4 Volts Supply Range Positive Supply +9.5 +10 +10.5 Volts Negative Supply –5.45 –5.2 –4.95 Volts Current Positive Supply 5 +705 +85 +100 mA Negative Supply5 –1005 –85 –70 mA Power Dissipation6 1.3 1.54 PSRR7 0.05 %/% NOTES 1IOHPROG/IOLPROG voltage range may be extended to –100 mV due to a possible 1 mA offset current. 2IOHRTN/IOLRTN should be connected to V COM to minimize power dissipation. 3VDUT = –2 V to +7 V, C TOTAL = 10 pF, R DUT = 10 Ω . For inhibit leakage tests, V DUT = 0 V to +5.9 V, I OH = –4 mA, IOL = +4 mA, T CASE = +36°C. 4Measured from the ECL crossing to the 10% change in the output current. 5IPROGRAM = ± 50 mA. 6Maximum power dissipation with +V S = +10 V, –VS = 5.2 V, I PROGRAM 50 mA, V COM = VDUT = 0 V. 7For a 1% change in +V S or VS, the output current may change a maximum of 0.05% of Full Scale Range (FSR). Specifications subject to change without notice.

–3–REV. A ABSOLUTE MAXIMUM RATINGS 1 Power Supply Voltage Inputs Pin No. Symbol Function 1I OLRTN Logic Low Current Return 2V COM Communication Voltage 3V DUT Load/Dot Connection 4– V S Negative Supply 5I OHRTN Logic High Current Return 6I OLPROG Logic Low Current Program Voltage

7 LID Lid Connection (Internal)

8 GND Ground

9I OHPROG Logic High Current Program Voltage

10 N/C No Connection

11 N/C No Connection

12 N/C No Connection

14 INH Inhibit

15 INH Inhibit

16 N/C No Connection

1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2To ensure lead coplanarity ( ± 0.002 inches) and solderability, handling with bare hands should be avoided and the device should be stored in an environment at 24°C, ± 5°C (75°F, ± 10°F) with relative humidity not to exceed 65%. CONNECTION DIAGRAM SUGGESTED PAD LOCATION Dimensions shown in inches and (mm). ORDERING GUIDE Temperature Package Package Model Range Description Option* AD1315KZ 0 to +70 °C 16-Lead Gull Wing Z-16B *Z = Leaded Chip Carrier (Ceramic).

–7–REV. A The AD1315 has been optimized to function as an active load in an ATE test system. Figure 14 shows a block diagram illus- trating the electronics behind a single pin of a high speed digital functional test system with the ability to test I/O pins on logic devices. The AD1315 active load, AD1321 or AD1324 pin driver, AD1317 high speed dual comparator and the AD664 quad 12-bit voltage DAC would comprise the pin electronic portion of the test system. Such a system could operate at

100 MHz with the AD1321 (200 MHz with the AD1324) in a

data mode or 50 MHz (100 MHz) in the I/O mode. The V COM input sets the commutation voltage of the active load. With DUT output voltage above V COM, the load will sink cur- rent (IOH). With DUT output voltage below V COM, the load will source current (IOL). Like the IOH and IOL return lines, the V COM must be able to sink or source 50 mA, therefore a standard op amp will not suffice. An op amp with an external complemen- tary output stage or a high power op amp such as the AD842 will work well here. A typical application is shown in Figure 15. LAYOUT CONSIDERATIONS IOHRTN and IOLRTN may be connected to any potential between –2 V and +7 V. These return points must be able to source or sink 50 mA, since the I OH and IOL programmed currents are diverted here in the inhibit mode. The RTNs may be connected to a suitable GND. However, to keep transient ground currents to a minimum, they are typically tied to the V COM programming voltage point. Figure 14. High Speed Digital Test System Block Diagram Figure 15. Suggested I OHRTN, IOLRTN, VCOM Hookup

C1337a–1–5/97PRINTED IN U.S.A. Figure 16. AD1315EB Evaluation Board Circuit in order to minimize variations due to test setups. Dimensions shown in inches and (mm).