AD12400

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Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent ri ghts of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.

FEATURES

400 MSPS sample rate

SNR of 63 dBFS @128 MHz SFDR of 70 dBFS @128 MHz VSWR of 1:1.5 Wideband ac-coupled input signal conditioning Enhanced spurious-free dynamic range Single-ended or differential encode signal LVDS output levels Twos complement output data

APPLICATIONS

Communications test equipment Radar and satellite subsystems Phased array antennas—digital beam forming Multichannel, multimode receivers Secure communications Wireless and wired broadband communications Wideband carrier frequency systems GENERAL DESCRIPTION The AD12400 is a 12-bit analog-to-digital converter with a transformer-coupled analog input and digital post processing for enhanced SFDR. The product operates at a 400 MSPS conversion rate with outstanding dynamic performance in wideband carrier systems. The AD12400 requires 3.8 V analog, 3.3 V digital, and 1.5 V digital supplies and provides a flexible encode signal that can be differential or single-ended. No external reference is required. The AD12400 package style is an enclosed 2.9" × 2.6" × 0.6" module. Performance is rated over a 0°C to 60°C case temperature range. FUNCTIONAL BLOCK DIAGRAM 03735-0-001 ADC A DATA READY A DATA READY B DA0–DA11 DB0–DB11 CLK DISTRIBUTION AD12400 POST- PROCESSING ADC B AIN CLOCK DISTRIBUTION DIVIDE BY 2 ENC ENC Figure 1. PRODUCT HIGHLIGHTS 1. Guaranteed sample rate of 400 MSPS. 2. Input signal conditioning with optimized dynamic performance to 180 MHz. 3. Additional performance options available—contact factory. 4. Proprietary Advanced Filter Bank™ digital post processing from VCorp® Technologies, Inc.

Rev. 0 | Page 2 of 28 TABLE OF CONTENTS

REVISION HISTORY

Revision 0: Initial Version

1 Tested using input frequency of 70 MHz. See Figure 17 for I(VD) variation vs. input frequency. 2 All ac specifications tested by driving ENC single-ended. 3 Refer to Table 5 for logic convention on all logic inputs. 4 Digital Output Logic Levels: DR V = 3.3 V, CLOAD = 8 pF. 3.3 V LVDS R1 = 100 Ω. Specifications subject to change without notice.

180 MHz Full I 57 61 57 61 dBFS

128 MHz Full I 67 76 67 76 dBFS

180 MHz Full I 62 71 62 71 dBFS

128 MHz Full I 56 70 62 70 dBFS

180 MHz Full I 54 70 62 70 dBFS

Rev. 0 | Page 5 of 28 AD12400JWS AD12400KWS Parameter Case Temp Test Level Min Typ Max Min Typ Max Unit DR Propagation Delay (tEDR) 60°C V 3.88 3.88 ns Data to DR Skew (tEDR − tPD) 60°C V 2.68 2.68 ns Pipeline Latency7 Full IV 40 40 Cycles Aperture Delay (tA) 60°C V 1.6 1.6 ns Aperture Uncertainty (Jitter, tJ) 60°C V 0.4 0.4 ps rms 1 All ac specifications tested with a single-ended 2.0 V p-p ENCODE. 2 Dynamic performance guaranteed for analog input frequencies of 10 MHz to 180 MHz. 3 Not including image spur. 4 Image spur will be at fs/2–AIN and the offset spur will be at fs/2. 5 F1 = 70 MHz, F2 = 73 MHz. 6 Parts are tested with 400 MSPS encode. Device can be clocked at lower encode rates, but specifications are not guaranteed. Specifications will be guaranteed by design for encode 400 MSPS ± 1%. 7Pipeline latency will be exactly 40 cycles. EXPLANATION OF TEST LEVELS I 100% production tested. II 100% production tested at 25°C and samp le tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by desi gn and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.

Rev. 0 | Page 6 of 28 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Value VA to AGND 5 V VC to DGND 4 V VD to DGND 1.65 V Analog Input Voltage 6 V (DC) Analog Input Power 18 dBm (AC) Encode Input Voltage 6 V (DC) Encode Input Power 12 dBm (AC) Logic Inputs and Outputs to DGND 5 V Storage Temperature Range, Ambient −65°C to +150°C Operating Temperature 0°C to 60°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Table 4. Output Coding (Twos Complement) Table 5. Option Pin List With Necessary Associated Circuitry Figure 2. Encode Equivalent Circuit *DATA LOST DUE TO ASSERTION OF LEAD/LAG. LATENCY OF 40 ENCODE CLOCK CYCLES BEFORE DATA VALID.

40 CLOCK CYCLES

1 IF A SINGLE-ENDED SINEWAVE IS USED FOR ENCODE, USE THE "ZERO CROSSING" POINT (AC-COUPLED) AS THE 50%

POINT AND APPLY THE SAME TIMING INFORMATION. NEXT VALID DRA AFTER LEAD/LAG IS RELEASED. Figure 3. Timing Diagram Figure 4. Highlighted Timing Diagram

*INTEGRAL GROUND PLANE CONNECTIONS. SECTION A = DGND, PINS 121–124. SECTION B = DGND, PINS 125–128. SECTION C = AGND, PINS 129–132. FOR MATING HALF, USE SAMTEC, INC. Figure 5. Pin Configuration

Table 6. Pin Function Descriptions 5 RESET LVTTL. 0 = Device Reset. Minimum Width = 200 ns. Device resumes operation after 600 ms maximum. 10 DRB Channel B Data Ready. Complement output. 12 DRB Channel B Data Ready. True output. 17 DB11− Channel B Data Bit 11. Complement output bit. 18 DB10− Channel B Data Bit 10. Complement output bit. 19 DB11+ Channel B Data Bit 11. True output bit. 20 DB10+ Channel B Data Bit 10. True output bit. 21 DB9− Channel B Data Bit 9. Complement output bit. 22 DB8− Channel B Data Bit 8. Complement output bit. 23 DB9+ Channel B Data Bit 9. True output bit. 24 DB8+ Channel B Data Bit 8. True output bit. 25 DB7− Channel B Data Bit 7. Complement output bit. 26 DB6− Channel B Data Bit 6. Complement output bit. 27 DB7+ Channel B Data Bit 7. True output bit. 28 DB6+ Channel B Data Bit 6. True output bit. 29 DB5− Channel B Data Bit 5. Complement output bit. 30 DB4− Channel B Data Bit 4. Complement output bit. 31 DB5+ Channel B Data Bit 5. True output bit. 32 DB4+ Channel B Data Bit 4. True output bit. 33 DB3− Channel B Data Bit 3. Complement output bit. 34 DB2− Channel B Data Bit 2. Complement output bit. 35 DB3+ Channel B Data Bit 3. True output bit. 36 DB2+ Channel B Data Bit 2. True output bit. 37 DB1− Channel B Data Bit 1. Complement output bit. 38 DB0− Channel B Data Bit 0. Co mplement output bit. DB0 is LSB. 39 DB1+ Channel B Data Bit 1. True output bit. 40 DB0+ Channel B Data Bit 0. True output bit. DB0 is LSB. 41−48 VD Digital Supply, +1.5 V. 53 DA11− Channel A Data Bit 11. Complement output bit. 54 DA10− Channel A Data Bit 10. Complement output bit. 55 DA11+ Channel A Data Bit 11. True output bit. 56 DA10+ Channel A Data Bit 10. True output bit. 57 DA9− Channel A Data Bit 9. Complement output bit. 58 DA8− Channel A Data Bit 8. Complement output bit. 59 DA9+ Channel A Data Bit 9. True output bit. 60 DA8+ Channel A Data Bit 8. True output bit. 61 DA7− Channel A Data Bit 7. Complement output bit. 62 DA6− Channel A Data Bit 6. Complement output bit. 63 DA7+ Channel A Data Bit 7. True output bit. 64 DA6+ Channel A Data Bit 6. True output bit. 65 DA5− Channel A Data Bit 5. Complement output bit. 66 DA4− Channel A Data Bit 4. Complement output bit. 67 DA5+ Channel A Data Bit 5. True output bit.

Rev. 0 | Page 10 of 28 Pin Number Mnemonic Function 68 DA4+ Channel A Data Bit 4. True output bit. 69 DA3− Channel A Data Bit 3. Complement output bit. 70 DA2− Channel A Data Bit 2. Complement output bit. 71 DA3+ Channel A Data Bit 3. True output bit. 72 DA2+ Channel A Data Bit 2. True output bit. 73 DA1− Channel A Data Bit 1. Complement output bit. 74 DA0− Channel A Data Bit 0. Co mplement output bit. DA0 is LSB. 75 DA1+ Channel A Data Bit 1. True output bit. 76 DA0+ Channel A Data Bit 0. True output bit. DA0 is LSB. 77 LEAD/LAG Typically DNC. See LEAD/LAG note on Page 17. 78 DRA Channel A Data Ready. Complement output. 80 DRA Channel A Data Ready. True output. 81−95, 109−112, 129−132* AGND Analog Ground. 113−120 VA Analog Supply, 3.8 V 121−128* DGND Digital Ground. *Internal Ground Plane Connections: Section A = DGND, Pins 121−124, Section B = DGND, Pins 125−128, Section C = AGND, Pins 129−132.

Rev. 0 | Page 11 of 28 DEFINITIONS OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point on the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Full-Scale Input Voltage Range This is the maximum peak-to-peak input signal magnitude that will result in a full-scale response, 0 dBFS on a single-tone input signal case. Any magnitude increase from this value will result in an over-range condition. Analog Input VSWR (50 Ω) The Voltage Standing Wave Ratio is a ratio of the transmitted and reflected signals. The VSWR can be related to input impedance using the following equations: Impedance Reference Impedance LoadActual Γ−= SZ LZ VSWR SZLZ SZLZ Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) Calculated from the measured SNR based on the equation 02.6 76.1 dBSNRENOB MEASURED −= Encode Pulsewidth/Duty Cycle Pulsewidth high is the minimum amount of time the ENCODE pulse should be left in Logic 1 state to achieve rated perform- ance; pulsewidth low is the minimum time the ENCODE pulse should be left in low state. See timing implications of changing t ENCH in the Application Notes, Encode Input section. At a specified clock rate of 400 MSPS, these specifications define an acceptable ENCODE duty cycle. Full-Scale Input Power Expressed in dBm. Computed using the following equation: () ⎟ = − − 001.0 log10 INPUT SCALErmsFULL SCALEFULL Z VPOWER Gain Error The difference between the measured and ideal full-scale input voltage range of the ADC. Harmonic Distortion, Second The ratio of the RMS signal amplitude to the RMS value of the second harmonic component, reported in dBFS. Harmonic Distortion, Third The ratio of the RMS signal amplitude to the RMS value of the third harmonic component, reported in dBFS. Distortion, Image Spur The ratio of the RMS signal amplitude to the RMS signal amplitude of the image spur, reported in dBFS. The image spur, a result of gain and phase errors between two time-interleaved conversion channels, is located at fs/2 – fAIN. Distortion, Offset Spur The ratio of the RMS signal amplitude to the RMS signal amplitude of the offset spur, reported in dBFS. The offset spur, a result of offset errors between two time-interleaved conversion channels, is located at fs/2. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. Minimum Conversion Rate The minimum ENCODE rate at which the image spur calibration will degrade no more than 1 dB (when image spur is 70 dB). Maximum Conversion Rate The maximum ENCODE rate at which the image spur calibration will degrade no more than 1 dB (when image spur is 70 dB). Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE (or zero crossing of a single-ended ENCODE). Total Noise Calculated as follows: ⎛ −− ××= 1010001.0 dBFSdBcdBm SIGNALSNRFS NOISE ZV where Z is the input impedance, FS is the full scale of the device for the frequency in question, SNR is the value of the particular input level, and SIGNAL is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise.

Rev. 0 | Page 12 of 28 Offset Error The DC offset imposed on the input signal by the ADC, reported in LSB (codes). Pipeline Latency The number of clock cycles that the output data will lag the corresponding clock cycle. Power Supply Rejection Ratio The ratio of power supply voltage change to the resulting ADC output voltage change. Signal-to-Noise-and-Distortion (SINAD) The ratio of the RMS signal amplitude (set 1 dB below full scale) to the RMS value of the sum of all other spectral components, including harmonics but excluding DC and image spur. Signal-to-Noise Ratio (SNR) The ratio of the RMS signal amplitude (set at 1 dB below full scale) to the RMS value of the sum of all other spectral components, excluding the first five harmonics and DC. Spurious-Free Dynamic Range (SFDR) The ratio of the RMS signal amplitude to the RMS value of the peak spurious spectral component, except the image spur. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered) or dBFS (always related back to converter full-scale). Two-Tone Intermodulation Distortion Rejection The ratio of the RMS value of either input tone to the RMS value of the worst third-order intermodulation product; reported in dBc. Two-Tone SFDR The ratio of the RMS value of either input tone to the RMS value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full-scale).

Rev. 0 | Page 17 of 28 While this product has been designed to provide good PSRR performance, systems designers need to be aware of the risks associated with switching power supplies and consider using linear regulators in their high speed ADC systems. Switching power supplies typically produce both conducted and radiated energy that result in common-/differential-mode EMI currents. Any system that requires 12-bit performance has very little room for errors associated with power supply EMI. For example, a system goal of 74 dB dynamic range performance on the AD12400 will require noise currents that are less than 4.5 µA and noise voltages of less than 225 µV in the analog input path. START-UP AND RESET The AD12400’s FPGA configuration is stored in the on-board EPROM and loaded into the FPGA when power is applied to the device. The RESET pin (active low) allows the user to reload the FPGA in case of a low digital supply voltage condition or a power supply glitch. Pulling the RESET pin low will pull the data ready and output bits high until the FPGA has been reloaded. The RESET pin should remain low for a minimum of 200 ns. On the rising edge of the reset pulse, the AD12400 will start loading the configuration into the FPGA. The reload process requires a maximum of 600 ms to complete. Valid signals on the data ready pins indicate that the reset process is complete. Also, system designers need be aware of the thermal conditions of the AD12400 at start-up. If large thermal imbalances are present, the AD12400 may require additional time to stabilize before providing specified image spur performance. LEAD/LAG The LEAD/LAG pin is used to synchronize the collection of data into external buffer memories. The LEAD/LAG pin can be applied synchronously or asynchronously to the AD12400. If applied asynchronously, LEAD/LAG must be held high for a minimum of 5 ns to ensure correct operation. The function will shut off DRA and DRB until the LEAD/LAG pin is released. DRA and DRB will resume on the next valid DRA after LEAD/LAG is released. If this feature is not required, tie this pin to DGND. THERMAL CONSIDERATIONS The module is rated to operate over a case temperature of 0°C to 60°C. In order to maintain the tight channel matching and reliability of the AD12400, care must be taken to assure that proper thermal and mechanical considerations have been made and addressed to assure case temperature is kept within this range. Each application will require evaluation of the thermal management as applicable to the system design. The following provides information that should be used in the evaluation of AD12400 thermal management for each specific use. In addition to the radiation of heat into its environment, the AD12400 module enables flow of heat through the mounting studs and standoffs as they contact the motherboard. As described in the Package Integrity/Mounting Guidelines section, the module should be secured to the motherboard using 2-56 nuts (washer use is optional). The torque on the nuts should not exceed 32 inch ounces. Use of a thermal grease at the standoffs will result in better thermal coupling between the board and module. Depending on the ambient conditions, air flow may be necessary to ensure the components in the module do not exceed their maximum operating temperature. In terms of reliability, the most sensitive component has a maximum junction temperature rating of 125°C. Figures 21 and 22 provide a basic guideline for two key thermal management decisions: the use of thermal interface material between the module bottom cover/mother board and airflow. Figure 21 characterizes the typical thermal profile of an AD12400 that is not using thermal interface material. Figure 22 provides the same information for a configuration that uses gap-filling thermal interface material (in this case Thermagon T-Flex 600 series, 0.040” thickness was used). One can see from these profiles that the maximum die temperature is reduced by approximately 2°C when thermal interface material is used. Figures 21 and 22 also provide a guideline for determining the airflow requirements for given ambient conditions. For example, a goal of 120°C die temperature in a 40°C ambient environment without the use of thermal interface material would require an air flow of 100 LFM. See the AD12400 Thermal Management and Measurement Application Note for further details. From a channel matching perspective, the most important consideration will be external thermal influences. It is possible for thermal imbalances in the end application to adversely affect the dynamic performance. Due to the temperature dependence of the image spur, substantial deviation from the factory calibration conditions can have a detrimental effect. Unbalanced thermal influences can cause gradients across the module, and performance degradation may result. Examples of unbalanced thermal influences may include large heat dissipating elements near one side of the AD12400 or obstructed air flow that does not flow uniformly across the module. The thermal sensitivity of the module can be affected by a change in thermal gradient across the module of 2°C.

The AD12400/KIT offers an easy way to evaluate the AD12400. and analog input source connect directly to the AD12400KWS. (not included) connect to the evaluation board. Table 8. Power Connector *The power supply cable has approximately 100 mV drop. frequency. Refer to Figure 17. properly evaluate the AD12400. Windows® 98, Windows® 2000, and Windows NT®. connected to this connector if required. is on the top side of the evaluation board. AD12400 without the digital post processing. ready pins indicate that the reset process is complete.

Table 9. Evaluation Board Bill of Materials Figure 23. Evaluation Board

Figure 24. Evaluation Board

Rev. 0 | Page 25 of 28 LAYOUT GUIDELINES The AD12400 requires a different approach to traditional high speed analog-to-digital converter system layouts. While the AD12400’s internal PCB isolates digital and analog grounds, these planes are tied together through the product’s aluminum case structure. Therefore, the decision of isolating the analog and digital grounds on the system PCB has additional factors to consider. For example, if the AD12400 will be attached with conductive thermal interface material to the system PCB, there will be essentially no benefit to keeping the analog and digital ground planes separate. If either no thermal interface material or nonconductive interface material is used, system architects will have to consider the ground loop that will be created if analog and digital planes are tied together directly under the AD12400. This EMI based decision will have to be considered on a case-by-case basis and will be largely dependent on the other sources of EMI in the system. One critical consideration is that a 12-bit performance requirement (–74 dBc) will require keeping conducted EMI currents (referenced to the input of the AD12400) below 4.5 μA. All of the characterization and testing of the AD12400 was performed using a system that isolated these ground planes. If thermal interface material is used in the final system design, the following layout factors will need to be considered: open solder mask on the area that contacts the interface material and the thickness of the ground plane. While this should be analyzed in each specific system design, the use of solder mask may negate any advantage achieved by using the thermal interface material, and its use should be carefully considered. The ground plane thickness will not have a major impact on the thermal performance, but if design margin is slight, additional thickness can yield incremental improvements. PCB INTERFACE Figure 37 provides the mounting hole footprint for assembling the AD12400 to the second-level assembly. The diagram is referenced to the center of the mating QTE connector. Refer to the QTE/QSE series connector documentation at www.samtec.com for the SMT footprint of the mating connector. The top view of the second-level assembly footprint provides a diagram of the second-level assembly locating tab locations for mating the SAMTEC QTE-060-01-L-A-K-TR terminal strip on the AD12400BWS to a QSE-060-01-L-A-K-TR socket on the second-level assembly. The diagram is referenced to the center of the QTE terminal strip on the AD12400BWS and the mounting holds for the screws, which will hold the AD12400BWS to the second-level assembly board. The relationship of these locating tabs is based on information provided by SAMTEC (connector supplier) and should be verified with SAMTEC by the customer. Mating and unmating forces—the knifing or peeling action of applying force to one end or one side—must be avoided to prevent damage to the connector and guidepost.

Figure 37. Top View of Interface PCB Assembly

3.190 TYP

2.890 MAX BOARD

2.328 TYP

0.856 TYP

0.505 TYP 2×

0.700 MAX

0.175 TYP

0.200 TYP2-56 STUDS 4×

0.600 MAX

Figure 38. Outline Dimensions

Rev. 0 | Page 28 of 28 © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. C03735-0-11/03(0)