AD10677 AD | Alldatasheet
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Technical content
16-Bit, 65 MSPS A/D Converter AD10677 Rev. B Information furn ished by An alog D evices is believed to be accurate and reliable. However, n o resp onsibility is assume d b y A nalog De vices fo r its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or p atent rights of Analog De vices. Trademarks an d registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
FEATURES
65 MSPS sample rate
80 dBFS signal-to-noise ratio Transformer-coupled analog input Single PECL clock source Digital outputs True binary format
3.3 V and 5 V CMOS compatible
APPLICATIONS
Communications instrumentation Instrumentation Antenna array processing GENERAL DESCRIPTION The AD10677 is a 16-bit, high performance, analog-to-digital converter for applications that demand increased SNR levels. Exceptional noise performance and a typical signal-to-noise ratio of 80 dBFS are obtained by digitally postprocessing the outputs of four ADCs. A single analog input and PECL sampling clock are required as well as 3.3 V and 5 V power supplies. The AD10677 is assembled using a 0.062" thick laminate board with three sets of connector interface pads to accommodate analog and digital isolation. Analog Devices recommends using the FSI-110-03-G-D-AD-K-TR connector from Samtec: The overall card fits a 2.2 "× 2.8" PCB specified from 0°C to 70°C. FUNCTIONAL BLOCK DIAGRAM AD10677 ANALOG POWER CLOCK DISTRIBUTION CIRCUIT DIGITAL POWERENCODE ENCODE OUTPUT DATA BITS DIGITAL POST- PROCES- SING AGND ADC ADC ADC ADC AGND DGND DGND +3.3VE +3.3V +5VA AIN AIN DOUT0 DOUT15 03208-B-001 Figure 1 PRODUCT HIGHLIGHTS 1. Guaranteed sample rate of 65 MSPS. 2. Input signal conditioning with optimized noise performance. 3. Fully tested and guaranteed performance.
Rev. B | Page 2 of 20 TABLE OF CONTENTS
REVISION HISTORY
12/03—Data sheet changed from REV. A to REV.B 8/03—Data sheet changed from REV. 0 to REV. A
Table 1. AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V; TA = 25°C, Differential Encode = 65 MSPS, CLOAD ≤ 10 pF, unless otherwise noted. 1 Measurement includes the recommended interface connector. 3 Supply voltages should remain stable within 65% for normal operation. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V. 4 Power dissipation measured with encode at rated speed and –1 dBFS analog input at 10 MHz.
Table 2. AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V; TA = 25°C, Differential Encode = 65 MSPS, CLOAD ≤ 10 pF, unless otherwise noted. Table 3. AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V; TA = 25°C, Differential Encode = 65 MSPS, CLOAD ≤ 10 pF, unless otherwise noted. in dBFS, related back to converter full scale. in dBFS, related back to converter full scale. 3 Analog input signal at –1 dBFS; SFDR is ratio of converter full scale to worst spur. 4 Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third-order intermodulation product.
Table 4. AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V; TA = 25°C, Differential Encode = 65 MSPS, CLOAD ≤ 10 pF, unless otherwise noted. II. 100% production tested at 25°C and sample tested at specified temperatures. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. production tested at temperature extremes for military devices.
may affect device reliability. Table 5. AD10677 Stress Ratings Thermal Considerations section. Table 6. Output Coding (True Binary) degradation or loss of functionality.
Table 7. Interfaces 1 and 2: Digital Pin Function Descriptions
1 DGND Digital Ground 1 DGND Digital Ground
2 DGND Digital Ground 2 DGND Digital Ground
4 NC No Connection 4 DOUT0 Data Bit Output
6 DGND Digital Ground 6 DOUT1 Data Bit Output
8 NC No Connection 8 DOUT2 Data Bit Output
9 DOUT12 Data Bit Output 9 DGND Digital Ground
10 DGND Digital Ground 10 DOUT3 Data Bit Output
11 DOUT11 Data Bit Output 11 DGND Digital Ground
12 NC No Connection 12 DOUT4 Data Bit Output
13 DOUT10 Data Bit Output 13 DGND Digital Ground
14 DGND Digital Ground 14 DOUT5 Data Bit Output
15 DOUT9 Data Bit Output 15 DGND Digital Ground
16 NC No Connection 16 DOUT6 Data Bit Output
18 DGND Digital Ground 18 DOUT7 Data Bit Output
20 NC No Connection 20 DGND Digital Ground
Table 8. Interface 3: Analog Pin Function Descriptions
5 AGND Analog Ground
7 AGND Analog Ground
9 AGND Analog Ground
10 AGND Analog Ground
11 AGND Analog Ground
12 AIN Analog Input
13 AGND Analog Ground
14 AIN Analog Input
15 ENCODE Encode Input
16 AGND Analog Ground
17 ENCODE Encode Input
18 AGND Analog Ground
19 AGND Analog Ground
20 AGND Analog Ground
Figure 6. Header Interface Dimensions (Inches)
junction temperature (150°C) is not exceeded.
- Operation temperature (TA) must be within 0° to 70°C.
- All mounting standoffs should be fastened to the interface PCB assembly with 2-56 nuts. This ensures good thermal paths as well as excellent ground points.
- The unit rises to ~72°C (TC) on the heat sink in still air (0 linear feet per minute (LFM)). The minimum recommended air flow is100 linear feet per minute (LFM) in either direction across the heat sink is (see Figure 15). 03208-B-023 AIR FLOW (LFM) 3000 100 15050 200 250 TEMPERATURE (CASE) (°C)
Figure 15. Temperature (Case) vs. Air Flow (Ambient) correlated and sums on an rms basis. phase, the differential analog input signal is 2.15 V p-p. interface to commercial cables, filters, and drivers, etc. terminators and are applied to the CPLD for postprocessing. digital CMOS compatible word coded as true binary. 2.15 V p-p input level to achieve full scale. performance, the AD10677 must be clocked differentially. Take care when designing the data receivers for the AD10677. specifications. Digital output timing is guaranteed with 10 pF. helping to minimize digital corruption of sensitive analog signals. section of the ADCs, the PCEL-to-TTL translator, and the CPLD. supply provides power to the analog sections of the ADCs. the circuit to provide low impedance noise shunts to ground.
grounding is essential in high speed, high resolution systems. power plane, printed circuit board material, and ground plane. be connected accordingly on the next level assembly. are described in Table 7 and Table 8. uninsulated metal banana jacks. converts the circuit to a differential analog input configuration. Table 9. PCB Bill of Material
Figure 16. Evaluation Board Schematic
Figure 17. Evaluation Board Mechanical Layout, Top View
Figure 18. Evaluation Board Mechanical Layout, Bottom View
Rev. B | Page 19 of 20 OUTLINE DIMENSIONS 2.795 2.745 2.695 2.220 2.170 2.120 0.170 0.120 0.070 0.370 0.320 0.270 0.314 0.264 0.214 Top View Bottom View a AD10677BWS LOT NUMBER DATA CODE USA Dimensions shown in inches Tolerances: 0.xx = ±10 mils 0.xxx = ±5 mils Figure 23
Rev. B | Page 20 of 20 ORDERING GUIDE Model Temperature Range Package Description Package Option AD10677BWS 0°C to 70°C Non-Herm Hybrid Surf Mount (2.2" × 2.8") WS-120 AD10677/PCB 25°C Evaluation Board © 2003 An alog Devices, Inc. All righ ts reserve d. Tr ademarks an d registered trade marks are the pr operty of their respectiv e ow ners. C03208–0–12/03(B)