AD10677

AD10677_15 AD | Alldatasheet

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16-Bit, 65 MSPS A/D Converter AD10677 Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

FEATURES

65 MSPS sample rate

80 dBFS signal-to-noise ratio Transformer-coupled analog input Single PECL clock source Digital outputs True binary format

3.3 V and 5 V CMOS-compatible

APPLICATIONS

Communications instrumentation Instrumentation Antenna array processing GENERAL DESCRIPTION The AD10677 is a 16-bit, high performance, analog-to-digital converter (ADC) for applications that demand increased SNR levels. Exceptional noise performance and a typical signal-to- noise ratio of 80 dBFS are obtained by digitally postprocessing the outputs of four ADCs. A single analog input and PECL sampling clock and 3.3 V and 5 V power supplies are required. The AD10677 is assembled using a 0.062-inch laminate board with three sets of connector interface pads to accommodate analog and digital isolation. Analog Devices recommends using the FSI-110-03-G-D-AD-K-TR connector from Samtec. The overall card fits a 2.2 inch × 2.8 inch PCB specified from 0°C to 70°C. FUNCTIONAL BLOCK DIAGRAM 03208-B-001 AD10677 ANALOG POWER CLOCK DISTRIBUTION CIRCUIT DIGITAL POWERENCODE ENCODE AGND ADC ADC ADC ADC AGND DGND DGND +3.3VE +3.3V +5VA AIN AIN DOUT0 DOUT15 DIGITAL POST- PROCES- SING OUTPUT DATA BITS Figure 1. PRODUCT HIGHLIGHTS 1. Guaranteed sample rate of 65 MSPS. 2. Input signal conditioning with optimized noise performance. 3. Fully tested and guaranteed performance.

Rev. D | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

5/06—Rev. C to Rev. D 3/05—Rev. B to Rev. C 12/03—Rev. A to Rev. B 8/03—Rev. 0 to Rev. A 11/02—Revision 0: Initial Version

Rev. D | Page 3 of 20 SPECIFICATIONS DC SPECIFICATIONS AVCC = 5 V , EVCC = 3.3 V , VDD = 3.3 V , TA = 25°C, differential encode = 65 MSPS, CLOAD ≤ 10 pF, unless otherwise noted. Table 1. Parameter Test Level Min Typ Max Unit RESOLUTION 16 Bits Offset Error I –0.30 +0.12 +0.30 %FS Gain Error I –7 +7 %FS Differential Nonlinearity (DNL) V ±0.7 LSB Integral Nonlinearity (INL) V ±4 LSB TEMPERATURE DRIFT Offset Error V 13 ppm/ºC Gain Error V 200 ppm/ºC POWER SUPPLY REJECTION RATIO (PSRR) V 60 dB ANALOG INPUTS (AIN, AIN)1 Differential Input Voltage Range V 2.15 V p-p Differential Input Resistance V 50 Ω Differential Input Capacitance V 2.5 nF Input Bandwidth IV 0.40 210 MHz VSWR2 V 1.04:1 Ratio POWER SUPPLY3 Supply Current IAVCC (AVCC = 5.0 V) I 0.95 1.05 A IEVCC (EVCC = 3.3 V) I 0.15 0.2 A IVDD (VDD = 3.3 V) I 0.49 0.625 A Total Power Dissipation4 I 6.86 7.5 W 1 Measurement includes the recommended interface connector. 2 Input VSWR, see Figure 15. 3 Supply voltages should remain stable within 65% for normal operation. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V. 4 Power dissipation measured with encode at rated speed and −1 dBFS analog input at 10 MHz. DIGITAL SPECIFICATIONS AVCC = 5 V , EVCC = 3.3 V , VDD = 3.3 V , TA = 25°C, differential encode = 65 MSPS, CLOAD ≤ 10 pF, unless otherwise noted. Table 2. Parameter Test Level Min Typ Max Unit ENCODE INPUTS (ENCODE, ENCODE) Differential Input Voltage Range IV 0.4 V p-p Differential Input Resistance V 100 Ω Differential Input Capacitance V 160 pF LOGIC OUTPUTS (D15 to D0) Logic Compatibility CMOS Logic 1 Voltage ILOAD ≤ 100 mA IV 0.9 × VDD V Logic 0 Voltage ILOAD ≤ 100 mA IV 0.4 V Output Coding True binary Series Output Resistance per Bit 120 Ω

Rev. D | Page 4 of 20 AC SPECIFICATIONS AVCC = 5 V , EVCC = 3.3 V , VDD = 3.3 V , TA = 25°C, differential encode = 65 MSPS, CLOAD ≤ 10 pF, unless otherwise noted. Table 3. Parameter Test Level Min Typ Max Unit SNR1 Analog Input 2.5 MHz I 77.5 80 dBFS @ –1 dBFS 10 MHz I 77.5 80 dBFS 30 MHz I 76.5 78.5 dBFS SINAD2 Analog Input 2.5 MHz I 77.2 79 dBFS @ –1 dBFS 10 MHz I 77.2 79 dBFS 30 MHz I 74.5 77 dBFS SFDR3 Analog Input 2.5 MHz I 84 92 dBFS @ –1 dBFS 10 MHz I 84 92 dBFS 30 MHz I 79.5 84 dBFS TWO-TONE4 Analog Input @ –7 dBFS—IMD f1 = 10 MHz, f2 = 12 MHz V 96 dBFS 1 Analog input signal power at –1 dBFS; signal-to-noise (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 65 MSPS. SNR is reported in dBFS, related back to converter full scale. 2 Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS. SINAD is reported in dBFS, related back to converter full scale. 3 Analog input signal at –1 dBFS; SFDR is the ratio of converter full scale to the worst spur. 4 Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third-order intermodulation product. SWITCHING SPECIFICATIONS AVCC = 5 V , EVCC = 3.3 V , VDD = 3.3 V , TA = 25°C, differential encode = 65 MSPS, CLOAD ≤ 10 pF, unless otherwise noted. Table 4. Parameter Test Level Min Typ Max Unit MAXIMUM CONVERSION RATE I 65 MSPS MINIMUM CONVERSION RATE IV 15 MSPS DUTY CYCLE IV 40 60 % ENCODE INPUT PARAMETERS Encode Period @ 65 MSPS, tENC V 15.4 ns Encode Pulse Width High @ 65 MSPS, tENCH V 7.7 ns Encode Pulse Width Low @ 65 MSPS, tENCL V 7.7 ns ENCODE/DATA (D15:D0) Propagation Delay, tPDH 6.7 ns Valid Time, tPDL 7.3 ns APERTURE DELAY, tA V 480 ps APERTURE UNCERTAINTY (JITTER), tJ V 500 fs rms PIPELINE DELAYS V 9 Cycles

Table 6. Output Coding (True Binary) V . Parameter is a typical value only. production tested at temperature extremes for military devices. Thermal Considerations section. degradation or loss of functionality.

ALL METAL HARDWARE TO BE TORQUED TO 1.0 INCH-POUND. Figure 9. Interface PCB Assembly, Top View

Rev. D | Page 11 of 20 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point on the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Nonlinearity (DNL) The deviation of any code from an ideal 1 LSB step. Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time the encode pulse should be left in a Logic 1 state to achieve rated perform- ance; pulse width low is the minimum time the encode pulse should be left in a low state. At a given clock rate, these speci- fications define an acceptable encode duty cycle. Integral Nonlinearity (INL) The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit. Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the worst harmonic component. Maximum Conversion Rate The encode rate at which parametric testing is performed. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB or less below the guaranteed limit. Output Propagation Delay The delay between the 50% point of the rising edge of the ENCODE command and the time when all output data bits are within valid logic levels. Power Supply Rejection Ratio (PSRR) The ratio of a change in output offset voltage to a change in power supply voltage. Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral compo- nents, including the first five harmonics and dc. Can be reported in dBc (that is, degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Can be reported in dBc (that is, degrades as the signal level is lowered) or in dBFS (always related back to converter full scale). Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious compo- nent may or may not be an harmonic. SFDR can be reported in dBc (that is, degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection (IMD) The ratio of the rms value of an input tone to the rms value of the worst third-order intermodulation product; reported in dBc. Voltage Standing-Wave Ratio (VSWR) The ratio of the amplitude of the elective field at a voltage maximum to that at an adjacent voltage minimum.

Figure 19. Evaluation Board Schematic

Figure 26. AD10677 Outline Dimensions

Rev. D | Page 19 of 20 NOTES

Rev. D | Page 20 of 20 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. C03208-0-5/06(D)