AD10465

AD10465 (Rev. B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 24

Technical content

Dual Channel, 14-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning Data Sheet AD10465 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2001–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Dual, 65 MSPS minimum sample rate Channel-to-channel matching, ±0.5% gain error Channel-to-channel isolation, >90 dB DC-coupled signal conditioning included Selectable bipolar input voltage range Gain flatness up to 25 MHz: <0.2 dB 80 dB spurious-free dynamic range Twos complement output format

3.3 V or 5 V CMOS-compatible output levels

1.75 W per channel

Industrial and military grade

APPLICATIONS

Multichannel, multimode receivers GENERAL DESCRIPTION The AD10465 is a full channel ADC solution with on-module signal conditioning for improved dynamic performance and fully matched channel-to-channel performance. The module includes two wide dynamic range AD6644 ADCs. Each AD6644 has a dc-coupled amplifier front end including an AD8037 low distortion, high bandwidth amplifier that provides high input impedance and gain and drives the AD8138 single- to-differential amplifier. The AD6644s have on-chip track-and- hold circuitry and utilize an innovative multipass architecture to achieve 14-bit, 65 MSPS performance. The AD10465 uses innovative high density circuit design and laser trimmed, thin film resistor networks to achieve exceptional matching and performance, while still maintaining excellent isolation and providing for significant board area savings. The AD10465 operates with ±5.0 V supplies for the analog signal conditioning with a separate 5.0 V supply for the analog- to-digital conversion and 3.3 V digital supply for the output stage. Each channel is completely independent, allowing operation with independent encode and analog inputs. The AD10465 also offers the user a choice of analog input signal ranges to further minimize additional external signal conditioning, while remaining general-purpose. The AD10465 is packaged in a 68-lead ceramic leaded chip carrier package, footprint-compatible with the earlier generation AD10242 (12-bit, 40 MSPS) and AD10265 (12-bit, 65 MSPS). Manufacturing is done on the Analog Devices Mil-

38534 Qualified Manufacturers Line (QML) and components

are available up to Class-H (−40°C to +85°C). The AD6644 internal components are manufactured on Analog Devices’ high speed complementary bipolar process (XFCB). PRODUCT HIGHLIGHTS 1. Guaranteed sample rate of 65 MSPS. 2. Input amplitude options, user configurable. 3. Input signal conditioning included; both channels matched for gain. 4. Fully tested/characterized performance. 5. Footprint-compatible family; 68-lead CLCC package. FUNCTIONAL BLOCK DIAGRAM VREF DROUT OUTPUT BUFFERING TIMING 3 VREF DROUT D11 D12A D13A (MSBA) D0B (LSBB) D1B D2B D3B D4B D5B D6B D7B D8B OUTPUT BUFFERING TIMING D9B ENCODEB ENCODEB DRBOUT D10B D11B D12B D13B (MSBB) REF_B D0A (LSB) D1A D2A D3A D4A D5A D6A D7A D8A D9A D10A AD10465 DRAOUT 12 AINA3 AINA2 AINA1 AINB3 REF_A AINB2 AINB1 ENCODEA 29 31 32 33 34 35 36 37 38 39 40 41 42 ENCODEA 02356-001 Figure 1.

Rev. B | Page 2 of 24 TABLE OF CONTENTS

REVISION HISTORY

7/15—Rev. A to Rev. B 3/06—Rev. 0 to Rev. A 1/01—Revision 0: Initial Version

Rev. B | Page 3 of 24 SPECIFICATIONS AVCC = +5 V; A VEE = –5 V; DVCC = 3.3 V applies to each ADC, unless otherwise noted. All specifications guaranteed within 100 ms of initial power-up, regardless of sequencing. Table 1. Test1 Mil AD10465BZ/QML-H Parameter Temp Level Subgroup Min Typ Max Unit RESOLUTION 14 Bits DC ACCURACY No Missing Codes Full VI 1, 2, 3 Guaranteed Offset Error 25°C I 1 −2.2 ±0.02 +2.2 % FS Full VI 2, 3 −2.2 ±1.0 +2.2 % FS Offset Error Channel Match Full V −1 ±1.0 +1 % Gain Error2 25°C I 1 −3 −1.0 +1 % FS Full VI 2, 3 −5 ±2.0 +5 % FS Gain Error Channel Match 25°C I 1 −1.5 ±0.5 +1.5 % Max I 2 −3 ±1.0 +3 % Min I 3 −5 +5 % ANALOG INPUT (AIN) Input Voltage Range AIN1 Full V ±0.5 V AIN2 Full V ±1.0 V AIN3 Full V ±2 V Input Resistance AIN1 Full IV 12 99 100 101 Ω AIN2 Full IV 12 198 200 202 Ω AIN3 Full IV 12 396 400 404 Ω Input Capacitance3 25°C IV 12 0 4.0 7.0 pF Analog Input Bandwidth4 Full V 100 MHz ENCODE INPUT (ENC, ENC)5 Differential Input Voltage Full IV 0.4 V p-p Differential Input Resistance 25°C V 10 kΩ Differential Input Capacitance 25°C V 2.5 pF SWITCHING PERFORMANCE Maximum Conversion Rate6 Full VI 4, 5, 6 65 MSPS Minimum Conversion Rate6 Full V 12 20 MSPS Aperture Delay (tA) 25°C V 1.5 ns Aperture Delay Matching 25°C IV 12 250 500 ps Aperture Uncertainty (Jitter) 25°C V 0.3 ps rms ENCODE Pulse Width High 25°C IV 12 6.2 7.7 9.2 ns ENCODE Pulse Width Low 25°C IV 12 6.2 7.7 9.2 ns Output Delay (tOD) Full V 6.8 ns ENCODE, Rising to Data Ready, Rising Delay (TE_DR) Full 11.5 ns SNR7 Analog Input @ 4.98 MHz 25°C V 70 dBFS Analog Input @ 9.9 MHz 25°C I 4 69 70 dBFS Full II 5, 6 68 70 dBFS Analog Input @ 19.5 MHz 25°C I 4 68 70 dBFS Full II 5, 6 67 70 dBFS Analog Input @ 32.1 MHz 25°C I 4 67 69 dBFS Full II 5, 6 67 69 dBFS

Rev. B | Page 4 of 24 Test1 Mil AD10465BZ/QML-H Parameter Temp Level Subgroup Min Typ Max Unit SINAD8 Analog Input @ 4.98 MHz 25°C V 70 dB Analog Input @ 9.9 MHz 25°C I 4 67.5 69 dB Full II 5, 6 67.5 69 dB Analog Input @ 19.5 MHz 25°C I 4 65 68 dB Full II 5, 6 65 68 dB Analog Input @ 32.1 MHz 25°C I 4 60 63 dB Full II 5, 6 58 61 dB SPURIOUS-FREE DYNAMIC RANGE9 Analog Input @ 4.98 MHz 25°C V 85 dBFS Analog Input @ 9.9 MHz 25°C I 4 73 82 dBFS Full II 5, 6 70 82 dBFS Analog Input @ 19.5 MHz 25°C I 4 72 78 dBFS Full II 5, 6 70 78 dBFS Analog Input @ 32.1 MHz 25°C I 4 62 68 dBFS Full II 5, 6 60 66 dBFS TWO-TONE IMD REJECTION10 fIN = 10 MHz and 11 MHz 25°C I 4 78 87 dBFS f1 and f2 are −7 dB II 5, 6 78 dBFS fIN = 31 MHz and 32 MHz 25°C I 4 68 70 dBFS f1 and f2 Are −7 dB Full II 5, 6 60 dBFS CHANNEL-TO-CHANNEL ISOLATION11 25°C IV 12 90 dB TRANSIENT RESPONSE 25°C V 15.3 ns OVERVOLTAGE RECOVERY TIME VIN = 2.0 × fS Full IV 12 40 100 ns VIN = 4.0 × fS Full IV 12 150 200 ns DIGITAL OUTPUTS12 Logic Compatibility CMOS DVCC = 3.3 V Logic 1 Voltage Full I 1, 2, 3 2.5 DVCC − 0.2 V Logic 0 Voltage Full I 1, 2, 3 0.2 0.5 V DVCC = 5 V Logic 1 Voltage Full V DVCC − 0.3 V Logic 0 Voltage Full V 0.35 V Output Coding Twos complement POWER SUPPLY AVCC Supply Voltage13 Full VI 4.85 5.0 5.25 V I (AVCC) Current Full I 270 308 mA AVEE Supply Voltage13 Full VI −5.25 −5.0 −4.75 V I (AVEE) Current Full V 38 49 mA DVCC Supply Voltage13 Full VI 3.135 3.3 3.465 V I (DVCC) Current Full V 30 46 mA ICC (Total) Supply Current per Channel Full I 1, 2, 3 338 403 mA Power Dissipation (Total) Full I 1, 2, 3 3.5 3.9 W Power Supply Rejection Ratio (PSRR) Full V 0.02 % FSR/% VS Passband Ripple to 10 MHz V 0.1 dB Passband Ripple to 25 MHz V 0.2 dB

Rev. B | Page 5 of 24 1 See Table 3. 2 Gain tests are performed on AIN1 input voltage range. 3 Input capacitance specification combines AD8037 die capacitance and ceramic package capacitance. 4 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 5 All ac specifications tested by driving ENCODE and ENCODE differentially. 6 Minimum and maximum conversion rates allow for variation in encode duty cycle of 50% ± 5%. 7 Analog input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). ENCODE = 65 MSPS. SNR is reported in dBFS, related back to converter full power. 8 Analog input signal power at –1 dBFS. Signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. ENCODE = 65 MSPS. 9 Analog input signal power swept from −1 dBFS to −60 dBFS; SFDR is the ratio of converter full scale to worst spur. 10 Both input tones at −7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermodulation product. 11 Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel. 12 Digital output logic levels: DVCC = 3.3 V, CLOAD = 10 pF. Capacitive loads > 10 pF degrade performance. 13 Supply voltage recommended operating range. AVCC can be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V.

Table 3. Test Levels V Parameter is a typical value only.

Figure 7. Pin Configuration Table 4. Pin Function Descriptions 1 SHIELD Internal Ground Shield Between Channels. 3 REF_A A Channel Internal Voltage Reference. 6 AINA1 Analog Input for A Side ADC (Nominally ±0.5 V). 7 AINA2 Analog Input for A Side ADC (Nominally ±1.0 V). 8 AINA3 Analog Input for A Side ADC (Nominally ±2.0 V). 12 DRAOUT Data Ready A Output. 13 AVEE Analog Negative Supply Voltage (Nominally −5.0 V or −5.2 V). 14 AVCC Analog Positive Supply Voltage (Nominally 5.0 V). 26, 27 DGNDA A Channel Digital Ground. 15 to 25, 31 to 33 D0A to D13A Digital Outputs for ADC A. D0A (LSBA). 28 ENCODEA Complement of ENCODE. 29 ENCODEA Data Conversion Initiated on Rising Edge of ENCODE Input. 30 DVCC Digital Positive Supply Voltage (Nominally 5.0 V or 3.3 V). 43, 44 DGNDB B Channel Digital Ground. 34 to 42, 45 to 49 D0B to D13B Digital Outputs for ADC B. D0B (LSBB). 50 DVCC Digital Positive Supply Voltage (Nominally 5.0 V or 3.3 V). 51 ENCODEB Data conversion initiated on rising edge of ENCODE input. 52 ENCODEB Complement of ENCODEB. 55 DRBOUT Data Ready B Output. 56 REF_B B Channel Internal Voltage Reference. 62 AINB1 Analog Input for B Side ADC (Nominally ±0.5 V). 63 AINB2 Analog Input for B Side ADC (Nominally ±1.0 V). 64 AINB3 Analog Input for B Side ADC (Nominally ±2.0 V). 66 AVCC Analog Positive Supply Voltage (Nominally 5.0 V). 67 AVEE Analog Negative Supply Voltage (Nominally −5.0 V or −5.2 V).

Rev. B | Page 11 of 24 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between a differential crossing of ENCODE and ENCODE, and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Nonlinearity The deviation of any code from an ideal 1 LSB step. ENCODE Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulse width low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable encode duty cycle. Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the worst harmonic component. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed, above which converter performance can degrade. Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE, and the time when all output data bits are within valid logic levels. Overvoltage Recovery Time The amount of time required for the converter to recover to 0.02% accuracy after an analog input signal of the specified percentage of full scale is reduced to midscale. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral compo- nents, including harmonics but excluding dc. Can be reported in dB (that is, relative to signal level) or in dBFS (always related back to converter full scale). Signal-to-Noise Ratio (Without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc. Can be reported in dB (that is, relative to signal level) or in dBFS (always related back to converter full scale). Spurious-Free Dynamic Range The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. Transient Response The time required for the converter to achieve 0.03% accuracy when a one-half, full-scale step function is applied to the analog input. Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dBFS.

2 V p-p, and 4 V p-p) and input impedance (100 Ω, 200 Ω, and

analog-to-digital converter. the proper input terminal for the application. dynamic range capability on the amplifiers inputs and outputs.

300 MHz and delivers a differential signal with the lowest

to the AD6644, maximizing the performance of the ADC. which is the midsupply level for the AD6644. digital CMOS-compatible word, coded as twos complement. the impedance options available at each input location. Table 5. Input Impedance Options

Rev. B | Page 14 of 24 POWER SUPPLIES Care should be taken when selecting a power source. Linear supplies are strongly recommended. Switching supplies tend to have radiated components that can be “received” by the AD10465. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 μF chip capacitors. The AD10465 has separate digital and analog power supply pins. The analog supplies are denoted AVCC and the digital supply pins are denoted DVCC. AVCC and DVCC should be separate power supplies. This is because the fast digital output swings can couple switching current back into the analog sup- plies. Note that AVCC must be held within 5% of 5 V . The AD10465 is specified for DVCC = 3.3 V as this is a common supply for digital ASICs. OUTPUT LOADING Care must be taken when designing the data receivers for the AD10465. The digital outputs drive an internal series resistor (for example, 100 Ω) followed by a gate, such as the 75LCX574. To minimize capacitive loading, there should only be one gate on each output pin. An example of this is shown in the evaluation board schematic shown in Figure 26. The digital outputs of the AD10465 have a constant output slew rate of 1 V/ns. A typical CMOS gate combined with a PCB trace has a load of approximately 10 pF. Therefore, as each bit switches, 10 mA (10 pF × 1 V ÷1 ns) of dynamic current per bit flows in or out of the device. A full-scale transition can cause up to 140 mA (14 bits ×10 mA/bit) of current flow through the output stages. These switching currents are confined between ground and the DV CC pin. Standard TTL gates should be avoided because they can appreciably add to the dynamic switching currents of the AD10465. It should also be noted that extra capacitive loading increases output timing and invalidates timing specifications. Digital output timing is guaranteed with 10 pF loads. LAYOUT INFORMATION The schematic of the evaluation board (see Figure 24) represents a typical implementation of the AD10465. The pinout of the AD10465 is very straightforward and facilitates ease of use and the implementation of high frequency/high resolution design practices. It is recommended that high quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. All capacitors can be standard high quality ceramic chip capacitors. Care should be taken when placing the digital output runs. Because the digital outputs have such a high slew rate, the capacitive loading on the digital outputs should be minimized. Circuit traces for the digital outputs should be kept short and connect directly to the receiving gate. Internal circuitry buffers the outputs of the ADC through a resistor network to eliminate the need to externally isolate the device from the receiving gate.

Connector J1 and Connector J2. Power to the analog supply pins is connected via banana jacks. factory if additional layout or applications assistance is required. Figure 23. Evaluation Board Mechanical Layout

Figure 24. Evaluation Board

Figure 25. Evaluation Board

Figure 26. Evaluation Board

Table 6. Bill of Materials

2 U2, U4 IC, low-voltage Quad 2-input nand,

2 U21, U22 IC, 16-bit transparent latch with

1 U1 DUT, IC 14-bit analog-to-digital

10 E1 to E10 Banana jack, socket Johnson Components/08-

22 C13 to C15, C20, C21,

2 C43, C45 100 pF Capacitor, 100 pF, 10%, 12 V dc, 0805 Johansen/500R15N101JV4 CAP 0805

2 J3, J4 Connector, 40-pin header male Samtec/TSW-120-08-G-D HD40M

6 L6 to L11 47 μH Inductor, 47 μH @ 100 MHz, 20%,

2 U7, U9 IC, differential receiver, SOIC-8 Motorola/MC10EP16D MC10EP16D

6 C22, C52, C53, C58,

8 R76, R79, R82, R83, R98,

36 R89, R94, R95, R97,

8 J1, J2, J6 to J8, J16 to

Figure 35. 68-Lead Ceramic Leaded Chip Carrier [CLCC] 1 The data sheet for the 5962-9961601HXA is the property of and maintained by DSCC. registered trademarks are the property of their respective owners.