AD10265

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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. AD10265

FEATURES

Dual, 65 MSPS Minimum Sample Rate Channel-Channel Matching, 60.1% Gain Error Channel-Channel Isolation, >80 dB AC-Coupled Signal Conditioning Included Selectable Bipolar Input Voltage Range Gain Flatness up to Nyquist: < 0.5 dB 80 dB Spurious-Free Dynamic Range Twos Complement Output Format +3.3 V or +5 V CMOS-Compatible Output Levels

1.05 W Per Channel

Industrial and Military Grade

APPLICATIONS

GPS Anti-Jamming Receivers Multichannel, Multimode Receivers FUNCTIONAL BLOCK DIAGRAM D11B (MSB) D10B D9B D8B D7B D0B (LSB) D1B D2B D3B D4B D5B D6BD9A D10A D11A (MSB) (LSB) D0A D1A D2A D3A D4A D5A D6A D7A D8A ENCODEA AINB3 ENCODEB ENCODEB TIMING ENCODEA AD9631AD9632 AIN AIN AINA2 A INA1AINA3 AD6640 OUTPUT BUFFERING AD10265 AINB2 A INB1 OUTPUT BUFFERING TIMING AD9631AD9632 AIN AIN AD6640 Dual Channel, 12-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioninga PRODUCT DESCRIPTION The AD10265 is a full channel ADC solution with on-module signal conditioning for improved dynamic performance and fully matched channel-to-channel performance. The module includes two wide dynamic range AD6640 ADCs. Each AD6640 has an AD9631/AD9632 ac-coupled amplifier front end. The AD6640s have on-chip track-and-hold circuitry, and utilize an innovative multipass architecture, to achieve 12-bit, 65 MSPS performance. The AD10265 uses innovative high- density circuit design and laser-trimmed thin-film resistor networks to achieve exceptional matching and performance while still maintaining excellent isolation, and providing for significant board area savings. The AD10265 operates with – 5.0 V for the analog signal conditioning with a separate +3.3 V supply for the analog-to- digital conversion. Each channel is completely independent allowing operation with independent Encode and Analog in- puts. The AD10265 also offers the user a choice of Analog Input Signal ranges to further minimize additional external signal conditioning, while still remaining general-purpose. The AD10265 is packaged in a 68-lead Ceramic Gull Wing Package, footprint compatible with the earlier generation AD10242 (12-bit, 40 MSPS). Manufacturing is done on Analog Devices’ MIL-38534 Qualified Manufacturers Line (QML) and components are available up to Class-H (–55°C to +125°C). The AD6640 internal components are manufactured on Analog Devices’ high speed complementary bipolar process (XFCB). PRODUCT HIGHLIGHTS 1. Guaranteed sample rate of 65 MSPS. 2. Input amplitude options, user configurable. 3. Input signal conditioning included; both channels matched for gain. 4. Fully tested/characterized performance for full channel. 5. Footprint compatible family; 68-lead LCCC. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998

REV. 0–2– AD10265–SPECIFICATIONS Electrical Characteristics(AVCC = +5 V; AVEE = –5.0 V; DV CC = +3.3 V; applies to each ADC unless otherwise noted) Test Mil AD10265AZ Parameter Temp Level Subgroup Min Typ Max Units RESOLUTION 12 Bits ACCURACY No Missing Codes Full VI 1, 2, 3 Guaranteed Offset Error Full IV 2, 3 –10 3.5 +10 mV Gain Error Full VI 2, 3 –2.0 – 0.8 +2.0 % FS Gain Error Channel Match Full V – 0.1 % Pass Band Ripple to Nyquist Full I 12 0.2 0.5 dB ANALOG INPUT (A IN) Input Voltage Range AIN1 Full I – 0.5 V AIN2 Full I – 1.0 V AIN3 Full I – 2V Input Resistance AIN1 Full IV 12 99 100 101 W AIN2 Full IV 12 198 200 202 W AIN3 Full IV 12 396 400 404 W Input Capacitance 2 +25°CI V 1 2 0 4 . 0 7 . 0 p F Analog Input Bandwidth High 3 +25°C V 160 MHz Analog Input Bandwidth Low 3 +25°CV 5 0 k H z ENCODE INPUT4, 5 Logic Compatibility TTL/CMOS Logic “1” Voltage Full I 1, 2, 3 2.0 5.0 V Logic “0” Voltage Full I 1, 2, 3 0 0.8 V Logic “1” Current (VINH = 5 V) Full I 1, 2, 3 500 650 800 mA Logic “0” Current (VINL = 0 V) Full I 1, 2, 3 –400 –320 –200 mA Input Capacitance +25 °CV 1 2 4 . 5 7 . 0 p F SWITCHING PERFORMANCE Maximum Conversion Rate 6 Full VI 4, 5, 6 65 MSPS Minimum Conversion Rate 6 Full V 12 6.5 MSPS Aperture Delay (t A) +25 °C V 400 ps Aperture Delay Matching +25 °CV – 2.0 ns Aperture Uncertainty (Jitter) +25 °C V 0.3 ps rms ENCODE Pulsewidth High +25 °C IV 12 6.5 ns ENCODE Pulsewidth Low +25 °C IV 12 6.5 ns Output Delay (t OD) Full IV 12 7.0 9.0 12.5 ns SNR7 Analog Input @ 1.24 MHz +25 °CI 4 6 2 6 6 d B Full II 5, 6 60.5 66 dB @ 17 MHz +25 °CI 4 6 1 6 5 d B Full II 5, 6 60 65 dB @ 32 MHz +25 °CI 4 6 1 6 3 d B Full II 5, 6 59.5 62 dB SINAD8 Analog Input @ 1.24 MHz +25 °CI 4 6 1 6 5 d B Full II 5, 6 60 64 dB @ 17 MHz +25 °CI 4 6 1 6 4 d B Full II 5, 6 59.5 63 dB @ 32 MHz +25 °CI 4 6 1 6 2 d B Full II 5, 6 59 62 dB

Parameter Temp Level Subgroup Min Typ Max Units SPURIOUS-FREE DYNAMIC RANGE 9 Analog Input @ 1.24 MHz +25 °C I 4 75 80 dBFS Full II 5, 6 75 80 dBFS @ 17 MHz +25 °C I 4 72 80 dBFS Full II 5, 6 72 79 dBFS @ 32 MHz +25 °C I 4 72 79 dBFS Full II 5, 6 72 79 dBFS TWO-TONE IMD REJECTION 10 f1, f2 @ –7 dBFS Full II 4, 5, 6 72 80 dBc CHANNEL-TO-CHANNEL ISOLATION11 +25°CI V 1 2 8 0 d B LINEARITY Differential Nonlinearity (Encode = 20 MHz) +25 °C IV 12 –1.0 – 0.5 1.5 LSB Integral Nonlinearity (Encode = 20 MHz) Full V – 1.25 LSB DIGITAL OUTPUTS Logic Compatibility CMOS Logic “1” Voltage Full I 1, 2, 3 2.8 DV CC – 0.2 V Logic “0” Voltage Full I 1, 2, 3 0.2 0.5 V Output Coding Twos Complement POWER SUPPLY AVCC Supply Voltage Full VI +5.0 V I (AVCC) Current Full V 336 mA AVEE Supply Voltage Full VI –5.0 V I (AVEE) Current Full V 66 mA DVCC Supply Voltage Full VI +3.3 V I (DVCC) Current Full V 20 mA ICC (Total) Supply Current Full I 1, 2, 3 422 520 mA Power Dissipation (Total) Full I 1, 2, 3 2.1 2.4 W Power Supply Rejection Ratio (PSRR) Full IV 7, 8 0.01 0.02 % FSR/% V S NOTES 1Gain tests are performed on A IN1 over specified input voltage range. 2Input capacitance specifications show only ceramic package capacitance. 3Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 mF capacitor. 5ENCODE may also be driven differentially in conjunction with ENCODE; see “Encoding the AD10265” for details. 6Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% – 5%. 7Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonic s removed). Encode = 65 MSPS. 8Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harm onics. Encode = 65 MSPS. 9Analog Input signal equal –1 dBFS; SFDR is ratio of converter full scale to worst spur. 10Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst 3rd order intermod product. f1 = 17.0 MHz – 100 kHz, f 2 = 18.0 MHz – 100 kHz. 11Channel-to-channel isolation tested with A channel/50 ohm terminated <A IN2 grounded, and a full-scale signal applied to B channel (A IN1). All specifications guaranteed within 100 ms of initial power up regardless of sequencing. Specifications subject to change without notice. AD10265 –3–REV. 0

–4– REV. 0 ABSOLUTE MAXIMUM RATINGS 1 Parameter Min Max Units ELECTRICAL VCC Voltage 0 7 V VEE Voltage –7 0 V Analog Input Voltage V EE VCC V Analog Input Current –10 +10 mA Digital Input Voltage (ENCODE) 0 AV CC V ENCODE, ENCODE Differential Voltage 4 V Digital Output Current –10 +10 mA ENVIRONMENTAL2 Operating Temperature (Case) –55 +125 °C Maximum Junction Temperature +175 °C Lead Temperature (Soldering, 10 sec) +300 °C Storage Temperature Range (Ambient) –65 +150 °C NOTES 1Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2Typical thermal impedances for “Z” package: qJC = 11°C/W; qJA = 30°C/W. Table I. Output Coding MSB LSB Base 10 Input 0111111111111 2047 +FS 0000000000001 +1 0000000000000 0 0.0 V 1111111111111 –1 1000000000000 2048 –FS EXPLANATION OF TEST LEVELS Test Level I – 100% Production Tested. II – 100% production tested at +25 °C, and sample tested at specified temperatures. AC testing done on sample basis. III – Sample Tested Only. IV – Parameter is guaranteed by design and characterization testing. V – Parameter is a typical value only. VI – All devices are 100% production tested at +25 °C; sample tested at temperature extremes. ORDERING GUIDE Model Temperature Range Package Description Package Option AD10265AZ –25 °C to +85°C (Case) 68-Lead Leaded Ceramic Chip Carrier Z-68A AD10265/PCB +25 °C Evaluation Board with AD10265AZ CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD10265 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

–5–REV. 0 PIN FUNCTION DESCRIPTIONS Pin No. Name Function 1 SHIELD Internal Ground Shield between channels. 2, 5, 9–11, 26, 27 GNDA A Channel Ground. A and B grounds should be connected as close to the device as possible. 3, 4, 12, 15, 16, NC No Connect. Pins 15 and 17 are internal test pins: it is recommended to connect them to 34, 35, 55–57 GND 6A INA1 Analog Input for A side ADC (nominally – 0.5 V). 7A INA2 Analog Input for A side ADC (nominally – 1.0 V). 8A INA3 Analog Input for A side ADC (nominally – 2.0 V). 13 AV EE Analog Negative Supply Voltage (nominally –5.0 V). For A side ADC. 14 AV CC Analog Positive Supply Voltage (nominally +5.0 V). For A side ADC. 17–25, 31–33 D0A–D11A Digital Outputs for ADC A. D0 (LSB). 28 ENCODEA ENCODE is complement of ENCODE. 29 ENCODEA Data conversion initiated on rising edge of ENCODE input. 30 DV CC Digital positive supply voltage (nominally +3.3 V) for A side ADC. 36–42, 45–49 D0B–D11B Digital Outputs for ADC B. D0 (LSB). 43, 44, 53, 54, GNDB B Channel Ground. A and B grounds should be connected as close to the device 58–61, 65, 68 as possible. 50 DV CC Digital Positive Supply Voltage (nominally +3.3 V) for B side ADC. 51 ENCODEB Data conversion initiated on rising edge of ENCODE input. 52 ENCODEB ENCODE is complement of ENCODE. 62 A INB1 Analog Input for B side ADC (nominally – 0.5 V). 63 A INB2 Analog Input for B side ADC (nominally – 1.0 V). 64 A INB3 Analog Input for B side ADC (nominally – 2.0 V). 66 AV CC Analog Positive Supply Voltage (nominally +5.0 V). For B side ADC. 67 AV EE Analog Negative Supply Voltage (nominally –5.0 V). For B side ADC. PIN CONFIGURATION 68-Lead Leaded Ceramic Chip Carrier 27 4328 29 30 31 32 33 34 35 36 37 38 39 40 41 42 96 18 7 6 5 68 67 66 65 64 63 624321 TOP VIEW (Not to Scale) GNDB GNDB GNDB NC NC NC GNDB GNDB ENCODEB ENCODEB DV CC D11B (MSB) D10B D9B D8B D7B GNDB GNDA DV CC D9A D10A (MSB) D11A ENCODEA ENCODEA NC NC D1B D2B D3B D4B D5B D6B GNDB (LSB) D0B GNDA GNDA NC AV EE AV CC NC NC (LSB) D0A D1A D2A D3A D4A D5A D6A D7A D8A GNDA NC = NO CONNECT GNDA GNDB GNDA A INA1 GNDA NC NC AV EE A INB3 AV CC GNDB A INA3 A INA2 GNDB A INB1 A INB2 SHIELD AD10265 PIN 1

–6– REV. 0 Output Propagation Delay The delay between the 50% point of the rising edge of ENCODE command and the time when all output data bits are within valid logic levels. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral compo- nents, including harmonics but excluding dc. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc. Spurious-Free Dynamic Range The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious compo- nent may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal levels is lowered) or in dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious compo- nent may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal levels is lowered) or in dBFS (always related back to converter full scale). DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Nonlinearity The deviation of any code from an ideal 1 LSB step. Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the ENCODE pulse should be left in logic “1” state to achieve rated performance; pulse width low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable Encode duty cycle. Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the worst harmonic component. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” de- termined by a least square curve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed.

80 SFDR – dBc

Figure 12. SNR/Harmonics to A IN > Nyquist MSPS Figure 13. Gain Flatness vs. Input Frequency

Figure 21. Evaluation Board Schematic

Figure 22. Evaluation Board Mechanical Layout Power to the analog supply pins is connected via banana jacks. tions assistance is required.

Figure 23. Top Layer

Figure 24. Bottom Layer

Figure 25. Power Plane Layer

Figure 26. Ground Plane Layer

–18– REV. 0 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 68-Lead Leaded Ceramic Chip Carrier (Z-68A) 0.060 (1.52) 0.240 (6.096) TOP VIEW (PINS DOWN) PIN 1 96 1 4327 0.050 (1.27) 0.950 (24.13) SQ 0.018 (0.457) 0.800 (20.32) 1.180 (29.97) SQ