AD10242BZ

AD10242 AD | Alldatasheet

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REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. AD10242

FEATURES

Two Matched ADCs with Input Signal Conditioning Selectable Bipolar Input Voltage Range Full MIL-STD-883B Compliant 80 dB Spurious-Free Dynamic Range Trimmed Channel-Channel Matching

APPLICATIONS

Any I/Q Signal Processing Application The AD10242 operates with ± 5.0 V for the analog signal condi- tioning with a separate +5.0 V supply for the analog-to-digital conversion. Each channel is completely independent allowing operation with independent encode or analog inputs. The AD10242 also offers the user a choice of analog input signal ranges to minimize additional signal conditioning required for multiple functions within a single system. The heart of the AD10242 is the AD9042 which is designed specifically for appli- cations requiring wide dynamic range. The AD10242 is manufactured by Analog Devices on our MIL-PRF-38534 MCM line and is completely qualified. Units are packaged in a custom cofired ceramic 68-lead gull wing package and specified for operation from –55 °C to +125°C. Contact the factory for additional custom options including those which allow the user to ac couple the ADC directly, by- passing the front end amplifier section. Also see the AD9042 data sheet for additional details on ADC performance. PRODUCT HIGHLIGHTS 1. Guaranteed sample rate of 40 MSPS. 2. Dynamic performance specified over entire Nyquist band; spurious signals @ 80 dBc for –1 dBFS input signals. 3. Low power dissipation: <2 W off ± 5.0 V supplies. 4. User defined input amplitude. 5. Packaged in 68-lead ceramic leaded chip carrier. PRODUCT DESCRIPTION The AD10242 is a complete dual signal chain solution including onboard amplifiers, references, ADCs, and output buffering pro- viding unsurpassed total system performance. Each channel is laser trimmed for gain and offset matching and provides channel- to-channel crosstalk performance better than 80 dB. The AD10242 utilizes two each of the AD9631, OP279, and the AD9042 in a custom MCM to gain space, performance, and cost advantages over solutions previously available. FUNCTIONAL BLOCK DIAGRAM OP279 OP279 AD9042 AD9631 TIMING A IN3 A IN2A IN1 D11B (MSB) D10B D9B D8B D7B D0B (LSB) D1B D2B D3B D4B D5B D6BD9A D10A D11A (MSB) (LSB) D0A D1A D2A D3A D4A D5A D6A D7A D8A ENC ENC AD10242 VREF OUTPUT BUFFERING UNEG UCOM UPOS OP279 OP279 AD9042 AD9631 TIMING A IN2 A IN1 VREF OUTPUT BUFFERING A IN3UPOSUNEG UCOM ENC ENC 68 7 626356 55 6457 28 29 31 32 33 36 40 41 423837 39 Dual, 12-Bit, 40 MSPS MCM A/D Converter with Analog Input Signal Conditioninga Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997

REV. A–2– AD10242–SPECIFICATIONS Electrical Characteristics (AVCC = +5 V; AVEE = –5.0 V; DV CC = +5 V; applies to each ADC unless otherwise noted) Test Mil AD10242BZ/TZ Parameter Temp Level Subgroup Min Typ Max Units RESOLUTION 12 Bits DC ACCURACY No Missing Codes Full VI 1, 2, 3 Guaranteed Offset Error +25 °C I 1 –0.5 ± 0.05 +0.5 % FS Full VI 2, 3 –2.0 ± 1.0 +2.0 % FS Offset Error Channel Match Full V ± 0.1 % Gain Error Full VI 2, 3 –1.5 ± 0.8 +1.5 % FS Gain Error Channel Match Full V ± 0.1 % ANALOG INPUT (A IN) Input Voltage Range AIN1 Full I ± 0.5 V AIN2 Full I ± 1.0 V AIN3 Full I ± 2V Input Resistance AIN1 Full IV 12 99 100 101 Ω AIN2 Full IV 12 198 200 202 Ω AIN3 Full IV 12 396 400 404 Ω Input Capacitance 2 +25°C IV 12 0 4.0 7.0 pF Analog Input Bandwidth 3 Full V 60 MHz ENCODE INPUT4, 5 Logic Compatibility TTL/CMOS Logic “1” Voltage Full I 1, 2, 3 2.0 5.0 V Logic “0” Voltage Full I 1, 2, 3 0 0.8 V Logic “1” Current (V INH = 5 V) Full I 1, 2, 3 625 800 µA Logic “0” Current (VINL = 0 V) Full I 1, 2, 3 –400 –300 µA Input Capacitance +25 °C V 12 7.0 pF SWITCHING PERFORMANCE Maximum Conversion Rate 6 Full VI 4, 5, 6 40 50 MSPS Minimum Conversion Rate 6 Full V 12 5 MSPS Aperture Delay (t A) +25 °C V 1.0 ns Aperture Delay Matching +25 °CV ± 2.0 ns Aperture Uncertainty (Jitter) +25 °C V 1 ps rms ENCODE Pulse Width High +25 °CI V 1 2 1 2 1 0 n s ENCODE Pulse Width Low +25 °CI V 1 2 1 0 4 1 n s Output Delay (t OD) Full IV 12 10 12 14 ns SNR7 Analog Input @ 1.2 MHz +25 °CV 6 8 d B @ 4.85 MHz +25 °CI 4 6 3 6 6 d B Full II 5, 6 62 66 dB @ 9.9 MHz +25 °CI 4 6 3 6 5 d B Full II 5, 6 62 65 dB @ 19.5 MHz +25 °CI 4 6 0 6 3 d B Full II 5, 6 59 62 dB SINAD8 Analog Input @ 1.2 MHz +25 °CV 6 7 d B @ 4.85 MHz +25 °CI 4 6 2 6 5 d B Full II 5, 6 61 64 dB @ 9.9 MHz +25 °CI 4 6 0 6 4 d B Full II 5, 6 60 63 dB @ 19.5 MHz +25 °CI 4 5 8 6 1 d B Full II 5, 6 58 60 dB

Parameter Temp Level Subgroup Min Typ Max Units SPURIOUS-FREE DYNAMIC RANGE 9 Analog Input @ 1.2 MHz +25 °C I 81 dBFS @ 4.85 MHz +25 °C I 4 70 80 dBFS Full II 5, 6 70 79 dBFS @ 9.9 MHz +25 °C I 4 63 70 dBFS Full II 5, 6 63 69 dBFS @ 19.5 MHz +25 °C I 4 60 67 dBFS Full II 5, 6 60 66 dBFS TWO-TONE IMD REJECTION 10 F1, F2 @ –7 dBFS Full II 4, 5, 6 70 76 dBc CHANNEL-TO-CHANNEL ISOLATION11 +25°CI V 1 2 7 5 8 0 d B TRANSIENT RESPONSE +25 °CV 1 0 n s LINEARITY Differential Nonlinearity +25 °C IV 12 0.3 1.0 LSB (Encode = 20 MHz) Full IV 12 0.5 1.25 LSB Integral Nonlinearity +25 °C V 0.3 LSB (Encode = 20 MHz) Full V 0.5 LSB OVERVOLTAGE RECOVERY TIME 12 VIN = 2.0 × FS Full IV 12 50 100 ns VIN = 4.0 × FS Full IV 12 75 200 ns DIGITAL OUTPUTS Logic Compatibility CMOS Logic “1” Voltage13 Full I 1, 2, 3 3.5 4.2 V Logic “0” Voltage14 Full I 1, 2, 3 0.45 0.65 V Output Coding Twos Complement POWER SUPPLY AVCC Supply Voltage Full VI +5.0 V I (AVCC) Current Full V 260 mA AVEE Supply Voltage Full VI –5.0 V I (AVEE) Current Full V 55 mA DVCC Supply Voltage Full VI +5.0 V I (DVCC) Current Full V 25 mA ICC (Total) Supply Current Full I 1, 2, 3 350 400 mA Power Dissipation (Total) Full I 1, 2, 3 1.75 2.0 W Power Supply Rejection Ratio (PSRR) Full I 7, 8 0.01 0.02 % FSR/% V S Pass Band Ripple to 10 MHz Full IV 12 0.2 dB NOTES 1 Gain tests are performed on A IN3 over specified input voltage range. 2 Input capacitance specifications combines AD9631 die capacitance + ceramic package capacitance. 3 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4 ENCODE (Pin 4) driven by single-ended source; ENCODE (Pin 5) bypassed to ground through 0.01 µF capacitor. 5 ENCODE (Pin 4) may also be driven differentially in conjunction with ENCODE (Pin 5); see “Encoding the AD10242” for details. 6 Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%. 7 Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonic s removed). Encode = 40.0 MSPS. 8 Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harm onics. Encode = 40.0 MSPS. 9 Analog Input signal equal –1 dBFS; SFDR is ratio of converter full scale to worst spur. 10 Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the rati o of either tone to the worst 3rd order intermod product. f1 = 10.0 MHz ± 100 kHz, 50 kHz ≤ f1 – f2 ≤ 300 kHz. 11 Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel (AIN1). 12 Input driven to 2 × and 4× AIN1 range for >4 clock cycles. Output recovers inband in specified time with Encode = 40 MSPS. No foldover guaranteed. 13 Outputs are sourcing 10 µA. 14 Outputs are sinking 10 µA. All specifications guaranteed within 100 ms of initial power up regardless of sequencing. Specifications subject to change without notice. AD10242 –3–REV. A

–4– REV. A ABSOLUTE MAXIMUM RATINGS 1 Parameter Min Max Units ELECTRICAL VCC Voltage 0 7 V VEE Voltage –7 0 V Analog Input Voltage V EE VCC V Analog Input Current –10 +10 mA Digital Input Voltage (ENCODE) 0 V CC V ENCODE, ENCODE Differential Voltage 4 V Digital Output Current –40 +40 mA ENVIRONMENTAL2 Operating Temperature (Case) –55 +125 °C Maximum Junction Temperature +175 °C Lead Temperature (Soldering, 10 sec) +300 °C Storage Temperature Range (Ambient) –65 +150 °C NOTES 1Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedances for “Z” package: θJC = 11oC/W; θJA = 30oC/W. Table I. Output Coding MSB LSB Base 10 Input 0111111111111 2047 +FS 0000000000001 +1 0000000000000 0 0.0 V 1111111111111 –1 1000000000000 2048 –FS EXPLANATION OF TEST LEVELS Test Level I – 100% Production Tested. II – 100% production tested at +25 °C, and sample tested at specified temperatures. AC testing done on sample basis. III – Sample Tested Only. IV – Parameter is guaranteed by design and characterization testing. V – Parameter is a typical value only. VI – All devices are 100% production tested at +25 °C; sample tested at temperature extremes. ORDERING GUIDE Model Temperature Range Package Description Package Option AD10242BZ –40 °C to +85°C (Case) 68-Pin Ceramic Leaded Chip Carrier Z-68A AD10242TZ –55 °C to +125°C (Case) 68-Pin Ceramic Leaded Chip Carrier Z-68A AD10242TZ/883B –55 °C to +125°C (Case) 68-Pin Ceramic Leaded Chip Carrier Z-68A 5962-9581501HXA –55 °C to +125°C (Case) 68-Pin Ceramic Leaded Chip Carrier Z-68A AD10242/PCB +25 °C Evaluation Board with AD10242BZ WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD10242 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–5–REV. A PIN FUNCTION DESCRIPTIONS Pin No. Name Function 1 SHIELD Internal Ground Shield between channels. 2, 5, 9–11, 26–27 GNDA A Channel Ground. A and B grounds should be connected as close to the device as possible. 3 UNEGA Unipolar Negative. 4 UCOMA Unipolar Common. INA1 Analog Input for A side ADC (nominally ± 0.5 V). 7A INA2 Analog Input for A side ADC (nominally ± 1.0 V). 8A INA3 Analog Input for A side ADC (nominally ± 2.0 V). 12 UPOSA Unipolar Positive. 13 AV EE Analog Negative Supply Voltage (nominally –5.0 V or –5.2 V). 14 AV CC Analog Positive Supply Voltage (nominally +5.0 V). 15–16 NC No Connect. 17–25, 31–33 D0A–D11A Digital Outputs for ADC A. D0 (LSB). ENCODEA ENCODE is complement of ENCODE. 29 ENCODEA Data conversion initiated on rising edge of ENCODE input. 30 DV CC Digital positive supply voltage (nominally +5.0 V). 34–35 NC No Connect. 36–42, 45–49 D0B–D11B Digital Outputs for ADC B. D0 (LSB). 43–44, 53–54 GNDB B Channel Ground. A and B grounds should be connected as close to the device 58–61, 65, 68 as possible. 50 DV CC Digital Positive Supply Voltage (nominally +5.0 V). 51 ENCODEB Data conversion initiated on rising edge of ENCODE input. 52 ENCODEB ENCODE is complement of ENCODE. 55 UCOMB Unipolar Common. 56 UNEGB Unipolar Negative. 57 UPOSB Unipolar Positive. 62 A INB1 Analog Input for B side ADC (nominally ± 0.5 V). 63 A INB2 Analog Input for B side ADC (nominally ± 1.0 V). 64 A INB3 Analog Input for B side ADC (nominally ± 2.0 V). 66 AV CC Analog Positive Supply Voltage (nominally +5.0 V). 67 AV EE Analog Negative Supply Voltage (nominally –5.0 V or –5.2 V). PIN CONFIGURATION 68-Lead Ceramic Leaded Chip Carrier 27 4328 29 30 31 32 33 34 35 36 37 38 39 40 41 42 96 18 7 6 5 68 67 66 65 64 63 624 321 TOP VIEW (Not to Scale) GNDB GNDB GNDB UPOSB UNEGB UCOMB GNDB GNDB ENCODEB ENCODEB DV CC D11B (MSB) D10B D9B D8B D7B GNDB GNDA DV CC D9A D10A (MSB) D11A ENCODEA ENCODEA NC NC D1B D2B D3B D4B D5B D6B GNDB (LSB) D0B GNDA GNDA UPOSA AV EE AV CC NC NC (LSB) D0A D1A D2A D3A D4A D5A D6A D7A D8A GNDA NC = NO CONNECT GNDA GNDB GNDA A INA1 GNDA UCOMA UNEGA AV EE A INB3 AV CC GNDB A INA3 A INA2 GNDB A INB1 A INB2 SHIELD AD10242 PIN 1

–6– REV. A Overvoltage Recovery Time The amount of time required for the converter to recover to 0.02% accuracy after an analog input signal of the specified per- centage of full scale is reduced to midscale. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral compo- nents, including harmonics but excluding dc. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc. Spurious-Free Dynamic Range The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious compo- nent may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal levels is lowered) or in dBFS (always re- lated back to converter full scale). Transient Response The time required for the converter to achieve 0.02% accuracy when a one-half full-scale step function is applied to the analog input. Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious compo- nent may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal levels is lowered) or in dBFS (always related back to converter full scale). DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Nonlinearity The deviation of any code from an ideal 1 LSB step. Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the ENCODE pulse should be left in logic “1” state to achieve rated performance; pulse width low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable Encode duty cycle. Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the worst harmonic component. Integral Nonlinearity The deviation of the transfer function from a reference line mea- sured in fractions of 1 LSB using a “best straight line” deter- mined by a least square curve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between the 50% point of the rising edge of ENCODE command and the time when all output data bits are within valid logic levels.

Figure 29. Evaluation Board Schematic

8 H2DM

A SIDE + CONNECT 2.43kΩ RES. FROM TP1 TO TP5. A SIDE – CONNECT 2.67kΩ RES. FROM TP5 TO TP6. B SIDE + CONNECT 2.43kΩ RES. FROM TP2 TO TP4. B SIDE – CONNECT 2.67kΩ RES. FROM TP4 TO TP3. IS A 51Ω RESISTOR BETWEEN J15 & J16. J15 & J16. CONNECT JUMPERS J17 & J18. (THE DIGITAL INTERFACES). TO POWER THE EVAL. FROM E1 TO E4 (CONNECTED AT FACTORY).

Care should be taken when placing the digital output runs. capacitive loading on the digital outputs should be minimized. Power to the analog supply pins is connected via banana jacks. factory if additional layout or applications assistance is required. Figure 30. Evaluation Board Mechanical Layout

–15–REV. A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 68-Lead Ceramic Leaded Chip Carrier (Z-68A) 0.950 (24.13) SQ 0.060 (1.52) 0.240 (6.096) TOP VIEW (PINS DOWN) PIN 1 96 1 4327 0.800 (20.32) 1.180 (29.97) SQ

C2161a–4–3/97PRINTED IN U.S.A. –16–