AD10242

AD10242 (Rv. D)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 15

Technical content

FEATURES

2 Matched ADCs with Input Signal Conditioning

Selectable Bipolar Input Voltage Range (/H115500.5 V, /H115501.0 V, /H115502.0 V) Full MIL-STD-883B Compliant 80 dB Spurious-Free Dynamic Range Trimmed Channel-Channel Matching

APPLICATIONS

Any I/Q Signal Processing Application The AD10242 operates with ± 5.0 V for the analog signal condi- tioning with a separate 5.0 V supply for the analog-to-digital conversion. Each channel is completely independent, allowing operation with independent encode or analog inputs. The AD10242 also offers the user a choice of analog input signal ranges to mini- mize additional signal conditioning required for multiple functions within a single system. The heart of the AD10242 is the AD9042, which is designed s pecifically for applications requiring wide dynamic range. The AD10242 is manufactured on Analog Devices’ MIL-PRF-38534 MCM line and is completely qualified. Units are packaged in a custom, cofired, ceramic 68-lead gull wing package and specified for operation from –55 °C to +125 °C. Contact the factory for additional custom options including those that allow the user to ac couple the ADC directly, bypassing the front end amplifier section. Also see the AD9042 data sheet for additional details on ADC performance. PRODUCT HIGHLIGHTS 1. Guaranteed sample rate of 40 MSPS. 2. Dynamic performance specified over entire Nyquist band; spurious signals @ 80 dBc for –1 dBFS input signals. 3. Low power dissipation: <2 W off ±5.0 V supplies. 4. User defined input amplitude. 5. Packaged in 68-lead ceramic leaded chip carrier. GENERAL DESCRIPTION The AD10242 is a complete dual signal chain solution including on-board amplifiers, references, ADCs, and output buffering providing unsurpassed total system performance. Each channel is laser trimmed for gain and offset matching and provides channel- to-channel crosstalk performance better than 80 dB. The AD10242 utilizes two each of the AD9632, OP279, and AD9042 in a cus- tom MCM to gain space, performance, and cost advantages over solutions previously available. FUNCTIONAL BLOCK DIAGRAM OP279 OP279 AD9042 AD9632 TIMING AIN3 AIN2A IN1 D11B (MSB) D10B D9B D8B D7B D0B (LSB) D1B D2B D3B D4B D5B D6BD9A D10A D11A (MSB) (LSB) D0A D1A D2A D3A D4A D5A D6A D7A D8A ENC AD10242 VREF OUTPUT BUFFERING UNEG UCOM UPOS OP279 OP279 AD9042 AD9632 TIMING AIN2 AIN1 VREF OUTPUT BUFFERING AIN3UPOSUNEG UCOM ENC ENC ENC Dual, 12-Bit, 40 MSPS MCM A/D Converter with Analog Input Signal Conditioninga Tel: 781/329-4700 www.analog.com Fax: © Analog Devices, Inc. All rights reserved. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. REV. D 2015 781/461-3113

–2– AD10242–SPECIFICATIONS Electrical Characteristics (AVCC = +5 V; AVEE = –5.0 V; DV CC = +5 V; applies to each ADC, unless otherwise noted.) Test Mil AD10242BZ/TZ Parameter Temp Level Subgroup Min Typ Max Unit RESOLUTION 12 Bits DC ACCURACY No Missing Codes Full VI 1, 2, 3 Guaranteed Offset Error 25°CI 1 –0.5 ± 0.05 +0.5 % FS Full VI 2, 3 –2.0 ± 1.0 +2.0 % FS Offset Error Channel Match Full V ± 0.1 % Gain Error1 25°CI 1 –1.0 ± 0.5 +1.0 % FS Full VI 2, 3 –1.5 ± 0.8 +1.5 % FS Gain Error Channel Match Full V ± 0.1 % ANALOG INPUT (A IN) Input Voltage Range AIN1 Full I ± 0.5 V AIN2 Full I ± 1.0 V AIN3 Full I ± 2V Input Resistance AIN1 Full IV 12 99 100 101 Ω AIN2 Full IV 12 198 200 202 Ω AIN3 Full IV 12 396 400 404 Ω Input Capacitance 2 25°CI V 1 2 0 4.0 7.0 pF Analog Input Bandwidth 3 Full V 60 MHz ENCODE INPUT4, 5 Logic Compatibility TTL/CMOS Logic “1” Voltage Full I 1, 2, 3 2.0 5.0 V Logic “0” Voltage Full I 1, 2, 3 0 0.8 V Logic “1” Current (V INH = 5 V) Full I 1, 2, 3 625 800 µA Logic “0” Current (V INL = 0 V) Full I 1, 2, 3 –400 –300 µA Input Capacitance 25°CV 1 2 7.0 pF SWITCHING PERFORMANCE Maximum Conversion Rate 6 Full VI 4, 5, 6 40 50 MSPS Minimum Conversion Rate 6 Full V 12 5 MSPS Aperture Delay (t A)2 5°CV 1.0 ns Aperture Delay Matching 25°CV ± 2.0 ns Aperture Uncertainty (Jitter) 25°CV 1 ps rms ENCODE Pulsewidth High 25°CI V 1 2 1 2 1 0 n s ENCODE Pulsewidth Low 25°CI V 1 2 1 0 4 1n s Output Delay (t OD) Full IV 12 10 12 14 ns SNR7 Analog Input @ 1.2 MHz 25°CV 6 8 d B @ 4.85 MHz 25°CI 4 6 3 6 6 d B Full II 5, 6 62 66 dB @ 9.9 MHz 25°CI 4 6 3 6 5 d B Full II 5, 6 62 65 dB @ 19.5 MHz 25°CI 4 6 0 6 3 d B Full II 5, 6 59 62 dB SINAD8 Analog Input @ 1.2 MHz 25°CV 6 7 d B @ 4.85 MHz 25°CI 4 6 2 6 5 d B Full II 5, 6 61 64 dB @ 9.9 MHz 25°CI 4 6 0 6 4 d B Full II 5, 6 60 63 dB @ 19.5 MHz 25°CI 4 5 8 6 1 d B Full II 5, 6 58 60 dB REV. D

Parameter Temp Level Subgroup Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE 9 Analog Input @ 1.2 MHz 25°CI 81 dBFS @ 4.85 MHz 25°CI 47 08 0 dBFS Full II 5, 6 70 79 dBFS @ 9.9 MHz 25°CI 46 37 0 dBFS Full II 5, 6 63 69 dBFS @ 19.5 MHz 25°CI 46 06 7 dBFS Full II 5, 6 60 66 dBFS TWO-TONE IMD REJECTION 10 F1, F2 @ –7 dBFS Full II 4, 5, 6 70 76 dBc CHANNEL-TO-CHANNEL ISOLATION11 25°CI V 1 2 7 58 0 d B TRANSIENT RESPONSE 25°CV 1 0 n s LINEARITY Differential Nonlinearity 25°CI V 1 2 0.3 1.0 LSB (Encode = 20 MHz) Full IV 12 0.5 1.25 LSB Integral Nonlinearity 25°CV 0.3 LSB (Encode = 20 MHz) Full V 0.5 LSB OVERVOLTAGE RECOVERY TIME 12 VIN = 2.0 × FS Full IV 12 50 100 ns VIN = 4.0 × FS Full IV 12 75 200 ns DIGITAL OUTPUTS Logic Compatibility CMOS Logic “1” Voltage 13 Full I 1, 2, 3 3.5 4.2 V Logic “0” Voltage 14 Full I 1, 2, 3 0.45 0.65 V Output Coding Twos Complement POWER SUPPLY AVCC Supply Voltage Full VI 5.0 V I (AVCC) Current Full V 260 mA AVEE Supply Voltage Full VI –5.0 V I (AVEE) Current Full V 55 mA DVCC Supply Voltage Full VI 5.0 V I (DVCC) Current Full V 25 mA ICC (Total) Supply Current Full I 1, 2, 3 350 400 mA Power Dissipation (Total) Full I 1, 2, 3 1.75 2.0 W Power Supply Rejection Ratio (PSRR) Full I 7, 8 0.01 0.02 % FSR/% V S Pass-Band Ripple to 10 MHz Full IV 12 0.2 dB NOTES 1Gain tests are performed on A IN3 over specified input voltage range. 2Input capacitance specifications combine AD9632 die capacitance and ceramic package capacitance. 3Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 µF capacitor. 5ENCODE may also be driven differentially in conjunction with ENCODE; see Encoding the AD10242 section for details. 6Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%. 7Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 40.0 MSPS. 8Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 40.0 MSPS. 9Analog Input signal equals –1 dBFS; SFDR is the ratio of converter full scale to worst spur. 10Both input tones at –7 dBFS; two-tone intermodulation distor tion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 = 10.0 MHz ± 100 kHz, 50 kHz ≤ f1 – f2 ≤ 300 kHz. 11Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel (A IN1). 12Input driven to 2 × and 4× AIN1 range for >4 clock cycles. Output recovers in band in specified time with Encode = 40 MSPS. No foldover guaranteed. 13Outputs are sourcing 10 µA. 14Outputs are sinking 10 µA. All specifications guaranteed within 100 ms of initial power-up regardless of sequencing. Specifications subject to change without notice. AD10242 –3– REV. D

–4– ABSOLUTE MAXIMUM RATINGS 1 Parameter Min Max Unit ELECTRICAL VCC Voltage 0 7 V VEE Voltage –7 0 V Analog Input Voltage VEE VCC V Analog Input Current –10 +10 mA Digital Input Voltage (ENCODE) 0 V CC V ENCODE, ENCODE Differential Voltage 4 V Digital Output Current –40 +40 mA ENVIRONMENTAL2 Operating Temperature (Case) –55 +125 °C Maximum Junction Temperature 175 °C Lead Temperature (Soldering, 10 sec) 300 °C Storage Temperature Range (Ambient) –65 +150 °C NOTES 1Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2Typical thermal impedances for ES-68-1 package: θJC = 11°C/W; θJA = 30°C/W. Table I. Output Coding MSB LSB Base 10 Input 0111111111111 2047 +FS 0000000000001 +1 0000000000000 0 0.0 V 1111111111111 –1, 4095 1000000000000 –2047, 2048 –FS EXPLANATION OF TEST LEVELS Test Level I– 100% Production Tested. II – 100% production tested at 25 °C, and sample tested at specified temperatures. AC testing done on sample basis. III – Sample Tested Only. IV – Parameter is guaranteed by design and characterization testing. V– Parameter is a typical value only. VI – All devices are 100% production tested at 25 °C; sample tested at temperature extremes. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD10242 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. D

–5– 27 4328 29 30 31 32 33 34 35 36 37 38 39 40 41 42 96 18765 6 7 6 6 65 64 63 624321 6 8 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) NC = NO CONNECT AD10242 GNDA GNDA UPOSA AVEE AVCC NC NC (LSB) D0A D1A D2A D3A D4A D5A D6A D7A D8A GNDA GNDA ENCODEA ENCODEA DVCC D9A D10A (MSB) D11A NC NC (LSB) D0B D1B D2B D3B D4B D5B D6B GNDB GNDB GNDB GNDB UPOSB UNEGB UCOMB GNDB GNDB ENCODEB ENCODEB DVCC D11B (MSB) D10B D9B D8B D7B GNDB GNDA AINA3 AINA2 AINA1 GNDA UCOMA UNEGA GNDA SHIELD GNDB AV EE AVCC GNDB A INB3 AINB2 AINB1 GNDB PIN CONFIGURATION 68-Lead Ceramic Leaded Chip Carrier PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 SHIELD Internal Ground Shield between Channels. 2, 5, 9–11, 26–27 GNDA A Channel Ground. A and B grounds should be connected as close to the device as possible. 3 UNEGA Unipolar Negative. 4 UCOMA Unipolar Common. 6A INA1 Analog Input for A Side ADC (Nominally ±0.5 V). 7A INA2 Analog Input for A Side ADC (Nominally ±1.0 V). 8A INA3 Analog Input for A Side ADC (Nominally ±2.0 V). 12 UPOSA Unipolar Positive. 13 AVEE Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V). 14 AV CC Analog Positive Supply Voltage (Nominally 5.0 V). 15, 16, 34, 35 NC No Connect. 17–25, 31–33 D0A–D11A Digital Outputs for ADC A. (D0 LSB.) 28 ENCODEA ENCODE is the complement of ENCODE. 29 ENCODEA Data conversion is initiated on the rising edge of the ENCODE input. 30, 50 DV CC Digital Positive Supply Voltage (Nominally 5.0 V). 36–42, 45–49 D0B–D11B Digital Outputs for ADC B. (D0 LSB.) 43–44, 53–54, GNDB B Channel Ground. A and B grounds should be connected as close to the device 58–61, 65, 68 as possible. 51 ENCODEB Data conversion is initiated on the rising edge of the ENCODE input. 52 ENCODEB ENCODE is the complement of ENCODE. 55 UCOMB Unipolar Common. 56 UNEGB Unipolar Negative. 57 UPOSB Unipolar Positive. 62 A INB1 Analog Input for B Side ADC (Nominally ±0.5 V). 63 AINB2 Analog Input for B Side ADC (Nominally ±1.0 V). 64 AINB3 Analog Input for B Side ADC (Nominally ±2.0 V). 66 AVCC Analog Positive Supply Voltage (Nominally 5.0 V). 67 AVEE Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V). REV. D

–6– Overvoltage Recovery Time The amount of time required for the converter to recover to 0.02% accuracy after an analog input signal of the specified percentage of full scale is reduced to midscale. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral compo- nents, including harmonics but excluding dc. Signal-to-Noise Ratio (SNR, without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious compo- nent may or may not be a harmonic. SFDR may be reported in dBc (i.e., degrades as signal levels are lowered) or in dBFS (always r elated back to converter full scale). Transient Response The time required for the converter to achieve 0.02% accu- racy when a one-half full-scale step function is applied to the analog input. Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Two-tone SFDR may be reported in dBc (i.e., degrades as signal levels are lowered) or in dBFS (always related back to converter full scale). DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Nonlinearity The deviation of any code from an ideal 1 LSB step. Encode Pulsewidth/Duty Cycle Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic “1” state to achieve rated performance; pulsewidth low is the minimum time that the ENCODE pulse should be left in low state. At a given clock rate, these specifications define an acceptable encode duty cycle. Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the worst harmonic component. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” deter- mined by a least square curve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between the 50% point of the rising edge of the ENCODE command and the time when all output data bits are within valid logic levels. REV. D

–8– AD10242–Typical Performance Characteristics FREQUENCY – MHz POWER RELATIVE TO FULL SCALE – dB –60 –100 02 0 2468 1 0 1 2 1 4 1 6 1 8 –10 –50 –70 –90 –30 –40 –80 –20 ENCODE = 40MSPS AIN = 4.85MHz AIN = –1dBFS SNR = 66.4dB SFDR = 72.8dBc TPC 1. Single Tone @ 4.85 MHz FREQUENCY – MHz –60 –100 0 202468 1 0 1 2 1 4 1 6 1 8 –10 –50 –70 –90 –30 –40 –80 –20 ENCODE = 40MSPS AIN = 9.9MHz AIN = –1dBFS SNR = 66.0dB SFDR = 65.7dBc POWER RELATIVE TO FULL SCALE – dB TPC 2. Single Tone @ 9.9 MHz FREQUENCY – MHz POWER RELATIVE TO FULL SCALE – dB –60 –100 0 202468 1 0 1 2 1 4 1 6 1 8 –10 –50 –70 –90 –30 –40 –80 –20 ENCODE = 40MSPS AIN = 19.5MHz AIN = –1dBFS SNR = 64.3dB SFDR = 63.3dBc TPC 3. Single Tone @ 19.5 MHz FREQUENCY – MHz POWER RELATIVE TO FULL SCALE – dB –60 –100 02 0 246 8 1 0 1 21 41 61 8 –10 –50 –70 –90 –30 –40 –80 –20 ENCODE = 40MSPS AIN1 = 9.8MHz AIN1 = –7dBFS AIN2 = 10.1MHz AIN2 = –7dBFS SFDR = 76.0dBc TPC 4. Two-Tone FFT @ 9.8 MHz/10.1 MHz FREQUENCY – MHz POWER RELATIVE TO FULL SCALE – dB –60 –100 02 0 2468 1 0 1 2 1 4 1 6 1 8 –10 –50 –70 –90 –30 –40 –80 –20 ENCODE = 40MSPS AIN1 = 19.5MHz AIN1 = –7dBFS AIN2 = 19.7MHz AIN2 = –7dBFS SFDR = 70.6dBc TPC 5. Two-Tone FFT @ 19.5 MHz/19.7 MHz ANALOG INPUT FREQUENCY – MHz 52 0 10 ENCODE = 40MSPS AIN = –1dBFS T = +125 C T = +25 C T = –55 C WORST-CASE HARMONIC – dB TPC 6. Harmonics vs. A IN REV. D

–9– ANALOG INPUT FREQUENCY – MHz 64.0 61.5 52 0 10 67.0 64.5 63.0 66.0 65.0 62.0 ENCODE = 40MSPS AIN = –1dBFS T = +125 C T = +25 C T = –55 C 62.5 63.5 65.5SNR – dB 66.5 TPC 7. SNR vs. A IN SAMPLE RATE – MSPS 55 0 10 AIN = 9.9MHz AIN = –1dBFS SFDR SNR, WORST SPUR – dB, dBc 15 20 25 30 35 40 45 SNR TPC 8. SNR and Harmonics vs. Encode Rate TEMPERATURE – C –2.0 –55 125 GAIN OFFSET 45 65 85 1055 –15–35 –1.5 –1.0 –0.5 0.5 1.0 1.5 2.0 ERROR – % FS TPC 9. Offset and Gain Error vs. Temperature ANALOG INPUT FREQUENCY – MHz –10 IN A1 25 30 35 402015 –20 –30 –40 –50 –60 –70 –80 –90 ENCODE = 40MSPS AIN = –1dBFS ISOLATION – dB IN B1 IN B3 IN A3 TPC 10. Isolation vs. Frequency ANALOG INPUT POWER LEVEL – dBFS –70 –60 ENCODE = 40MSPS AIN = 9.98MHz SFDR (dBFS) SFDR (dBc) SFDR = 75dB WORST-CASE SPURIOUS – dBc, dBFS TPC 11. Single Tone SFDR (A IN @ 9.98) vs. Power Level ANALOG INPUT POWER LEVEL – dBFS –70 –60 ENCODE = 40MSPS AIN = 19.9MHz SFDR (dBFS) SFDR (dBc) SFDR = 75dB 100WORST-CASE SPURIOUS – dBc, dBFS TPC 12. Single Tone SFDR (A IN @ 19.9) vs. Power Level REV. D

analog-to-digital converter. 0.4 V to the noninverting input of the internal AD9632 amplifier. external gain and level shift circuitry normally requiring trim. the ability of many amplifiers to drive high performance ADCs. matching over an extended temperature range of operation. will limit SNR and overall performance. Figure 6. Single-Ended TTL/CMOS Encode 05085C103MA15, a 0.01 µF capacitor, work well. ment in SFDR over the entire frequency range of the converter. care should be taken to avoid the absolute maximum ratings.

8 H2DM

A SIDE + CONNECT 2.43k/H9024 RES. FROM TP1 TO TP5. A SIDE – CONNECT 2.67k/H9024 RES. FROM TP5 TO TP6. B SIDE + CONNECT 2.43k/H9024 RES. FROM TP2 TO TP4. B SIDE – CONNECT 2.67k/H9024 RES. FROM TP4 TO TP3. IS A 51/H9024 RESISTOR BETWEEN J15 AND J16. J15 AND J16. CONNECT JUMPERS J17 AND J18. CONNECT JUMPERS J17 AND J18. (THE DIGITAL INTERFACES). TO POWER THE EVAL. FROM E1 TO E4 (CONNECTED AT FACTORY). Figure 15. Evaluation Board Schematic

Care should be taken when placing the digital output runs. capacitive loading on the digital outputs should be minimized. Power to the analog supply pins is connected via banana jacks. factory if additional layout or applications assistance is required. Figure 16. Evaluation Board Mechanical Layout

Rev. D | Page 15 OUTLINE DIMENSIONS CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 0.060 (1.52) 0.050 (1.27) 0.040 (1.02) TOE DOWN ANGLE 0–8 DEGREES 0.010 (0.254) 30° 0.050 (1.27) 0.020 (0.508) DETAIL A ROTATED 90° CCW 1.190 (30.23) 1.180 (29.97) SQ 1.170 (29.72) PIN 1 9 61 4327 TOP VIEW (PINS DOWN) 0.800 (20.32) BSC 0.960 (24.38) 0.950 (24.13) SQ 0.940 (23.88) 0.055 (1.40) 0.050 (1.27) 0.045 (1.14) 0.020 (0.508) 0.017 (0.432) 0.014 (0.356) 0.175 (4.45) MAX 0.235 (5.97) MAX DETAIL A 0.010 (0.25) 0.008 (0.20) 0.007 (0.18) 1.070 (27.18) MIN 012908-A Figure 17. 68-Lead Ceramic Leaded Chip Carrier [CLCC]

REVISION HISTORY

6/15—Rev. C to Rev. D 1/03—Rev. B to Rev. C 6/01—Rev. A to Rev. B ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D00665-0-6/15(D)