AD10226

AD10226 Dual-Channel, 12-Bit 125 MSPS IF Sampling A/D Converter data sheet (Rev 0)

Document overview

• Manufacturer or author: Analog Devices
• PDF pages: 20

Technical content

REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD10226 Tel: 781/329-4700www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 Dual-Channel, 12-Bit 125 MSPS IF Sampling A/D Converter FUNCTIONAL BLOCK DIAGRAM D0B (LSB) D1B D2B D3B D4B D5B D6B D7B D8B D9B D10B D11B (MSB) D0A (LSB) D1A D2A D3A D4A D5A D6A D7A D8A D9A D10A D11A (MSB) ADC 50/H9024 AINA2 T1A ADC 50/H9024 AINB2 T1B AD10226 TIMING ENCODEAENCODEA REF REF_A_OUT TIMING ENCODEBENCODEB REF REF_B_OUT OUTPUT RESISTORS T/H T/H AINA1 A INB1 OUTPUT RESISTORS 12 12 DFS_A SFDR_A DFS_B SFDR_B

FEATURES

Two Independent 12-Bit, 125 MSPS ADCs Channel-to-Channel Isolation, > 80 dB AC-Coupled Signal Conditioning Included Gain Flatness up to Nyquist, < 0.1 dB Input VSWR 1.1:1 to Nyquist 80 dB Spurious-Free Dynamic Range Two’s Complement Output Format

3.3 V or 5 V CMOS-Compatible Output Levels

1.5 W Per Channel

Single-Ended or Differential Input

350 MHz Input Bandwidth

APPLICATIONS

Wireless and Wired Broadband Communications Base Stations and “Zero-IF” or Direct IF Sampling Subsystems Wireless Local Loop (WLL) Local Multipoint Distribution Service (LMDS) Radar and Satellite Subsystems PRODUCT DESCRIPTION The AD10226 offers two complete ADC channels with on-module signal conditioning for improved dynamic performance. Each wide dynamic range ADC has a tr ansformer coupled front end optimized for direct-IF samp ling. The AD 10226 has on-chip track-and-hold circuitry and utilizes an innovative architecture to achieve 12-bit, 125 MSPS performance. The AD10226 uses innovative high density circuit design to achieve exceptional performance, while still maintaining excellent isolation and pro- viding for board area savings. The AD10226 operates with 5.0 V analog supply and 3.3 V digital supply. Each channel is completely independent, allowing opera- tion with independent ENCODE and analog inputs. The AD10226 is available in a 35 mm square 385-lead BGA package. PRODUCT HIGHLIGHTS 1. Guaranteed sample rate of 125 MSPS 2. Input signal conditioning included with full-power bandwidth to 350 MHz 3. Industry-leading IF sampling performance

REV. 0–2– AD10226–SPECIFICATIONS ELECTRICAL CHARACTERISTICS1 Test Parameter Temp Level Min Typ Max Unit RESOLUTION 12 Bits DC ACCURACY Differential Nonlinearity 2 Full IV –0.99 ± 0.3 +0.99 LSB Integral Nonlinearity 2 Full IV –1.3 ± 0.75 +1.3 LSB No Missing Codes Full IV Guaranteed Gain Error 3 25°CI – 9 ± 1+ 9 % F S Output Offset 25 °CI –12 +2 +12 LSB Gain Tempco Full V 100 ppm/ °C Offset Tempco Full V –50 ppm/ °C ANALOG INPUT Input Voltage Range 25 °CV 1 . 84 V p-p Input Impedance 25 °CV 5 0 Ω Input VSWR4 Full V 1.1:1 1.25:1 Ratio Analog Input Bandwidth, High Full IV 300 350 MHz Analog Input Bandwidth, Low Full IV 1 MHz ANALOG REFERENCE Output Voltage 25 °CV 2.5 V Load Current 25 °CV 5 m A Tempco Full V ± 80 ppm/ °C SWITCHING PERFORMANCE5 Maximum Conversion Rate Full VI 125 MSPS Minimum Conversion Rate Full IV 10 MSPS Duty Cycle Full IV 45 50 55 % Aperture Delay (t A)2 5 °CV 2.1 ns Aperture Uncertainty (Jitter) 25 °CV 0 . 25 ps rms Output Valid Time (t V)6 Full IV 3.0 4.5 ns Output Propagation Delay (t PD)6 Full IV 4.5 6.0 ns Output Rise Time (t R)2 5 °CV 3.5 ns Output Fall Time (tF)2 5 °CV 3.3 ns DIGITAL INPUTS ENCODE Input Common-Mode Full IV 3.75 V Differential Input (ENC, ENC) Full IV 500 mV Logic “1” Voltage Full IV 2.0 V Logic “0” Voltage Full IV 0.8 V Input Resistance Full IV 3 6 k Ω Input Capacitance 25 °CV 3 p F DIGITAL OUTPUTS Logic “1” Voltage6 Full IV 3.1 3.3 V Logic “0” Voltage6 Full IV 0 0.2 V Output Coding Two’s Complement POWER SUPPLY7 Power Dissipation8 Full VI 3040 3300 mW Power Supply Rejection Ratio Full IV ± 0.5 ± 5.0 mV/V Total I (DVDD) Current Full VI 40 60 mA Total I (AVCC) Current Full VI 540 650 mA (VDD = 3.3 V, VCC = 5.0 V; ENCODE = 125 MSPS, unless otherwise noted.)

REV. 0 –3– AD10226 Test Parameter Temp Level Min Typ Max Unit DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 9 (Without Harmonics) fIN = 10.3 MHz 25 °CI 66.5 68.5 dBFS fIN = 49 MHz 25 °CV 67 dBFS fIN = 71 MHz 25 °CI 63 66 dBFS fIN = 121 MHz 25 °CV 64 dBFS fIN = 250 MHz 25 °CV 60 dBFS Signal-to-Noise Ratio (SINAD) 10 (With Harmonics) fIN = 10.3 MHz 25 °CI 65.5 68 dBFS fIN = 49 MHz 25 °CV 66.5 dBFS fIN = 71 MHz 25 °CI 62.5 65 dBFS fIN = 121 MHz 25 °CV 62.5 dBFS fIN = 250 MHz 25 °CV 59.5 dBFS Spurious-Free Dynamic Range 11 fIN = 10 MHz 25 °CI 76.5 82 dBFS fIN = 41 MHz 25 °CV 77 dBFS fIN = 71 MHz 25 °CI 66 72 dBFS fIN = 121 MHz 25 °CV 71 dBFS fIN = 250 MHz 25 °CV 70 dBFS Two-Tone Intermodulation Distortion12 (IMD) fIN = 29.3 MHz; fIN = 30.3 MHz 25 °CV 7 8 dBc fIN = 150 MHz; f IN = 151 MHz 25 °CV 7 0 dBc Channel-to-Channel Isolation 13 fIN = 121 MHz Full IV 85 dB NOTES 1All ac specifications tested by driving ENCODE and ENCODE differentially, with the analog input applied to A INX1 and AINX2 tied to ground. 2SFDR enabled (SFDR = 1) for DNL and INL specifications. 3Gain error measured at 10.3 MHz. 4Input VSWR, see TPC 14. 5See Figure 1, Timing Diagram. 6tV and tPD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital ou tput load during test is not to exceed an ac load of 10 pF or a dc current of ±40 /H9262A. 7Supply voltages should remain stable within ±5% for normal operation. 8Power dissipation measures with encode at rated speed. 9Analog input signal power at –1 dBFS; signal-to-noise (SNR) is the ratio of signal level to total noise (first six harmonics re moved). ENCODE = 125 MSPS, SFDR mode = 1. SNR is reported in dBFS, related back to converter full-scale. 10Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harm onics. ENCODE = 125 MSPS. SINAD is reported in dBFS, related back to converter full-scale. 11Analog input signal equals –1 dBFS; SFDR is ratio of converter full-scale to worst spur. 12Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. 13Channel-to-channel isolation tested with A channel/50 Ω terminated (A IN A2) grounded and a full-scale signal applied to B channel (A IN B2). Specifications subject to change without notice.

recommended to avoid performance degradation or loss of functionality. extended periods may affect device reliability. Figure 1. Timing Diagram

• · ·
• · · 00 0000 0000 0000 –1 –0.000427 1111 1111 1111
• · ·
• · · –2048 –0.875 1000 0000 0000

REV. 0 AD10226 –5– PIN CONFIGURATION 35mm SQUARE BOTTOM VIEW A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE 24 22 20 18 16 14 12 10 8 6 4 2 25 23 21 19 17 15 13 11 9 7 5 3 1 PIN FUNCTION DESCRIPTIONS Mnemonic Function AGNDA A Channel Analog Ground. A and B grounds should be connected as close to the device as possible. REF_A_OUT A Channel Internal Voltage Reference NC No connection AIN A1 Analog Input for A side ADC (– input) AIN A2 Analog Input for A side ADC (+ input) AVCCA Analog Positive Supply Voltage (nominally 5.0 V) DGNDA A Channel Digital Ground D11A–D0A Digital Outputs for ADC A. D0 (LSB) ENCODEA Complement of ENCODE ENCODEA Data conversion initiated on the rising edge of ENCODE input. DV CCA Digital Positive Supply Voltage (nominally 3.3 V) DGNDB B Channel Digital Ground D11B–D0B Digital Outputs for ADC B. D0 (LSB) AGNDB B Channel Analog Ground. A and B grounds should be connected as close to the device as possible. DV CCB Digital Positive Supply Voltage (nominally 3.3 V) ENCODEB Complement of ENCODE ENCODEB Data conversion initiated on rising edge of ENCODE input. REF_B_OUT B Channel Internal Voltage Reference AIN B1 Analog Input for B side ADC (– input) AIN B2 Analog Input for B side ADC (+ input) AVCCB Analog Positive Supply Voltage (nominally 5.0 V) DFS Data format select. Low = Two’s Complement, High = Binary. SFDR Mode CMOS control pin that enables (SFDR MODE = 1) a proprietary circuit that may improve the spurious free dynamic range (SFDR) performance. It is useful in applications where the dynamic range of the system is limited by discrete spurious frequency content caused by nonlinearities in the ADC transfer function. SFDR Mode = 0 for normal operation.

REV. 0 AD10226 –6– A1 AGNDA A2 AGNDA A3 AGNDA A4 AGNDA A5 AGNDA A6 AGNDA A7 DNC A8 DNC A9 AGNDA A10 AV CCA A11 REF_A_OUT A12 AGNDA A13 DNC A14 AGNDB A15 AGNDB A16 AV CCB A17 AGNDB A18 AV CCB A19 DNC A20 DNC A21 AGNDB A22 AGNDB A23 AGNDB A24 AGNDB A25 AGNDB B1 AGNDA B2 AGNDA B3 AGNDA B4 AGNDA B5 AGNDA B6 AGNDA B7 DNC B8 DNC B9 AGNDA B10 AV CCA B11 REF_A_OUT B12 AGNDA B13 DNC B14 AGNDB B15 AGNDB B16 AV CCB B17 AGNDB B18 AV CCB B19 DNC B20 DNC B21 AGNDB B22 AGNDB B23 AGNDB B24 AGNDB B25 AGNDB C1 AGNDA C2 AGNDA C3 AGNDA C4 AGNDA C5 AGNDA C6 AGNDA C7 DNC C8 DNC C9 AGNDA C10 AV CCA C11 REF_A_OUT C12 AGNDA C13 DNC C14 AGNDB C15 AGNDB C16 AV CCB C17 AGNDB C18 AV CCB C19 DNC C20 DNC C21 AGNDB C22 AGNDB C23 AGNDB C24 AGNDB C25 AGNDB D1 AGNDA D2 AGNDA D3 AGNDA D4 AGNDA D5 AGNDA D6 AGNDA D7 A INA2 D8 A INA1 D9 AGNDA D10 AV CCA D11 REF_A_OUT D12 AGNDA D13 DNC D14 AGNDB D15 AGNDB D16 AV CCB D17 AGNDB D18 AV CCB D19 A INB2 D20 A INB1 D21 AGNDB D22 AGNDB D23 AGNDB D24 AGNDB D25 AGNDB E1 AGNDA E2 AGNDA E3 AGNDA E4 AGNDA E22 AGNDB E23 AGNDB E24 AGNDB E25 AGNDB F1 AGNDA F2 AGNDA F3 AGNDA F4 AGNDA F22 AGNDB F23 AGNDB F24 AGNDB F25 AGNDB G1 AGNDA G2 AGNDA G3 AGNDA G4 AGNDA G22 AGNDB G23 AGNDB G24 AGNDB G25 AGNDB H1 AGNDA H2 AGNDA H3 AGNDA H4 AGNDA H22 AGNDB H23 AGNDB H24 AGNDB H25 AGNDB J1 AV CCA J2 AV CCA J3 AV CCA J4 AV CCA J22 REF_B_OUT J23 REF_B_OUT J24 REF_B_OUT J25 REF_B_OUT K1 AGNDA K2 AGNDA K3 AGNDA K4 AGNDA K10 SFDR_MODE_A K11 AGNDA K12 AGNDA K13 DNC K14 AGNDB K15 AGNDB K16 SFDR_MODE_B K22 AGNDB K23 AGNDB K24 AGNDB K25 AGNDB L1 AGNDA L2 AGNDA L3 AGNDA L4 AGNDA L10 DFS_A L11 AGNDA L12 AGNDA L13 DNC L14 AGNDB L15 AGNDB L16 DFS_B L22 ENCBB L23 ENCBB L24 ENCBB L25 ENCBB M1 ENCAB M2 ENCAB M3 ENCAB M4 ENCAB M10 AGNDA M11 AGNDA M12 AGNDA M13 DNC M14 AGNDB M15 AGNDB M16 AGNDB M22 ENCB M23 ENCB M24 ENCB M25 ENCB N1 ENCA N2 ENCA N3 ENCA N4 ENCA N10 GAIN_A N11 AGNDA N12 AGNDA N13 DNC N14 AGNDB N15 AGNDB N16 AGNDB N22 AGNDB N23 AGNDB N24 AGNDB N25 AGNDB P1 AGNDA P2 AGNDA P3 AGNDA P4 AGNDA P10 AGNDA P11 AGNDA P12 AGNDA P13 DNC P14 AGNDB P15 AGNDB P16 AGNDB P22 DV CCB P23 DV CCB P24 DV CCB P25 DV CCB P25 DV CCB R1 DV CCA R2 DV CCA R3 DV CCA R4 DV CCA R10 AGNDA R11 AGNDA R12 AGNDA R13 DNC R14 AGNDB R15 AGNDB R16 AGNDB R22 DB0 R23 DB0 R24 DB0 R25 DB0 T1 DA11 T2 DA11 T3 DA11 T4 DA11 T10 AV CCA T11 AGNDA T12 AGNDA T13 DNC T14 AV CCB T15 GAIN_B T16 AGNDB T22 DB1 T23 DB1 T24 DB1 T25 DB1 U1 DA10 U2 DA10 U3 DA10 U4 DA10 U22 DB2 U23 DB2 U24 DB2 U25 DB2 V1 DA9 V2 DA9 V3 DA9 V4 DA9 V22 DB3 V23 DB3 V24 DB3 V25 DB3 W1 DA8 W2 DA8 W3 DA8 W4 DA8 W22 DB4 W23 DB4 W24 DB4 W25 DB4 Y1 DA7 Y2 DA7 Y3 DA7 Y4 DA7 Y22 DB5 Y23 DB5 Y24 DB5 Y25 DB5 AA1 DGNDA AA2 DGNDA AA3 DGNDA AA4 DGNDA AA22 DGNDB AA23 DGNDB AA24 DGNDB AA25 DGNDB AB1 OVRA AB2 OVRA AB3 OVRA AB4 OVRA AB5 DGNDA AB6 DA6 AB7 DA5 AB8 DA4 AB9 DA3 AB10 DA2 AB11 DA1 AB12 DA0 AB13 DGNDA AB14 DGNDB AB15 DB11 AB16 DB10 AB17 DB9 AB18 DB8 AB19 DB7 AB20 DB6 AB21 DGNDB AB22 OVRB AB23 OVRB AB24 OVRB AB25 OVRB AC1 DGNDA AC2 DGNDA AC3 DGNDA AC4 DGNDA AC5 DGNDA AC6 DA6 AC7 DA5 AC8 DA4 AC9 DA3 AC10 DA2 AC11 DA1 AC12 DA0 AC13 DGNDA AC14 DGNDB AC15 DB11 AC16 DB10 AC17 DB9 AC18 DB8 AC19 DB7 AC20 DB6 AC21 DGNDB AC22 DGNDB AC23 DGNDB AC24 DGNDB AC25 DGNDB AD1 DGNDA AD2 DGNDA AD3 DGNDA AD4 DGNDA AD5 DGNDA AD6 DA6 AD7 DA5 AD8 DA4 AD9 DA3 AD10 DA2 AD11 DA1 AD12 DA0 AD13 DGNDA AD14 DGNDB AD15 DB11 AD16 DB10 AD17 DB9 AD18 DB8 AD19 DB7 AD20 DB6 AD21 DGNDB AD22 DGNDB AD23 DGNDB AD24 DGNDB AD25 DGNDB AE1 DGNDA AE2 DGNDA AE3 DGNDA AE4 DGNDA AE5 DGNDA AE6 DA6 AE7 DA5 AE8 DA4 AE9 DA3 AE10 DA2 AE11 DA1 AE12 DA0 AE13 DGNDA AE14 DGNDB AE15 DB11 AE16 DB10 AE17 DB9 AE18 DB8 AE19 DB7 AE20 DB6 AE21 DGNDB AE22 DGNDB AE23 DGNDB AE24 DGNDB AE25 DGNDB 385-LEAD BGA PINOUT Ball Signal Ball Signal Ball Signal Ball Signal Ball Signal Ball Signal

REV. 0 AD10226 –7– 385-LEAD BGA PINOUT (Top View, PCB Footprint) DNC = DO NOT CONNECT AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AV CCA AGNDA AGNDA OVRB DGNDB DGNDB DGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB DB0 DB1 DB2 DB3 DB4 DB5 DGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB OVRB DGNDB DGNDB DGNDB OVRB DGNDB DGNDB DGNDB OVRB DGNDB DGNDB DGNDB DB0 DB1 DB2 DB3 DB4 DB5 DGNDB DB0 DB1 DB2 DB3 DB4 DB5 DGNDB DB0 DB1 DB2 DB3 DB4 DB5 DGNDB REF_B_OUT AGNDB ENCBB ENCB AGNDB DVCCB REF_B_OUT AGNDB ENCBB ENCB AGNDB DVCCB REF_B_OUT AGNDB ENCBB ENCB AGNDB DVCCB REF_B_OUT AGNDB ENCBB ENCB AGNDB DVCCB DGNDA OVRA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DA6 DA6 DA6 DA6 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE DGNDA OVRA DGNDA DGNDA DGNDA DGNDA OVRA DGNDA DGNDA DGNDA DGNDA OVRA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDB DGNDB DGNDB DGNDB DB11 DB11 DB11 DB11 DB10 DB10 DB10 DB10 DB9 DB9 DB9 DB9 DB8 DB8 DB8 DB8 DB7 DB7 DB7 DB7 DB6 DB6 DB6 DB6 DGNDB DGNDB DGNDB DGNDB AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA DNC DNC DNC DNC DNC DNC DNC AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AV CCB ENCAB ENCA AGNDA DVCCA DA11 DA10 DA9 DA8 DA7 AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AV CCA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AV CCA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AV CCA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA DNC DNC DNC AINA2 DNC DNC DNC AINA1 AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AVCCA AVCCA AVCCA AVCCA REF_A_OUT REF_A_OUT REF_A_OUT REF_A_OUT DNC DNC DNC DNC AGNDB AGNDB AGNDB AGNCB AGNDB AGNDB AGNDB AGNCB AVCCB AVCCB AVCCB AVCCB AGNDB AGNDB AGNDB AGNCB AVCCB AVCCB AVCCB AVCCB DNC DNC DNC AINB2 AGNDB AGNDB AGNDB AGNDB DNC DNC DNC AINB1 ENCAB ENCA AGNDA DVCCA DA11 DA10 DA9 DA8 DA7 ENCAB ENCA AGNDA DVCCA DA11 DA10 DA9 DA8 DA7 ENCAB ENCA AGNDA DVCCA DA11 DA10 DA9 DA8 DA7 DFS_B AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA DA5 DA5 DA5 DA5 DA4 DA4 DA4 DA4 DA3 DA3 DA3 DA3 DA2 DA2 DA2 DA2 DA1 DA1 DA1 DA1 DA0 DA0 DA0 DA0 DFS_A AGNDA AGNDA AGNDA AGNDA AV CCB SFDR Mode A SFDR Mode B

REV. 0 AD10226 –8– FREQUENCY – MHz /H11546130 dB /H1154620 /H1154680 /H11546100 /H11546110 /H11546120 /H1154640 /H1154660 /H1154610 /H1154630 /H1154690 /H1154650 /H1154670 51 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 ENCODE = 125MSPS AIN = 10.3MHz (–1dBFS) SNR = 68.19dBFS SFDR = 85.13dBFS 55 60 TPC 1. Single Tone @ 10.3 MHz FREQUENCY – MHz /H11546130 dB /H1154620 /H1154680 /H11546100 /H11546110 /H11546120 /H1154640 /H1154660 /H1154610 /H1154630 /H1154690 /H1154650 /H1154670 51 0 1 5 2 0 2 5 3 03 54 04 5 5 0 ENCODE = 125MSPS AIN = 49MHz (–1dBFS) SNR = 67.12dBFS SFDR = 83.09dBFS 55 60 TPC 2. Single Tone @ 49 MHz FREQUENCY – MHz /H11546130 dB /H1154620 /H1154680 /H11546100 /H11546110 /H11546120 /H1154640 /H1154660 /H1154610 /H1154630 /H1154690 /H1154650 /H1154670 51 0 1 5 2 0 2 5 3 03 54 04 5 5 0 ENCODE = 125MSPS AIN = 71MHz (–1dBFS) SNR = 66.2dBFS SFDR = 82.02dBFS 55 60 TPC 3. Single Tone @ 71 MHz – Typical Performance Characteristics FREQUENCY – MHz /H11546130 dB /H1154620 /H1154680 /H11546100 /H11546110 /H11546120 /H1154640 /H1154660 /H1154610 /H1154630 /H1154690 /H1154650 /H1154670 51 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 ENCODE = 125MSPS AIN = 121MHz (–1dBFS) SNR = 63.66dBFS SFDR = 79.28dBFS 55 60 TPC 4. Single Tone @ 121 MHz FREQUENCY – MHz /H11546130 dB /H1154620 /H1154680 /H11546100 /H11546110 /H11546120 /H1154640 /H1154660 /H1154610 /H1154630 /H1154690 /H1154650 /H1154670 51 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 ENCODE = 125MSPS AIN = 240MHz (–1dBFS) SNR = 59.06dBFS SFDR = 74.56dBFS 55 60 TPC 5. Single Tone @ 240 MHz FREQUENCY – MHz /H11546130 dB /H1154620 /H1154680 /H11546100 /H11546110 /H11546120 /H1154640 /H1154660 /H1154610 /H1154630 /H1154690 /H1154650 /H1154670 51 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 ENCODE = 125MSPS AIN = 29.3MHz AND 30.3MHz SFDR = 79.03dBFS 55 60 TPC 6. Two Tone @ 29/30 MHz

REV. 0 AD10226 –9– FREQUENCY – MHz /H11546130 dB /H1154620 /H1154680 /H11546100 /H11546110 /H11546120 /H1154640 /H1154660 /H1154610 /H1154630 /H1154690 /H1154650 /H1154670 51 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 ENCODE = 125MSPS AIN = 150MHz AND 151MHz SFDR = 75.38dBFS 55 60 TPC 7. Two Tone @ 150/151 MHz FREQUENCY – MHz /H11546130 dB /H1154620 /H1154680 /H11546100 /H11546110 /H11546120 /H1154640 /H1154660 /H1154610 /H1154630 /H1154690 /H1154650 /H1154670 51 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 ENCODE = 125MSPS AIN = 240MHz AND 241MHz SFDR = 67dBFS 55 60 TPC 8. Two Tone @ 240/241 MHz 3.0 /H115461.0 LSB 1.5 0.5 0.0 /H115460.5 2.5 1.0 2.0 512 1024 1536 2048 2560 3072 3584 4096 ENCODE = 125MSPS DNL MIN = 0.530 DNL MAX = 0.369 OUTPUT CODES TPC 9. Differential Nonlinearity 3.0 /H115463.0 LSB0.0 1.0 2.0 512 1024 1536 2048 2560 3072 3584 4096 /H115462.0 /H115461.0 ENCODE = 125MSPS INL MIN = 0.610 INL MAX = 0.702 OUTPUT CODES TPC 10. Integral Nonlinearity GAIN – dB /H115466 /H115462 /H115464 FREQUENCY – MHz /H115463 /H115465 100 1000 /H115461 TPC 11. Frequency Response GAIN – dB /H115462 FREQUENCY – MHz 100 1000 /H115461 TPC 12. Gain Flatness* *Gain flatness measurement is performed by applying a constant voltage at the device input.

REV. 0 AD10226 –10– 10MHz = 52.22 – j0.421 50MHz = 50.69 – j2.84 100MHz = 47.50 – j3.58 150MHz = 44.61 – j0.970 200MHz = 43.70 + j3.70 250MHz = 46.41 + j9.48 300MHz = 53.09 + j14.76 TPC 13. Input Impedance S11 FREQUENCY – MHz 0.1 1 GAIN – dB 100 1000 1MHz = 1.010 10MHz = 1.028 50MHz = 1.045 100MHz = 1.066 140MHz = 1.090 160MHz = 1.126 200MHz = 1.170 TPC 14. Voltage Standing Wave Ratio (VSWR) Equivalent Circuits VCC 24k/H9024 8k/H9024 ENCODE ENCODE 8k/H9024 24k/H9024 Test Circuit 1. Equivalent ENCODE Input VCC 100/H9024DIGITAL OUTPUT Test Circuit 2. Equivalent Digital Output NPN VREF OUTPUT VCC VCC Test Circuit 3. Equivalent Voltage Reference Output VCC AIN2 15k/H9024 50/H9024 3.75k/H9024 AIN1 15k/H9024 3.75k/H9024 Test Circuit 4. Equivalent Analog Input DEFINITION OF TERMS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point on the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Nonlinearity The deviation of any code from an ideal 1 LSB step. ENCODE Pulsewidth/Duty Cycle Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in logic “1” state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable ENCODE duty cycle.

interference (EMI) and an overall improvement in performance. pins to reduce stray capacitance. The Solder Reflow Profile for the AD10226 is shown in Figure 6. Figure 6. Typical Solder Reflow Profile be used to decouple each supply pin to ground directly at the device. All capacitors can be standard high quality ceramic chip capacitors. to externally isolate the device from the receiving gate. or application assistance is required.

2 U16, U17 IC, Low Voltage 16-Bit D-Type Flip-Flop 74LCX16374MTD

8 R1, R7, R8, R41, R60, R61, R71, R72 51 Ω RES 51 Ω 1/10W 5% 0805 SMD ERJ-6GEYJ510V (Panasonic)

32 R3, R4, R9–R18, R23–R30, R35, 100 Ω RES 100 Ω 1/10W 1% 0805 SMD ERJ-6ENF1000V

2 J1, J2 2 /H11003 20 Male Connector Strip, 100 Centers TSW-120-08G-D (Samtec)

4 L1, L2, L3, L4 47 Ω SMT Ferrite Bead 2743019447 (Fair Rite)

8 E3–E6, E25, E26, E33, E34 Power Jack, Banana Plug 108- 0740-001 (Johnson Company)

10 C3, C4, C11, C14, C15, C19, 10 µF Solid Tantalum Chip Capacitor, T 491C106M016AS

8 J3–J7, J10–J12 SMA PLUG 200Mil STR GOLD 142-0801-201

4 Spacer Aluminum, Hex M–F (Standoff)

4 Nut Hex Stl #4-40 UNC-2B

6 JP3, JP4, JP6, JP8, JP9, JP12 0 Ω RES 0 Ω 1/16 W 5% 0402 ER J-2GEOR00

REV. 0 AD10226 –14– R71 51/H9024 MSB B11A B10A B9A B8A B7A B6A B5A B4A B3A B2A B1A LSB B0A DGNDA DGNDA BUFLA T A DGNDA C15 10/H9262F 16V 3.3VDA 18CP2 OE2 I15 I14 I13 I12 I11 I10 CP1 OE1 GND GND GND GND VCC VCC O15 O14 O13 O12 O11 O10 GND GND GND GND VCC VCC U16 MSB D11A D10A D9A D8A D7A D6A D5A D4A 51/H9024 LA TCHA LSB D0A D3A D2A D1A DGNDA 74LCX16374MTD DGNDA R18 100/H9024 R17 100/H9024 R16 100/H9024 R40 100/H9024 R44 100/H9024 R45 100/H9024 R46 100/H9024 R15 100/H9024 R14 100/H9024 R13 100/H9024 R24 100/H9024 R23 100/H9024 DUT_3.3VDA B11A MSB B10A B9A B8A B7A B6A B5A B4A B3A B2A B1A B0A LSB R72 51/H9024 MSB B11B B10B B9B B8B B7B B6B B5B B4B B3B B2B B1B LSB B0B DGNDB DGNDB BUFLA TB DGNDB C14 10/H9262F 16V 3.3VDB 18CP2 OE2 I15 I14 I13 I12 I11 I10 CP1 OE1 GND GND GND GND VCC VCC O15 O14 O13 O12 O11 O10 GND GND GND GND VCC VCC U17 MSB D11B D10B D9B D8B D7B D6B D5B D4B 51/H9024 LA TCHB LSB D0B D3B D2B D1B DGNDB 74LCX16374MTD DGNDB R11 100/H9024 R10 100/H9024 R30 100/H9024 R29 100/H9024 R28 100/H9024 R27 100/H9024 R26 100/H9024 R12 100/H9024 100/H9024 R25 100/H9024 R36 100/H9024 R35 100/H9024 DUT_3.3VDB B11B MSB B10B B9B B8B B7B B6B B5B B4B B3B B2B B1B B0B LSB Figure 7a. Evaluation Board Schematic

REV. 0 AD10226 –15– JP1 AINA1 AGNDA AGNDA AGNDA 5VAA 10/H9262F 16V 47/H9024 @ 100MHz C20 0.1/H9262F C11 10/H9262F 16V AGNDA 5VAA AINA1 AINA2 AGNDA AINA2 AGNDB AGNDB 5VAB 10/H9262F 16V 47/H9024 @ 100MHz C21 0.1/H9262F C19 10/H9262F 16V AGNDB 5VAB AINB2 AGNDB AINB2 JP2 AINB1 AGNDBDGNDA E34 DGNDA E25 3.3VDA C29 10/H9262F 16V 47/H9024 @ 100MHz C12 0.1/H9262F C31 10/H9262F 16V DGNDA DUT_3.3VDA AINB1 DGNDB E33 DGNDB E26 3.3VDB C30 10/H9262F 16V 47/H9024 @ 100MHz C16 0.1/H9262F C32 10/H9262F 16V DGNDB DUT_3.3VDB AGNDA C34 0.1/H9262F 5VAA DGNDA 0.1/H9262F C10 0.1/H9262F DUT_3.3VDA DGNDB C17 0.1/H9262F C18 0.1/H9262F DUT_3.3VDB DGNDB E30E29 E35E36 E37E38 E39E40 E46E45 E80E79 E83E84 AGNDB E41E42 E43E44 E47E48 E65E66 E68E67 E69E70 E71E72 AGNDADGNDA E74E73 E75E76 E82E81 STITCHES TO TIE GROUNDS TOGETHER E78 E77 E7 E12 E10 E9 E8 E11 E1 E2 DGNDA DGNDB DGNDA DGNDB DGNDA AGNDA AGNDA AGNDB DGNDB AGNDB Figure 7b. Evaluation Board Schematic

REV. 0 AD10226 –16– NC VCC DQ DQ VBB VEE MC10EP16D AGNDA C13 0.1/H9262F 25V R42 100/H9024 R43 100/H9024 AGNDA R56 33k/H9024 3.3VA 0.1/H9262F 51/H9024 AGNDA AGNDA ENCODE IN OUT SD NR ERR GND U14 AGNDA 5VAA 3.3VA NC VCC DQ DQ VBB VEE MC10EP16D DGNDA 0.1/H9262F R3 100/H9024 100/H9024 DGNDA R58 33k/H9024 3.3VDA 0.1/H9262F R41 51/H9024 AGNDA AGNDA J12 ENCA 3.3VDA D0 VCC D0 Q D1 Q D1 GND SY100EPT23L DGNDA 0.1/H9262F 3.3VDA LA TCHA BUFLA T A E23 E19 0.1/H9262F 0.1/H9262F ENCAB ENCA NC VCC U11 DQ DQ VBB VEE MC10EP16D AGNDB C27 0.47/H9262F 25V R63 100/H9024 R64 100/H9024 AGNDB R38 33k/H9024 3.3VB C22 0.1/H9262F R60 51/H9024 AGNDB AGNDB J10 ENCODE IN OUT SD NR ERR GND U15 AGNDB 5VAB 3.3VB NC VCC DQ DQ VBB VEE MC10EP16D DGNDB C25 0.1/H9262F R65 100/H9024 R66 100/H9024 DGNDB R39 33k/H9024 3.3VDB R61 51/H9024 AGNDB AGNDB J11 ENCB 3.3VDB D0 VCC U10 D0 Q D1 Q D1 GND SY100EPT23L DGNDB C26 0.1/H9262F 3.3VDB LA TCHB BUFLA TB E24 E22 C24 0.1/H9262F C28 0.1/H9262F ENCBB ENCB C23 0.1/H9262F Figure 7c. Evaluation Board Schematic

REV. 0 AD10226 –17– AB25 AB24 AB23 AB22 AE15 AD15 AC15 AB15 AE16 AD16 AC16 AB16 AE17 AD17 AC17 AB17 AE18 AD18 AC18 AB18 AE19 AD19 AC19 AB19 AE20 AD20 AC20 AB20 Y25 Y24 Y23 Y22 W25 W24 W23 W22 V25 V24 V23 V22 U25 U24 U23 U22 T25 T24 T23 T22 R25 R24 R23 R22 M25 M24 M23 M22 L25 L24 L23 L22 J25 J24 J23 J22 D20 C20 B20 A20 D19 C19 B19 A19 AINB2 AINB1 ENCBB ENCB D0B D1B D2B D3B D4B D5B D6B D7B D8B D9B D10B D11B OVRB AGNDB C35 0.1/H9262F E50 AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB A12 B12 C12 D12 K10 K11 K12 L10 L11 L12 M10 M11 M12 N10 N11 N12 P10 P11 P12 R10 R11 R12 T10 T11 T12 AA1 AA2 AA3 AA4 AB5 AB13 AC1 AC2 AC3 AC4 AC5 AC13 AD1 AD2 AD3 AD4 AD5 AD13 AE1 AE2 AE3 AE4 AE5 AE13 AA22 AA23 AA24 AA25 AB14 AB21 AC14 AC21 AC22 AC23 AC24 AC25 AD14 AD21 AD22 AD23 AD24 AD25 AE14 AE21 AE22 AE23 AE24 AE25 AGNDA DGNDA DGNDB OVRB OVRB OVRB OVRB D11B (MSBB) D11B (MSBB) D11B (MSBB) D11B (MSBB) D10B D10B D10B D10B D9B D9B D9B D9B D8B D8B D8B D8B D7B D7B D7B D7B D6B D6B D6B D6B D5B D5B D5B D5B D4B D4B D4B D4B D3B D3B D3B D3B D2B D2B D2B D2B D1B D1B D1B D1B D0B (LSBB) D0B (LSBB) D0B (LSBB) D0B (LSBB) ENCB ENCB ENCB ENCB ENCBB ENCBB ENCBB ENCBB REF_B REF_B REF_B REF_B AINB1 AINB1 AINB1 AINB1 AINB2 AINB2 AINB2 AINB2 JP4 AGNDA C36 0.047/H9262F AGNDA JP6 AGNDA JP3 AGNDA +5VAA 5VAA 5VAA 5VAA 5VAA 5VAA 5VAA 5VAA 5VAA 3.3VDA 3.3VDA 3.3VDA 3.3VDA SHEILD SHEILD SHEILD SHEILD SHEILD SHEILD SHEILD SHEILD SHEILD SHEILD SHEILD 3.3VDB 3.3VDB 3.3VDB 3.3VDB 5VAB 5VAB 5VAB 5VAB 5VAB 5VAB 5VAB 5VAB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB A10 B10 C10 D10 A13 B13 C13 D13 K13 L13 M13 N13 P13 R13 T13 P22 P23 P24 P25 A16 B16 C16 D16 A18 B18 C18 D18 A14 A15 A17 A21 A22 A23 A24 A25 B14 B15 B17 B21 B22 B23 B24 B25 C14 C15 C17 C21 C22 C23 C24 C25 D14 D15 D17 D21 D22 D23 D24 D25 E22 E23 E24 E25 F22 F23 F24 F25 G22 G23 G24 G25 H22 H23 H24 H25 K14 K15 K16 K22 K23 K24 K25 L14 L15 L16 M14 M15 M16 N14 N15 N16 N22 N23 N24 N25 P14 P15 P16 R14 R15 R16 T14 T15 T16 AGNDB JP12 AGNDB JP9 AGNDB JP8 C37 0.047/H9262F +5VAA DUT_3.3VDA DUT_3.3VDB +5VAB OVRA OVRA OVRA OVRA D0A (LSBA) D0A (LSBA) D0A (LSBA) D0A (LSBA) D1A D1A D1A D1A D2A D2A D2A D2A D3A D3A D3A D3A D4A D4A D4A D4A D5A D5A D5A D5A D6A D6A D6A D6A D7A D7A D7A D7A D8A D8A D8A D8A D9A D9A D9A D9A D10A D10A D10A D10A D11A (MSBA) D11A (MSBA) D11A (MSBA) D11A (MSBA) ENCA ENCA ENCA ENCA ENCAB ENCAB ENCAB ENCAB AINA2 AINA2 AINA2 AINA2 AINA1 AINA1 AINA1 AINA1 REF_A REF_A REF_A REF_A AB4 AB3 AB2 AB1 AE12 AD12 AC12 AB12 AE11 AD11 AC11 AB11 AE10 AD10 AC10 AB10 AE9 AD9 AC9 AB9 AE8 AD8 AC8 AB8 AE7 AD7 AC7 AB7 AE6 AD6 AC6 AB6 D11 C11 B11 A11 AINA1 AINA2AGNDA C33 0.1/H9262F E49 OVRA D0A D1A D2A D3A D4A D5A D6A D7A D8A D9A D10A D11A ENCA ENCAB AD10226 +5VAA +5VAA +5VAA +5VAB +5VAB +5VAB +5VAB AGNDB Figure 7d. Evaluation Board Schematic

REV. 0–20– PRINTED IN U.S.A. AD10226 C02927–0–5/02(0) OUTLINE DIMENSIONS Dimensions shown in millimeters (mm). 385-Lead Ball Grid Array (BGA) (B-385) AD10201AB XXXX DET AIL C 0.75 0.60 0.50 DET AIL A 0.90 0.75 0.60 DET AIL B AD10201AB XXXX DET AIL C 37.00

35.00 BSC SQ

33.00 DET AIL A 1.27 TYP A C E G J L N R U W AA AC B D F H K M P T V Y AB AD AE 135791113151719212325 24681012141618202224 DET AIL B

30.48 BSC

VOLUME 1.15 1.02 0.89 3.20 MAX