AD10200

AD10200_17 AD | Alldatasheet

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REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD10200 Tel: 7 81/329-4700 www.analog.com Fax: 781/326-8703 ©Analog Devices, Inc., 2001–2016 Dual Channel, 12-Bit 105 MSPS IF Sampling A/D Converter with Analog Input Signal Conditioning FUNCTIONAL BLOCK DIAGRAM

50 D00B

(LSB)

49 D01B

48 D02B

47 D03B

46 D04B

45 D05B

42 D06B

41 D07B

40 D08B

39 D09B

38 D10B

37 D11B

(MSB) 34D00A (LSB) D01A D02A D03A D04A D05A D06A D07A D08A D09A D10A D11A (MSB) ADC 50/H9024 AINA2 T1A ADC 50/H9024 AINB2 T1B AD10200 OUTPUT RESISTORS 12 12 18 17 ENCODEAENCODEA REF REF_A_OUT TIMING 53 54 ENCODEBENCODEB REF REF_B_OUT OUTPUT RESISTORS 12 12 T/H T/H TIMING

FEATURES

Dual, 105 MSPS Minimum Sample Rate Channel-Channel Isolation, >80 dB AC-Coupled Signal Conditioning Included Gain Flatness up to Nyquist: < 0.2 dB Input VSWR 1.1:1 to Nyquist 80 dB Spurious-Free Dynamic Range Two’s Complement Output Format

3.3 V or 5 V CMOS-Compatible Output Levels

0.850 W per Channel

Industrial and Military Grade

APPLICATIONS

Multichannel, Multimode Receivers PRODUCT DESCRIPTION The AD10200 is a full channel ADC solution with on-module signal conditioning for improved dynamic performance and fully m atched channel-to-channel performance. The module includes two wide-dynamic range ADCs. Each ADC has a transformer coupled front-end optimized for Direct-IF sampling. The AD10200 has on-chip track-and-hold circuitry, and utilizes an innovative architecture to achieve 12-bit, 105 MSPS perfor- mance. The AD10200 uses innovative high-density circuit design to achieve exceptional matching and performance while still maintaining excellent isolation, and providing for significant board area savings. The AD10200 operates with 5.0 V supply for the analog-to- digital conversion. Each channel is completely independent allowing operation with independent encode and analog inputs. The AD10200 is packaged in a 68-lead ceramic chip carrier package. Manufacturing is done on Analog Devices, Inc. MIL-

38534 Qualified Manufacturers Line (QML) and components

are available up to Class-H (–50°C to +125°C). PRODUCT HIGHLIGHTS 1. Guaranteed sample rate of 105 MSPS. 2. Input signal conditioning with full power bandwidth to 250 MHz. 3. Fully tested/characterized performance at 121 MHz A IN. 4. Optimized for IF sampling.

AD10200* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS

• AD10200 Evaluation Board DOCUMENTATION Application Notes
• AN-280: Mixed Signal Circuit Technologies
• AN-282: Fundamentals of Sampled Data Systems
• AN-297: Test Video A/D Converters Under Dynamic Conditions
• AN-302: Exploit Digital Advantages in an SSB Receiver
• AN-342: Analog Signal-Handling for High Speed and Accuracy
• AN-345: Grounding for Low-and-High-Frequency Circuits
• AN-501: Aperture Uncertainty and ADC System Performance
• AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated
• AN-737: How ADIsimADC Models an ADC
• AN-741: Little Known Characteristics of Phase Noise
• AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter
• AN-835: Understanding High Speed ADC Testing and Evaluation
• AN-905: Visual Analog Converter Evaluation Tool Version

1.0 User Manual

• AN-935: Designing an ADC Transformer-Coupled Front End Data Sheet
• AD10200: Dual Channel, 12-Bit 105 MSPS IF Sampling A/D Converter with Analog Input Data Sheet SOFTWARE AND SYSTEMS REQUIREMENTS
• Military Part Cross-Reference Guide
• Military Products by Function
• Military Products by GENERIC Part Number
• SMD to Generic Cross Reference TOOLS AND SIMULATIONS
• Visual Analog REFERENCE MATERIALS Technical Articles
• Class T Satellite Products
• Correlating High-Speed ADC Performance to Multicarrier 3G Requirements
• DNL and Some of its Effects on Converter Performance
• MS-2210: Designing Power Supplies for High Speed ADC
• Multi-Channel Analog-to-Digital Converter Module Integration DESIGN RESOURCES
• AD10200 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints DISCUSSIONS View all AD10200 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

REV. B–2– AD10200–SPECIFICATIONS1 (VDD = 3.3 V, VCC = 5.0 V; ENCODE = 105 MSPS, unless otherwise noted) Test MIL Parameter Temp Level Subgroup Min Typ Max Unit RESOLUTION 12 Bits DC ACCURACY Differential Nonlinearity Full IV 12 –0.99 ±0.5 +0.99 LSB Integral Nonlinearity Full IV 12 –3 ±0.75 +3 LSB No Missing Codes Full I 1, 2, 3 Guaranteed Gain Error2 Full I 1, 2, 3 –9 ±1+ 9% F S Output Offset Full I 1, 2, 3 –12 +12 LSB ANALOG INPUT Input Voltage Range 25°C V 2.048 V p-p Input Impedance 25°CV 5 0 Ω Input VSWR3 Full IV 12 1.1:1 1.25:1 Ratio Analog Input Bandwidth, High Full IV 12 200 250 MHz Analog Input Bandwidth, Low Full IV 12 1 MHz ANALOG REFERENCE Output Voltage Full I 1, 2, 3 2.4 2.5 2.6 V Load Current 25°CV 5 m A Tempco Full V 50 ppm/°C SWITCHING PERFORMANCE Maximum Conversion Rate Full I 4, 5, 6 105 MSPS Minimum Conversion Rate Full IV 12 10 MSPS Duty Cycle Full IV 12 45 50 55 % Aperture Delay (tA)2 5°C V 1.0 ns Aperture Uncertainty (Jitter) 25°C V 0.25 ps rms Output Valid Time (t V)4 Full IV 12 3.0 5.3 ns Output Propagation Delay ( PD)4 Full IV 12 4.5 5.5 8.0 ns Output Rise Time (t R)2 5°C V 12 3.5 ns Output Fall Time (tF)2 5°C V 12 3.3 ns DIGITAL INPUTS Encode Input Common Mode Full IV 12 1.2 1.6 2.0 V Differential Input (Enc, Enc) Full IV 12 0.4 5.0 V Logic “1” Voltage Full IV 12 2.0 V Logic “0” Voltage Full IV 12 0.8 V Input Resistance Full IV 12 358k Ω Input Capacitance 25°C V 4.5 pF DIGITAL OUTPUTS Logic “1” Voltage4 Full VI 1, 2, 3 3.1 3.3 V Logic “0” Voltage4 Full VI 1, 2, 3 0 0.2 V Output Coding Two’s Complement POWER SUPPLY5 Power Dissipation6 Full I 1, 2, 3 1800 2200 mW Power Supply Rejection Ratio Full IV 12 ±0.5 ±5 mV/V I (DVDD) Current Full I 1, 2, 3 25 40 mA I (AVCC) Current Full I 1, 2, 3 340 410 mA DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 7 (Without Harmonics) fIN = 10 MHz 25°C V 67 dBFS Full V 66 dBFS fIN = 41 MHz 25°C I 4 64 66.5 dBFS Full II 5, 6 62 65 dBFS fIN = 71 MHz 25°C I 4 62.5 66.4 dBFS Full II 5, 6 61.5 64 dBFS fIN = 121 MHz 25°C I 4 61 65 dBFS Full II 5, 6 61 64 dBFS

–3– AD10200 Test MIL Parameter Temp Level Subgroup Min Typ Max Unit DYNAMIC PERFORMANCE (Continued) Signal-to-Noise Ratio (SINAD) 8 (With Harmonics) fIN = 10 MHz 25°C V 66 dBFS Full V 63 dBFS fIN = 41 MHz 25°C I 4 63 65.5 dBFS Full II 5, 6 60.5 63 dBFS fIN = 71 MHz 25°C I 4 61 63.5 dBFS Full II 5, 6 57 60 dBFS fIN = 121 MHz 25°C I 4 56 58.5 dBFS Full II 5, 6 53 55 dBFS Spurious Free Dynamic Range 9 fIN = 10 MHz 25°C V 81 dBFS Full V 70 dBFS fIN = 41 MHz 25°C I 4 73 81 dBFS Full II 5, 6 67.5 dBFS fIN = 71 MHz 25°C I 4 67 74 dBFS Full II 5, 6 60 dBFS fIN = 121 MHz 25°C I 4 61 65 dBFS Full II 5, 6 55.5 58 dBFS Two-Tone Intermodulation Distortion 10 (IMD) fIN = 10 MHz; fIN = 12 MHz 25 °C V 86 dBc Full V 81 dBc fIN = 71 MHz; fIN = 72 MHz 25 °C V 70 dBc Full V 65 dBc fIN = 121 MHz; fIN = 122 MHz 25 °C I 4 55.5 62 dBc Full II 5, 6 53 57 dBc Channel-to-Channel Isolation 11 fIN = 121 MHz Full IV 12 80 85 dB NOTES 1All ac specifications tested by driving ENCODE and ENCODE differentially. 2Gain Error measured at 2.5 MHz. 3Input VSWR guaranteed 10 MHz to 200 MHz. 4tV and tPD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 10 pF or a dc current of ± 40 mA. 5Supply voltages should remain stable within ± 5% for normal operation. 6Power dissipation measured with encode at rated speed and 0 dBm analog input. 7Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonic removed). Encode = 105 MSPS. SNR is reported in dBFS, related back to converter full scale. 8Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 105 MSPS. SINAD is reported in dBFS, related back to converter full scale. 9Analog Input signal equal –1 dBFS; SFDR is ratio of converter full scale to worst spur. 10Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 = x MHz ± 100 kHz, f2 = x MHz ± 100 kHz. 11Channel-to-Channel isolation tested with A Channel/50 Ω terminated (A INA2) grounded and a full-scale signal applied to B Channel (A INB2). Specifications subject to change without notice. REV. B

–4– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD10200 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ABSOLUTE MAXIMUM RATINGS 1, 2 NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2Typical thermal impedances for “Z” package: θJC = 2.22°C/W; θJA = 24.3°C/W. EXPLANATION OF TEST LEVELS Test Level I. 100% production tested. II. 100% production tested at 25 °C and sample tested at specific temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at 25 °C; guaranteed by design and characterization testing for industrial temperature range. Table I. Output Coding (VREF = 2.5 V) (Two’s Complement) Code AIN (V) Digital Output +2047 +1.024 0111 1111 1111

• • •
• • • 0 0 0000 0000 0000 –1 –0.00049 1111 1111 1111
• • •
• • • –2048 –1.024 1000 0000 0000 REV. B

Revision History

8/2016 Data Sheet changed from REV. A to REV. B. Data Sheet changed from REV. 0 to REV. A.

–5– PIN CONFIGURATION 27 4328 29 30 31 32 33 34 35 36 37 38 39 40 41 42 96 18 7 6 5 68 67 66 65 64 63 624321 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) AGNDB AGNDB DNC DNC REF_B_OUT AGNDB ENCODEB AGNDA AGNDA DNC AGNDA AV CC DNC AGNDA NC = NO CONNECT ENCODEA ENCODEA AGNDA DVCC ENCODEB AGNDB DV CC D0B (LSB) AGNDA AGNDA NC AGNDA DNC VREF_A_OUT DNC DNC AVCC AGNDB AGNDB AD10200 DNC AINA2 AGNDB SHIELD NC AINB2 (MSB) D11A D10A D9A D8A D7A DGNDA D1B D2B D3B D4B D5B DGNDB DGNDA D6A D5A D4A D3A D2A D1A (LSB) D0A AGNDA AGNDB (MSB) D11B D10B D9B D8B D7B D6B DGNDB PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function

1 SHIELD Internal Ground Shield between Channels

2, 5, 9–11, 13, 16, 19, 35 AGNDA A Channel Analog Ground. A and B grounds should be connected as close to the device as possible.

3 VREF_A_OUT A Channel Internal Voltage Reference

6, 62 NC No Connection 7A INA2 Analog Input for A Side ADC 4, 8, 12, 15, 57, 58, 64, 67 DNC Do Not Connect 14, 66 AVCC Analog Positive Supply Voltage (Nominally 5.0 V)

17 ENCODEA Complement of Encode

18 ENCODEA Data conversion initiated on the rising edge of ENCODE input. 20 DVCC Digital Positive Supply Voltage (Nominally 3.3 V) 21–25, 28–34 D11A–D7A, Digital Outputs for ADC A. D0 (LSB) D6A–D0A 26, 27 DGNDA A Channel Digital Ground 36, 52, 55, 59–61, 65, 68 AGNDB B Channel Analog Ground. A and B grounds should be connected as close to the device as possible. 37–42, 45–50 D11B–D6B, Digital Outputs for ADC B. D0 (LSB) D5B–D0B 43, 44 DGNDB B Channel Digital Ground 51 DVCC Digital Positive Supply Voltage (Nominally 3.3 V) 53 ENCODEB Data conversion initiated on rising edge of ENCODE input.

54 ENCODEB Complement of Encode

56 VREF_B_OUT B Channel Internal Voltage Reference

63 AINB2 Analog Input for B Side ADC

REV. B

REV. B AD10200 –6– DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point on the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Nonlinearity The deviation of any code from an ideal 1 LSB step. Encode Pulsewidth/Duty Cycle Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic “1” state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable Encode duty cycle. Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the worst harmonic component. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more that 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between the 50% point of the rising edge of ENCODE command and the time when all output data bits are within valid logic levels. Overvoltage Recovery Time The amount of time required for the converter to recover to 0.02% accuracy after an analog input signal of the specified percentage of full scale is reduced to midscale. Power Supply Rejection Ratio The ratio of a change in output offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set a 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. [May be reported in dBc (i.e., degrades as signal levels is lowered) or in dBFS (always related back to converter full scale)]. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set a I dB below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc. [May be reported in dBc (i.e., degrades as signal levels is lowered) or in dBFS (always related back to converter full scale).] Spurious-Free Dynamic Range The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious compo- nent may or may not be a harmonic. [May be reported in dBc (i.e., degrades as signal levels is lowered) or in dBFS (always related back to converter full scale).] Transient Response The time required for the converter to achieve 0.02% accu- racy when a on e-half full-scale step function is applied to the analog input. Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc. Voltage Standing-Wave Ratio (VSWR) The ratio of the amplitude of the elective field at a voltage maxi- mum to that at an adjacent voltage minimum.

REV. B –7– AD10200Typical Performance Characteristics– FREQUENCY – MHz /H11546130 dB /H1154620 /H1154680 /H11546100 /H11546110 /H11546120 /H1154640 /H1154660 /H1154610 /H1154630 /H1154690 /H1154650 /H1154670 5 1 01 52 02 53 03 54 04 55 0 ENCODE = 105 MSPS AIN = 10MHz (–1dBFS) SNR = 66.84dBFS SFDR = 82.28dBc TPC 1. Single Tone @ 10 MHz FREQUENCY – MHz /H11546130 dB /H1154620 /H1154680 /H11546100 /H11546110 /H11546120 /H1154640 /H1154660 /H1154610 /H1154630 /H1154690 /H1154650 /H1154670 5 1 01 52 02 53 03 54 04 55 0 ENCODE = 105 MSPS AIN = 71MHz (–1dBFS) SNR = 66.04dBFS SFDR = 79.71dBc TPC 2. Single Tone @ 71 MHz FREQUENCY – MHz /H11546130 dB /H1154620 /H1154680 /H11546100 /H11546110 /H11546120 /H1154640 /H1154660 /H1154610 /H1154630 /H1154690 /H1154650 /H1154670 5 1 01 52 02 53 03 54 04 55 0 ENCODE = 105 MSPS AIN = 121MHz (–6dBFS) SNR = 66.9dBFS SFDR = 65.57dBc TPC 3. Single Tone @ 121 MHz FREQUENCY – MHz /H11546130 dB /H1154620 /H1154680 /H11546100 /H11546110 /H11546120 /H1154640 /H1154660 /H1154610 /H1154630 /H1154690 /H1154650 /H1154670 5 1 01 52 02 53 03 54 04 55 0 ENCODE = 105 MSPS AIN = 41MHz (–1dBFS) SNR = 66.06dBFS SFDR = 80.59dBc TPC 4. Single Tone @ 41 MHz FREQUENCY – MHz /H11546130 dB /H1154620 /H1154680 /H11546100 /H11546110 /H11546120 /H1154640 /H1154660 /H1154610 /H1154630 /H1154690 /H1154650 /H1154670 5 1 01 52 02 53 03 54 04 55 0 ENCODE = 105 MSPS AIN = 121MHz (–1dBFS) SNR = 64.92dBFS SFDR = 64.73dBc TPC 5. Single Tone @ 121 MHz FREQUENCY – MHz /H11546130 dB /H1154620 /H1154680 /H11546100 /H11546110 /H11546120 /H1154640 /H1154660 /H1154610 /H1154630 /H1154690 /H1154650 /H1154670 5 1 01 52 02 53 03 54 04 55 0 ENCODE = 105 MSPS AIN = 201MHz (–10dBFS) SNR = 66.84dBFS SFDR = 64.57dBc TPC 6. Single Tone @ 201 MHz

REV. B AD10200 –8– FREQUENCY – MHz /H11546130 dBc /H1154620 /H1154680 /H11546100 /H11546110 /H11546120 /H1154640 /H1154660 /H1154610 /H1154630 /H1154690 /H1154650 /H1154670 5 1 01 52 02 5 3 03 54 04 55 0 ENCODE = 105 MSPS AIN = 37MHz & 38MHz (–10dBFS) SFDR = 79.84dBc TPC 7. Two-Tone @ 37 MHz/38 MHz FREQUENCY – MHz /H11546130 dBc /H1154620 /H1154680 /H11546100 /H11546110 /H11546120 /H1154640 /H1154660 /H1154610 /H1154630 /H1154690 /H1154650 /H1154670 5 1 01 52 02 53 03 54 04 55 0 ENCODE = 105 MSPS AIN = 120MHz & 121MHz (–7dBFS) SFDR = 63.8dBc TPC 8. Two-Tone @ 120 MHz/121 MHz /H115463 LSB0 /H115462 /H115461 512 1024 1536 2048 2560 3072 3584 4096 ENCODE = 105 MSPS INL MAX = 0.874 Codes INL MIN = 0.895 Codes TPC 9. Integral Nonlinearity FREQUENCY – MHz /H11546130 dBc /H1154620 /H1154680 /H11546100 /H11546110 /H11546120 /H1154640 /H1154660 /H1154610 /H1154630 /H1154690 /H1154650 /H1154670 5 1 01 52 02 53 03 54 04 55 0 ENCODE = 105 MSPS AIN = 71MHz & 72MHz (–7dBFS) SFDR = 74.8dBc TPC 10. Two-Tone @ 71 MHz/72 MHz 3.0 /H115461.0 LSB 1.5 0.5 0.0 /H115460.5 2.5 1.0 2.0 512 1024 1536 2048 2560 3072 3584 4096 ENCODE = 105 MSPS DNL MAX = 0.486 Codes DNL MIN = 0.431 Codes TPC 11. Differential Nonlinearity /H1154610 dBFS /H115466 /H115469 /H115462 3.0 /H115468 /H115464 MHz 270.3 300.0 /H115461 /H115467 /H115463 /H115465 ENCODE = 105 MSPS 3dB = 261MHz TPC 12. Gain Flatness

Care should be taken when placing the digital output runs. capacitive loading on the digital outputs should be minimized. the need to externally isolate the device from the receiving gate. Figure 8. Evaluation Board Mechanical Layout clocks are available at the standard 40-pin connectors J1 and J2. Power to the analog supply pins is connected via banana jacks. factory if additional layout or applications assistance is required.

REV. B AD10200 –12– Figure 9a. Evaluation Board AGNDB AGNDB VFU_B SDOUT_B REF_B AGNDB ENCBB ENCB AGNDB /H115453.3VDB D0B (LSB) D1B D2B D3B D4B D5B DGNDB AGNDA AGNDA SDOUT_A AGNDA /H115455VAA SCLK_A AGNDA ENCAB ENCA AGNDA /H115453.3VDA D11A (MSBA) D10A D9A D8A D7A DGNDA AGNDA AGNDA AINA1 AGNDA SDIN_A REF_A SCLK_B SDIN_B /H115455VAB AGNDB AGNDB VFU_A AINA2 AGNDB SHIELD AINB1 AINB2 AD10200 DGNDA D6A D5A D4A D3A D2A D1A D0A (LSBA) AGNDA AGNDB D11B (MSBB) D10B D9B D8B D7B D6B DGNDB C37 DNS AGNDA AGNDA SMA AGNDA SMA DNS AGNDA (NC) 0.1/H9262F C33 AGNDA E49 AGNDA SMA AGNDB SMA DNS AGNDB (NC) /H115455VAB_ AGNDB (NC) AGNDA LID AGNDA AGNDB C36 DNSAGNDB AGNDB NC 0.1/H9262F C35 AGNDB E50 AGNDB ENCBB ENCB AGNDB D0B D1B D2B D3B D4B D5B DGNDB C18 0.1/H9262F U17 DGNDB DUT_3.3VDB D0A DUT_3.3VDA C10 0.1/H9262F DGNDA /H115455VAA_ C34 0.1/H9262F AGNDA AGNDA AGNDA NC NC AGNDA ENCAB ENCA AGNDA D11A D10A D9A D8A D7A DGNDA AGNDA AGNDA DGNDA D6A D5A D4A D3A D2A D1A D10B D9B D8B D7B D6B DGNDB AGNDA AGNDB D11B C20 0.1/H9262F AGNDA /H115455AA_ C21 0.1/H9262F AGNDB /H115455AB_ 47/H9024 /H1155020% @100MHz 10/H9262F AGNDA /H11545 /H115455AA DUT_3.3VDA 47/H9024 /H1155020% @100MHz C12 0.1/H9262F DGNDA C29 10/H9262F /H115453.3VDA /H11545 E25 47/H9024 /H1155020% @100MHz 10/H9262F AGNDB /H11545 /H115455AB DUT_3.3VDB 47/H9024 /H1155020% @100MHz C16 0.1/H9262F DGNDB C30 10/H9262F /H115453.3VDB /H11545 E26 DGNDA H40DM (MSB) B11A B10A B9A B8A B7A B6A B5A B4A B3A B2A B1A (LSB) B0A F3A F2A F1A F0A DGNDA R71 50/H9024 BUFLATA C15 10/H9262F DGNDA /H11545 /H115453.3VDA DGNDB H40DM (MSB) B11B B10B B9B B8B B7B B6B B5B B4B B3B B2B B1B (LSB) B0B F3B F2B F1B F0B DGNDB R72 50/H9024 BUFLATB C14 10/H9262F DGNDB /H11545 /H115453.3VDB R18 100/H9024 B11B (MSB) R17 100/H9024B10B OE2 O15 O14 GND O13 O12 VCC O11 O10 GND GND VCC GND OE1 U17 74LCX16374 LE2 I15 I14 GND I13 I12 VCC I11 I10 GND GND VCC GND LE1 DUT_3.3VDB DGNDB DGNDB DGNDB DUT_3.3VDB DGNDB DGNDB DGNDB R16 100/H9024 B9B R45 100/H9024 B6B R46 100/H9024B5B R14 100/H9024 B3B R40 100/H9024B8B R44 100/H9024 B7B R15 100/H9024 B4B R13 100/H9024B2B R24 100/H9024B1B (LSB) R23 100/H9024 B0B R22 DNS F3B R20 DNS F1B R21 DNS F2B R19 DNS F0B DGNDB DGNDB DGNDB DGNDB DUT_3.3VDB (LSB) D0A D1A D2A D3A D4A D5A D6A D7A D8A D9A D10A D11A DUT_3.3VDB R53 0/H9024 R54 0/H9024 R49 0/H9024 R50 0/H9024 DGNDB 50/H9024 LATCHB R18 100/H9024 B11A (MSB) R17 100/H9024B10A OE2 O15 O14 GND O13 O12 VCC O11 O10 GND GND VCC GND OE1 U16 74LCX16374 LE2 I15 I14 GND I13 I12 VCC I11 I10 GND GND VCC GND LE1 DUT_3.3VDA DGNDA DGNDA DGNDA DUT_3.3VDA DGNDA DGNDA DGNDA R16 100/H9024B9A R45 100/H9024 B6A R46 100/H9024 B5A R14 100/H9024 B3A R40 100/H9024 B8A R44 100/H9024 B7A R15 100/H9024 B4A R13 100/H9024 B2A R24 100/H9024 B1A (LSB) R23 100/H9024 B0A R22 DNS F3A R20 DNS F1A R21 DNS F2A R19 DNS F0A DGNDA DGNDA DGNDA DGNDA DUT_3.3VDA (LSB) D0A D1A D2A D3A D4A D5A D6A D7A D8A D9A D10A D11A DUT_3.3VDA R52 0/H9024 R51 0/H9024 R47 0/H9024 R48 0/H9024 DGNDA 50/H9024 LATCHA NC = NO CONNECT

REV. B AD10200 –13– DGNDA E42 E44 E48 E67 E70 E72 E73 E76 E81 E41 E43 E47 E68 E69 E71 E74 E75 E82 AGNDA E65E66 DGNDB E36 E38 E40 E79 E84 E35 E37 E39 E80 E83 AGNDB E29 E30 E46E45 SO2 SO5 SO3 SO6 SO1 SO4 STAND OFFS ON THE BOARD E33 DGNDB DGNDB DGNDB AGNDB AGNDA E34 DGNDA DGNDA DGNDA BANANA JACKS FOR GNDS AND PWRS

2 IN+5VAA_

D DB VBB VCC Q QB VEE MC10EL16 AGNDA R56 33k/H9024 R58 33k/H9024 DGNDA 0.1/H9262F 100/H9024 DGNDA NC D DB VBB VCC Q QB VEE DGNDA +3.3VA 100/H9024 DGNDA R41 50/H9024 AGNDA J12 SMA C2 0.1/H9262F 0.1/H9262F 50/H9024 AGNDA ENCODE SMA AGNDA C13 0.47/H9262F AGNDA +3.3VA AGNDA R42 100/H9024 R43 100/H9024 ENCAB ENCAB 0.1/H9262F 0.1/H9262F AGNDA D0B D1B VCC VEE MC100EPT23 DGNDA +3.3VA 0.1/H9262F DGNDA E23 E19 LATCHA BUFLATA

2 IN+5VAB_

D DB VBB VCC Q QB VEE MC10EL16 U11 AGNDB R38 33k/H9024 R39 33k/H9024 DGNDB C25 0.1/H9262F 100/H9024 DGNDA NC D DB VBB VCC Q QB VEE MC10EL16 DGNDB +3.3VDB R66 100/H9024 DGNDB R61 50/H9024 AGNDB J11 SMA C23 0.1/H9262F C22 0.1/H9262F R60 50/H9024 AGNDB J10 ENCODE SMA AGNDB C27 0.47/H9262F AGNDB +3.3VB AGNDB R63 100/H9024 R64 100/H9024 ENCBB ENCB C24 0.1/H9262F C28 0.1/H9262F AGNDB D0B D1B VCC VEE MC100EPT23 DGNDB +3.3VB C26 0.1/H9262F DGNDB E24 E22 LATCHB BUFLATB U10 NC = NO CONNECT NC = NO CONNECT MC10EL16 Figure 9b. Evaluation Board

REV. B AD10200 –14– BILL OF MATERIALS LIST FOR AD10200 EVAL BOARD Qty. Component Name Ref Des Value Description M/S P/Ns 2 74LCX16373MTD U16, U17 74LCX16374MTD (Fairchild)

1 AD10200BZ U1 AD10200BZ

2 ADP3330 U14, U15 SM 3.3 V Regulator ADP3330ART-3.3-RL7 (Analog)

4 BRES0805 R38, R39, R56, R58 33 k Ω SM 0805 Resistor ERJ6GEYJ333V (Panasonic)

4 BRES0805 R1, R41, R60, 50 Ω SM 0805 Resistor ERJ6GEYJ510V (Panasonic)

8 BRES0805 R3, R4, R42, R43, 100 Ω SM 0805 Resistor ERJ6GEYJ101V (Panasonic)

R63, R64, R65, R66 23 CAP2 C1, C2, C5, C6, 0.1 µF SM 0805 Capacitor GRM40X7R104K025BL C7, C8, C9, C10, (MENA) C12, C16, C17, C18, C20, C21, C22, C23, C24, C25, C26, C28, C33, C34, C35 4 CAP2 C13, C27, C38, C39 0.47 µF SM 1206 Capacitor VJ1206U474MFXMB (VITRAMON)

2 N49DM J1, J2 2×20×100 Male Connector TSW-120-08G-D (Samtec)

4 IND2 L1, L2, L3, L4 47 Ω Inductor 2743019447 (Fair Ride)

4 MC10EL16 U2, U3 U9, U11 MC1016EP16D (Motorola)

10 BJACK BJ1 – BJ10 POWER JACK 108-0740-001 (Johnson Comp.)

2 MC100ELT23 U4, U10 SY100ELT23L (Micrel-Synergy)

6 POLCAP2 C3, C4, C14, C15, 10 µF SM 1812 Polar Capacitor T491C106M016A57280

C29, C30 (KEMET)

8 RES2 R47, R48, R49, 0 Ω SM 0805 Resistor ERJ-6GEY0R00V (Panasonic)

R50, R51, R52, R53, R54

4 RES4 R7, R8, R71, R72 50 Ω SM 0805 Resistor ERJ-6GEYJ510V (Panasonic)

24 RES2 R9, R10, R11, R12,

R13, R14, R15, R16, R17, R18, R23, R24, R25, R26, R27, R28, R29, R30, R35, R36, R40, R44, R45, R46

1 SMA J4 A

INA2 142-0701-201 (Johnson Comp.) 1 SMA J7 AINB2 142-0701-201 (Johnson Comp.) 2 SMA J11, J12 ENCODE 142-0701-201 (Johnson Comp.) 2 SMA J5, J10 ENCODE 142-0701-201 (Johnson Comp.) 4 Stand-Off S01–S04 Stand-Off 313-2477-016 (Johnson Comp.)

4 Screws Screws (Stand-Off) MPMS 0040005PH (Building

Fasteners) 1 PCB AD10200 Eval Board GS03363 Rev. A

Figure 8. 68-Lead Ceramic Leaded Chip Carrier [CLCC] registered trademarks are the prop erty of their respective owners.