ACTS74MS RENESAS | Alldatasheet
Document overview
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Technical content
Features
- Devices QML Qualified in Accordance with MIL-PRFF-38535 Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96713 and Intersil’s QM Plan 1.25 Micron Radiation Hardened SOS CMOS Single Event Upset (SEU) Immunity: <1 x 10 -10 Errors/Bit/Day (Typ) Latch-Up Free Under Any Conditions Significant Power Reduction Compared to ALSTTL Logic Input Logic Levels - VIL = 0.8V Max - VIH = VCC/2 Min Input Current ≤ 1µA at VOL, VOH
Description
The Intersil ACTS74MS is a Radiation Hardened Dual D Flip Flop with Set(s) and Reset (R). The logic level at data input is transferred to the output during the positive transition of the clock. The Set and Reset are independent from the clock and accomplished by a low level on the appropriate input. The ACTS74MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic Family. The ACTS74MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or a 14 Lead Ceramic Dual-In-Line Package (D suffix). January 1996
Ordering Information
PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE 5962F9671301VCC -55 oC to +125oC MIL-PRF-38535 Class V 14 Lead SBDIP 5962F9671301VXC -55 oC to +125oC MIL-PRF-38535 Class V 14 Lead Ceramic Flatpack ACTS74D/Sample 25 oC Sample 14 Lead SBDIP ACTS74K/Sample 25 oC Sample 14 Lead Ceramic Flatpack ACTS74HMSR 25 oCD i e D i e Spec Number 518787 File Number 3382.1 itle CTS MS) t adia- n rd- ed al D p p th t and set) thor ey- rds ter- mi- ctor, dia- n rd- ed, d rd, tel- ass CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143| Intersil and Design is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001, All Rights Reserved
L L X X H (Note 2) H (Note 2) HH HHL HH L LH H H L X Q0 Q0 H = High Level (Steady State) L = Low Level (Steady State) X = Don’t Care = Transition from Low to High Level NOTES: 1. Q0 = the level of Q before the indicated input conditions were es- tablished. 2. This configuration is nonstable, that is, it will not persist when set and reset inputs return to their inactive (high) level. 4(10) P N2(12) CL CL P N CL CL 3(11) P N CL CL P N CL CL CL CL 6(8) 5(9) Q Q Cp R 1(13) D S Spec Number 518787 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli- able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com
DIE DIMENSIONS: 88 mils x 88 mils 2240mm x 2240mm METALLIZATION: Type: AlSi Metal 1 Thickness: 7.125k Å ±1.125kÅ Metal 2 Thickness: 9kÅ ±1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ WORST CASE CURRENT DENSITY: <2.0 x 105A/cm2 BOND PAD SIZE: 110µm x 110µm 4.3 mils x 4.3 mils Metallization Mask Layout ACTS74MS R1 VCC R2 (1) (14) (13) (2) CP1 (3) S1 (4) Q1 (5) NC (7)(6) (8) Q1 GND Q2 (9) (12) D2 (11) CP2 (10) S2 NC Spec Number 518787