ACTS630MS INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Devices QML Qualified in Accordance with MIL-PRF-38535
  • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96721 and Intersil’s QM Plan
  • 1.25 Micron Radiation Hardened SOS CMOS
  • Single Event Upset (SEU) Immunity: <1 x 10 -10 Errors/Bit/Day (Typ)
  • Latch-Up Free Under Any Conditions oC to +125oC
  • Significant Power Reduction Compared to ALSTTL Logic
  • Input Logic Levels - VIL = 0.8V Max - VIH = VCC/2 Min
  • Input Current≤ 1µA at VOL, VOH

Description

The Intersil ACTS630MS is a Radiation Hardened 16-bit parallel error detection and correction circuit. It uses a modified Hamming code to generate a 6-bit check word from each 16-bit data word. The check word is stored with the data word during a memory write cycle; during a memory read cycle a 22-bit word is taken form memory and checked for errors. Single bit errors in the data words are flagged and corrected. Sin- gle bit errors in check words are flagged but not corrected. The position of the incorrect bit is pinpointed, in both cases, by the 6-bit error syndrome code which is output during the error correction cycle. The ACTS630MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic Family. The ACTS630MS is supplied in a 28 lead Ceramic Flatpack (K suffix) or a 28 Lead Ceramic Dual-In-Line Package (D suffix). January 1996

Ordering Information

PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE 5962F9672101VXC -55 oC to +125oC MIL-PRF-38535 Class V 28 Lead SBDIP 5962F9672101VYC -55 oC to +125oC MIL-PRF-38535 Class V 28 Lead Ceramic Flatpack ACTS630D/Sample 25 oC Sample 28 Lead SBDIP ACTS630K/Sample 25 oC Sample 28 Lead Ceramic Flatpack ACTS630HMSR 25 oC Die Die Pinouts

28 PIN CERAMIC DUAL-IN-LINE, MIL-STD-1835

DESIGNATOR CDIP-T28, LEAD FINISH C TOP VIEW

28 PIN CERAMIC FLATPACK, MIL-STD-1835

DESIGNATOR CDFP3-F28, LEAD FINISH C TOP VIEW DEF DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 GND VCC CB0 CB1 CB3 CB5 DB15 DB14 DB13 DB12 SEF CB2 CB4 DEF DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 GND VCC SEF CB0 CB1 CB2 CB3 CB4 CB5 DB15 DB14 DB13 DB12 Spec Number 518786 File Number 3204.1

EDAC FUNCTION DATA I/O CHECKWORD ERROR FLAGS S1 S0 SEF DEF WRITE Low Low Generates Checkword Input Data Output Checkword Low Low READ Low High Read Data and Check- word Input Data Input Checkword Low Low READ High High Latch and Flag Error Latch Data Latch Checkword Enabled Enabled READ High Low Correct Data Word and Generate Syndrome Bits Output Corrected Data Output Syndrome Bits Enabled Enabled Check Word Generation CHECKWORD BIT 16-BIT DATA WORD 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 C B 0 XX XX XXX X C B 1 XX XX XX X X CB2 X X X X X X X X C B 3 XXX XX XXX C B 4 XXXXX XXX C B 5 XXXXXXXX NOTE: The six check bits are parity bits derived from the matrix of data bits as indicated by “x” for each bit Error Syndrome Codes SYNDROME ERROR CODE ERROR LOCATIONS DB CB NO ERROR0123456789 1 0 1 1 1 2 1 3 1 4 1 5 012345 C B 0 L LHL LHHHL L LHHLHHLHHHHH H C B 1 LHL LHL LHLHHLHHLHHLHHHH H C B 2 HLLHLLHLHLHHLHHLHHLHHH H C B 3 L L LHHHL LHHL L LHHHHHHLHH H C B 4 H H HLLLLL HHHHHL L LHHHHLH H C B 5 HHHHHHHH LLLLLLLL HHHHHL H Error Functions TOTAL NUMBER OF ERRORS ERROR FLAGS DATA CORRECTION16-BIT DATA 6-BIT CHECKWORD SEF DEF 0 0 Low Low Not Applicable 1 0 High Low Correction 0 1 High Low Correction 1 1 High High Interrupt 2 0 High High Interrupt 0 2 High High Interrupt Spec Number 518786

DIE DIMENSIONS: 171 mils x 159 mils 6.7µm x 6.3µm METALLIZATION: Type: Al/Si/ Metal 1 Thickness: 7.125k Å ±1.125kÅ Metal 2 Thickness: 9kÅ ±1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ WORST CASE CURRENT DENSITY: < 2.0 x 105A/cm2 BOND PAD SIZE: 110µm x 110µm 4.3 mils x 4.3 mils Metallization Mask Layout ACTS630MS DEFDB0DB1DB2 VCC SEF S1 DB3 (5) DB4 (6) DB5 (7) DB6 (8) DB7 (9) DB8 (10) DB9 (11) (25) S0 (24) CB0 (23) CB1 (22) CB2 (21) CB3 (20) CB4 (19) CB5 DB10 DB11 GND DB12 DB13 DB14 DB15 Spec Number 518786

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 ACTS630MS Spec Number