ACTS573MS INTERSIL | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 3
Technical content
Features
- Devices QML Qualified in Accordance with MIL-PRF-38535
- Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96725 and Intersil’s QM Plan
- 1.25 Micron Radiation Hardened SOS CMOS
- Single Event Upset (SEU) Immunity: <1 x 10 -10 Errors/Bit/Day (Typ)
- Latch-Up Free Under Any Conditions oC to +125oC
- Significant Power Reduction Compared to ALSTTL Logic
- Input Logic Levels - VIL = 0.8V Max - VIH = VCC/2 Min
- Input Current≤ 1µA at VOL, VOH
Description
The Intersil ACTS573MS is a Radiation Hardened Octal Transparent Latch with an active low output enable. The outputs are transparent to the inputs when the latch enable ( LE) is High. When the latch goes low the data is latched. The output enable controls the three-state outputs. When the output enable pins ( OE) are high the output is in a high impedance state. The latch operation is independent of the state of output enable. The ACTS573MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic family. The ACTS573MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or a Ceramic Dual-In-Line package (D suffix). January 1996
Ordering Information
PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE 5962F9672501VRC -55 oC to +125oC MIL-PRF-38535 Class V 20 Lead SBDIP 5962F9672501VXC -55 oC to +125oC MIL-PRF-38535 Class V 20 Lead Ceramic Flatpack ACTS573D/Sample 25 oC Sample 20 Lead SBDIP ACTS573K/Sample 25 oC Sample 20 Lead Ceramic Flatpack ACTS573HMSR 25 oC Die Die Spec Number 518892 File Number 4092
NOTE: L = Low Logic Level, H = High Logic Level, X = Don’t Care, Z = High Impedance, l = Low Voltage Level Prior to High-to-Low Latch Enable Transition, h = High Voltage Level Prior to High-to-Low Latch Enable Transition. VCC Qn p LE LE Dn p n LE LE OE p n LE LE LE OE OE OE nOE VSS
1 OF 8 IDENTICAL CIRCUITS
All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com
DIE DIMENSIONS: 102 mils x 102 mils 2,600mm x 2,600mm METALLIZATION: Type: AlSi Metal 1 Thickness: 7.125k Å ±1.125kÅ Metal 2 Thickness: 9kÅ ±1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ WORST CASE CURRENT DENSITY: <2.0 x 105 A/cm2 BOND PAD SIZE: > 4.3 mils x 4.3 mils > 110µm x 110µm Metallization Mask Layout ACTS573MS (1)OE (2) D0 (20) VCC (16) Q3 GND (10) LE (11) Q7 (12) NC D2 (4) D6 (8) (14) Q5 (15) Q4 D3 (5) NC D4 (6) NC D5 (7) D7 (9) Q6 (13) (17) Q2 NC (3) D1 (18) Q1 (19) Q0 Spec Number 518892