ACTS161MS RENESAS | Alldatasheet

Document overview

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Technical content

Features

  • Devices QML Qualified in Accordance with MIL-PRF-38535
  • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96716 and Intersil’s QM Plan
  • 1.25 Micron Radiation Hardened SOS CMOS
  • Total Dose >300K RAD (Si)
  • Single Event Upset (SEU) Immunity: <1 x 10 -10 Errors/ Bit/Day (Typ)
  • SEU LET Threshold>100 MEV-cm2/mg
  • Dose Rate Upset>1011 RAD (Si)/s, 20ns Pulse
  • Dose Rate Survivability>1012 RAD (Si)/s, 20ns Pulse
  • Latch-Up Free Under Any Conditions
  • Military Temperature Range-55 oC to +125oC
  • Significant Power Reduction Compared to ALSTTL Logic
  • DC Operating Voltage Range 4.5V to 5.5V
  • Input Logic Levels - VIL = 0.8V Max - VIH = VCC/2 Min
  • Input Current  1A at VOL, VOH
  • Fast Propagation Delay25ns (Max), 16ns (Typ)

Description

The Intersil ACTS161MS is a Radiation Hardened 4-Bit Binary Syn- chronous Counter, featuring asynchronous reset and load ahead carry logic. The MR is an active low master reset. SPE is an active low Synchronous Parallel Enable which disables counting and allows data at the preset inputs (P0 - P3) to load the counter. CP is the positive edge clock. TC is the terminal count or carry output. Both TE and PE must be high for counting to occur, but are irrele- vant to loading. TE low will keep TC low. The ACTS161MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic family. The ACTS161MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or a Ceramic Dual-In-Line Package (D suffix). Pinouts

16 PIN CERAMIC DUAL-IN-LINE

MIL-STD-1835, DESIGNATOR CDIP2-T16, LEAD FINISH C TOP VIEW

16 PIN CERAMIC FLATPACK

MIL-STD-1835, DESIGNATOR CDFP4-F16, LEAD FINISH C TOP VIEW CP GND PE VCC TE SPE TC MR 11 6 MR CP PE GND VCC TC TE SPE

Ordering Information

PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE 5962F9671601VEC -55 oC to +125oC MIL-PRF-38535 Class V 16 Lead SBDIP 5962F9671601VXC -55 oC to +125oC MIL-PRF-38535 Class V 16 Lead Ceramic Flatpack ACTS161D/Sample 25 oC Sample 16 Lead SBDIP ACTS161K/Sample 25 oC Sample 16 Lead Ceramic Flatpack ACTS161HMSR 25 oCD i e D i e

FN4095 Rev.0.00 Page 2 of 4 January 1996 Functional Diagram CP MR P D3 TC TE CP MR P D2 CP MR P D1 MR Q1 CP MR P D0 Q0 GND SPE CP TE PE TE Q3Q2Q1Q0 TRUTH TABLE OPERATING MODE INPUTS OUTPUTS MR CP PE TE SPE PN QN TC Reset (Clear) L X X X X X L L Parallel Load H X X I I L L H X X I h H (Note 1) Count H h h h (Note 3) X count (Note 1) Inhibit H X I (Note 2) X h (Note 3) X q N (Note 1) H X X I (Note 2) h (Note 3) X q N L H = High Steady State, L = Low Steady State, h = High voltage level one setup time prior to the Low-to-High clock transition, I = Low volt- age level one setup time prior to the Low-to-High clock transition, X = Don’t Care,q = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition, = Low-to-Hig h Transition. NOTES: 1. The TC output is High when TE is High and the counter is at Terminal Count (HHHH). 2. The High-to-Low transition of PE or TE should only occur while CP is High for conventional operation. 3. The Low-to-High transition of SPE should only occur while CP is High for conventional operation.

FN4095 Rev.0.00 Page 3 of 4 January 1996 Die Characteristics DIE DIMENSIONS: 88 mils x 88 mils 2240mm x 2240mm METALLIZATION: Type: AlSi Metal 1 Thickness: 7.125k Å 1.125kÅ Metal 2 Thickness: 9kÅ 1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ 1kÅ WORST CASE CURRENT DENSITY: < 2.0 x 105A/cm2 BOND PAD SIZE: 110m x 110m 4.3 mils x 4.3 mils Metallization Mask Layout ACTS161MS MR VCC TC (1) (16) (15) CP (2) P0 (3) P1 (4) P2 (5) P3 (6) (8)(7) (9) PE GND SPE (10) TE (14) Q0 (13) Q1 (12) Q2 (11) Q3

FN4095 Rev.0.00 Page 4 of 4 January 1996 ACTS161MS Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 1999. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners.