ACT7881

SN74ACT7881 TI | Alldatasheet

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1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227E – FEBRUARY 1993 – REVISED APRIL 1998 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Member of the Texas Instruments Widebus  Family /C0068Independent Asynchronous Inputs and Outputs /C0068Read and Write Operations Can Be Synchronized to Independent System Clocks /C0068Programmable Almost-Full/Almost-Empty Flag /C0068Pin-to-Pin Compatible With SN74ACT7882, SN74ACT7884, and SN74ACT7811 /C0068Input-Ready, Output-Ready, and Half-Full Flags /C0068Expandable in Word Width and/or Word Depth /C0068Fast Access Times of 11 ns With a 50-pF Load /C0068High Output Drive for Direct Bus Interface /C0068Package Options Include 68-Pin Plastic Leaded Chip Carrrier (FN) or 80-Pin Shrink Quad Flat (PN) Package VCC Q14 Q13 GND Q12 Q11 V CC Q10 GND V CC GND D14 D13 D12 D11 D10 V CC GND V GND 87 6 5493 D17 GND RDCLK RDEN1 RDEN2 OE RESET HF WRTCLK WRTEN1 WRTEN2 AF/AE GND IR 16 8 6 726 6 6 5 DAF GND OR V 64 63 62 61 GND Q17 Q16 GND Q15 D15 D16 CC CC FN PACKAGE (TOP VIEW) V CC V CC V CC 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Copyright  1998, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Widebus is a trademark of Texas Instruments Incorporated. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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(TOP VIEW) 22 23 VCC VCC NC GND V CC HF IR GND GND AF/AE V CC WRTEN2 WRTEN1 WRTCLK GND NC NC GND GND Q16 Q17 V CC OR GND VCC RESET OE RDEN2 RDEN1 RDCLK GND D17 D16 D15 NC NC 25 26 27 28 79 78 77 76 7580 74 Q14 Q13 GND GND Q12 Q11 D13 D12 D11 D10 V 72 71 7073 29 30 31 32 33 69 68 NC 67 66 65 64 34 35 36 37 Q15 Q10 DAF 38 39 40 GND GND 63 62 61 VCC GND D14 NC CC GND VCC VCC NC – No internal connection

description

A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ACT7881 is organized as 1024 × 18 bits. The SN74ACT7881 processes data at rates up to 67 MHz and access times of 11 ns in a bit-parallel format. Data outputs are noninverting with respect to the data inputs. Expansion is accomplished easily in both word width and word depth. The SN74ACT7881 has normal input-bus to output-bus asynchronous operation. The special enable circuitry adds the ability to synchronize independent reads and writes to their respective system clocks. The SN74ACT7881 is characterized for operation from 0°C to 70°C.

1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227E – FEBRUARY 1993 – REVISED APRIL 1998 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic symbol† RESET D15 D16 D17 Q15 Q16 Q17 IR INPUT RDY D10 D11 D12 D13 D14 Q10 Q11 Q12 Q13 Q14 Φ FIFO SN74ACT7881 – 1024 × 18 Data Data 1 WRTCLK WRTEN1 WRTEN2 RDEN1 EN1 OE RDEN2 RDCLK WRTCLK DEFINE ALMOST FULL WRTEN RDEN RESET DAF HF HALF FULL AF/AE ALMOST FULL/EMPTY OR OUTPUT RDY RDCLK † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the FN package.

1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227E – FEBRUARY 1993 – REVISED APRIL 1998

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1024 × 18 Register DAF WRTEN2 WRTEN1 WRTCLK RDEN2 RDEN1 RDCLK D0–D17 OE Q0–Q17 OR IR HF AF/AE Write Pointer Read Pointer

1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227E – FEBRUARY 1993 – REVISED APRIL 1998 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL † I/O DESCRIPTION NAME NO. I/O DESCRIPTION AF/AE 33 O Almost-full/almost-empty flag. The AF/AE boundary is defined by the AF/AE offset value (X). This value can be programmed during reset, or the default value of 256 can be used. AF/AE is high when the FIFO contains (X + 1) or fewer words or (1025 – X) or more words. AF/AE is low when the FIFO contains between (X + 2) and (1024 – X) words. Programming procedure for AF/AE – The AF/AE flag is programmed during each reset cycle. The AF/AE offset value (X) is either a user-defined value or the default of X = 256. Instructions to program AF/AE using both methods are as follows: User-defined X Step 1: Take DAF from high to low. Step 2: If RESET is not already low, take RESET low. Step 3: With DAF held low, take RESET high. This defines the AF/AE using X. Step 4: To retain the current offset for the next reset, keep DAF low. Default X To redefine AF/AE using the default value of X = 256, hold DAF high during the reset cycle. DAF 27 I Define-almost-full. The high-to-low transition of DAF stores the binary value of data inputs as the AF/AE offset value (X). With DAF held low, a low pulse on RESET defines the AF/AE flag using X. D0–D17 26–19, 17, 15–7 I Data inputs for 18-bit-wide data to be stored in the memory. A high-to-low transition of DAF captures data for the AF/AE offset (X) from D8–D0. HF 36 O Half-full flag. HF is high when the FIFO contains 512 or more words and is low when the number of words in memory is less than half the depth of the FIFO. IR 35 O Input-ready flag. IR is high when the FIFO is not full and low when the device is full. During reset, IR is driven low on the rising edge of the second WRTCLK pulse. IR is then driven high on the rising edge of the second WRTCLK pulse after RESET goes high. After the FIFO is filled and IR is driven low, IR is driven high on the second WRTCLK pulse after the first valid read. OE 2 I Output enable. The Q0–Q17 outputs are in the high-impedance state when OE is low. OE must be high before the rising edge of RDCLK to read a word from memory. OR 66 O Output-ready flag. OR is high when the FIFO is not empty and low when the FIFO is empty. During reset, OR is set low on the rising edge of the third RDCLK pulse. OR is set high on the rising edge of the third RDCLK pulse to occur after the first word is written into the FIFO. OR is set low on the rising edge of the first RDCLK pulse after the last word is read. Q0–Q17 38–39, 41–42, 44, 46–47, 49–50, 52–53, 55–56, 58–59, 61, 63–64 O Data outputs. The first data word to be loaded into the FIFO is moved to Q0–Q17 on the rising edge of the third RDCLK pulse to occur after the first valid write. RDEN1 and RDEN2 do not affect this operation. Following data is unloaded on the rising edge of RDCLK when RDEN1, RDEN2, OE, and OR are high. RDCLK 5 I Read clock. Data is read out of memory on the low-to-high transition of RDCLK if OR, OE, RDEN1, and RDEN2 are high. RDCLK is a free-running clock and functions as the synchronizing clock for all data transfers out of the FIFO. OR also is driven synchronously with respect to the RDCLK signal. RDEN1 RDEN2 I Read enable. RDEN1 and RDEN2 must be high before a rising edge on RDCLK to read a word out of memory. RDEN1 and RDEN2 are not used to read the first word stored in memory. RESET 1 I Reset. A reset is accomplished by taking RESET low and generating a minimum of four RDCLK and WRTCLK cycles. This ensures that the internal read and write pointers are reset and that OR, HF, and IR are low, and AF/AE is high. The FIFO must be reset upon power up. With DAF at a low level, a low pulse on RESET defines AF/AE using the AF/AE offset value (X), where X is the value previously stored. With DAF at a high level, a low-level pulse on RESET defines the AF/AE flag using the default value of X = 256. WRTCLK 29 I Write clock. Data is written into memory on a low-to-high transition of WRTCLK if IR, WRTEN1, and WRTEN2 are high. WRTCLK is a free-running clock and functions as the synchronizing clock for all data transfers into the FIFO. IR also is driven synchronously with respect to WRTCLK. WRTEN1 WRTEN2 I Write enable. WRTEN1 and WRTEN2 must be high before a rising edge on WRTCLK for a word to be written into memory. WRTEN1 and WRTEN2 do not affect the storage of the AF/AE offset value (X). † Terminals listed are for the FN package.

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† X is the binary value on D8–D0. Figure 1. Reset Cycle: Define AF/AE Flag Using a Programmed Value of X

Figure 2. Reset Cycle: Define AF/AE Flag Using the Default Value of X = 256

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Figure 3. Write Cycle

Figure 4. Read Cycle

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absolute maximum ratings over operating free-air temperature range† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions MIN MAX UNIT VCC Supply voltage 4.5 5.5 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V IOH High-level output current –8 mA IOL Low-level output current 16 mA TA Operating free-air temperature 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP ‡ MAX UNIT VOH VCC = 4.5 V, IOH = –8 mA 2.4 V VOL VCC = 4.5 V, IOL = 16 mA 0.5 V II VCC = 5.5 V, VI = VCC or 0 ±5 µA IOZ VCC = 5.5 V, VO = VCC or 0 ±5 µA I § VI = VCC – 0.2 V or 0 400 µA ICC § One input at 3.4 V, Other inputs at VCC or GND 1.2 mA C i VI = 0, f = 1 MHz 4 pF C o VO = 0, f = 1 MHz 8 pF ‡ All typical values are at VCC = 5 V, TA = 25°C. § ICC is tested with outputs open.

1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227E – FEBRUARY 1993 – REVISED APRIL 1998 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figures 1 through 5) ’ACT7881-15 ’ACT7881-20 ’ACT7881-30 UNIT MIN MAX MIN MAX MIN MAX UNIT fclock Clock frequency 67 50 33.4 MHz WRTCLK high 5 7 8.5 WRTCLK low 7 7 11 tw Pulse duration RDCLK high 5 7 8.5 ns RDCLK low 7 7 11 DAF high 7 7 10 D0–D17 before WRTCLK↑ 5 5 5 WRTEN1, WRTEN2 high before WRTCLK ↑ 4 5 5 OE, RDEN1, RDEN2 high before RDCLK↑ 4 5 5 tsu Setup time Reset: RESET low before first WRTCLK↑ and RDCLK ↑† 5 6 7 ns Define AF/AE: D0–D8 before DAF↓ 3 5 5 Define AF/AE: DAF↓ before RESET↑ 3 6 7 Define AF/AE (default): DAFhigh before RESET↑ 4 5 5 D0–D17 after WRTCLK↑ 0 0 0 WRTEN1, WRTEN2 high after WRTCLK↑ 0 0 0 OE, RDEN1, RDEN2 high after RDCLK↑ 0 0 0 th Hold time Reset: RESET low after fourth WRTCLK↑ and RDCLK ↑† 0 0 0 ns Define AF/AE: D0–D8 after DAF↓ 0 0 0 Define AF/AE: DAFlow after RESET↑ 0 0 0 Define AF/AE (default): DAFhigh after RESET↑ 0 0 0 † To permit the clock pulse to be utilized for reset purposes switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 5) PARAMETER FROM TO ’ACT7881-15 ’ACT7881-20 ’ACT7881-30 UNITPARAMETER (INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX UNIT fmax WRTCLK or RDCLK 67 50 33.4 MHz tpd RDCLK ↑ Any Q 3 12 3 13 3 18 ns tpd‡ RDCLK ↑ Any Q ns WRTCLK ↑ IR 2 8 2 9.5 2 12 t d RDCLK ↑ OR 2 8 2 9.5 2 12 nstpd WRTCLK ↑ AF/AE 6 17 6 19 6 22 ns RDCLK ↑ AF/AE 6 17 6 19 6 22 tPLH WRTCLK ↑ HF 6 14 6 17 6 21 ns tPHL RDCLK ↑ HF 6 14 6 17 6 21 ns tPLH RESET ↓ AF/AE 3 12 3 17 3 21 ns tPHL RESET ↓ HF 3 14 3 19 3 23 ns ten OE Any Q 2 9 2 11 2 11 ns tdis OE Any Q 2 10 2 14 2 14 ns ‡ This parameter is measured with CL = 30 pF (see Figure 6).

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3 V 3 V

NOTE A: C L includes probe and jig capacitance. Figure 5. Load Circuit and Voltage Waveforms

1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227E – FEBRUARY 1993 – REVISED APRIL 1998 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS 0 50 100 150 200 250 300 t – Propagation Delay Time – nspd PROPAGATION DELAY TIME vs LOAD CAPACITANCE C L – Load Capacitance – pF VCC = 5 V R L = 500 Ω TA = 25°C Figure 6

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APPLICATION INFORMATION

The SN74ACT7881 is expandable in both word width and word depth. Word-depth expansion is accomplished by connecting the devices in series such that data flows through each device in the chain. Figure 8 shows two SN74ACT7881 devices configured for word-depth expansion. The common clock between the devices can be tied to either the write clock (WRTCLK) of the first device or the read clock (RDCLK) of the last device. The output-ready (OR) flag of the previous device and the input-ready (IR) flag of the next device maintain data flow to the last device in the chain whenever space is available. Figure 9 shows two SN74ACT7881 devices in word-width expansion. Word-width expansion is accomplished by simply connecting all common control signals between the devices and creating composite IR and OR signals. The almost-full/almost-empty (AF/AE) flag and half-full (HF) flag can be sampled from any one device. Word-depth expansion and word-width expansion can be used together. SN74ACT7881 CLK WRTCLK WRTEN1 WRTEN2 IR D0–D17 5 V WRTCLK WRTEN1 WRTEN2 IR D0–D17 RDCLK OR RDEN1 RDEN2 OE Q0–Q17 SN74ACT7881 WRTCLK WRTEN1 WRTEN2 IR D0–D17 RDCLK RDEN1 RDEN2 OR OE Q0–Q17 RDCLK RDEN1 RDEN2 OR Q0–Q17 OE Figure 7. Word-Depth Expansion: 2048/4096/8192 × 18 Bits, N = 2 Figure 8. Word-Width Expansion: 1024 × 36 Bits

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