SN54ACT74_06 TI | Alldatasheet
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/C0083/C0078/C0053/C0052/C0065/C0067/C0084/C0055/C0052/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0052 /C0068/C0085/C0065/C0076 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 /C0068/C0262/C0084/C0089/C0080/C0069 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0067/C0076/C0069/C0065/C0082 /C0065/C0078/C0068 /C0080/C0082/C0069/C0083/C0069/C0084 SCAS520H − AUGUST 1995 − REVISED OCTOBER 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C00684.5-V to 5.5-V VCC Operation /C0068Inputs Accept Voltages to 5.5 V /C0068Max tpd of 10.5 ns at 5 V /C0068Inputs Are TTL-Voltage Compatible 1CLR 1CLK 1PRE GND VCC 2CLR 2CLK 2PRE 321 2 0 1 9 91 0 1 1 1 2 1 3 NC 2CLK NC 2PRE 1CLK NC 1PRE NC SN54ACT74 ...F K PACKAGE (TOP VIEW)1D 1CLR NC V 2CLR GND NC CC S N 5 4 A C T 7 4 ...J O R W PACKAGE SN74ACT74 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) NC − No internal connection description/ordering information The ’ACT74 dual positive-edge-triggered devices are D-type flip-flops. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.
ORDERING INFORMATION
TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube SN74ACT74N SN74ACT74N SOIC − D Tube SN74ACT74D ACT74SOIC − D Tape and reel SN74ACT74DR ACT74 −40°C to 85°C SOP − NS Tape and reel SN74ACT74NSR ACT74−40 C to 85C SSOP − DB Tape and reel SN74ACT74DBR AD74 TSSOP − PW Tube SN74ACT74PW AD74TSSOP − PW Tape and reel SN74ACT74PWR AD74 CDIP − J Tube SNJ54ACT74J SNJ54ACT74J −55°C to 125°C CFP − W Tube SNJ54ACT74W SNJ54ACT74W−55 C to 125C LCCC − FK Tube SNJ54ACT74FK SNJ54ACT74FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2003, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0079/C0110 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0109/C0112/C0108/C0105/C0097/C0110/C0116 /C0116/C0111 /C0077/C0073/C0076/C0262/C0080/C0082/C0070/C0262/C0051/C0056/C0053/C0051/C0053/C0044 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115 /C0097/C0114/C0101 /C0116/C0101/C0115/C0116/C0101/C0100 /C0117/C0110/C0108/C0101/C0115/C0115 /C0111/C0116/C0104/C0101/C0114/C0119/C0105/C0115/C0101 /C0110/C0111/C0116/C0101/C0100/C0046 /C0079/C0110 /C0097/C0108/C0108 /C0111/C0116/C0104/C0101/C0114 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115/C0044 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
/C0083/C0078/C0053/C0052/C0065/C0067/C0084/C0055/C0052/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0052 /C0068/C0085/C0065/C0076 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 /C0068/C0262/C0084/C0089/C0080/C0069 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0067/C0076/C0069/C0065/C0082 /C0065/C0078/C0068 /C0080/C0082/C0069/C0083/C0069/C0084 SCAS520H − AUGUST 1995 − REVISED OCTOBER 2003
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(each flip-flop) INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H LXXL H L LXX H † H † H H ↑ HH L H H ↑ LL H H H L X Q 0 Q 0 † This configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. logic diagram, each flip-flop (positive logic) C C C C C C C C TGTGTG TG Q Q PRE CLK D CLR C C
/C0083/C0078/C0053/C0052/C0065/C0067/C0084/C0055/C0052/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0052 /C0068/C0085/C0065/C0076 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 /C0068/C0262/C0084/C0089/C0080/C0069 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0067/C0076/C0069/C0065/C0082 /C0065/C0078/C0068 /C0080/C0082/C0069/C0083/C0069/C0084 SCAS520H − AUGUST 1995 − REVISED OCTOBER 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54ACT74 SN74ACT74 UNITMIN MAX MIN MAX UNIT VCC Supply voltage 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V IOH High-level output current −24 −24 mA IOL Low-level output current 24 24 mA ∆t/∆v Input transition rise or fall rate 8 8 ns/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
/C0083/C0078/C0053/C0052/C0065/C0067/C0084/C0055/C0052/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0052 /C0068/C0085/C0065/C0076 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 /C0068/C0262/C0084/C0089/C0080/C0069 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0067/C0076/C0069/C0065/C0082 /C0065/C0078/C0068 /C0080/C0082/C0069/C0083/C0069/C0084 SCAS520H − AUGUST 1995 − REVISED OCTOBER 2003
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C SN54ACT74 SN74ACT74 UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT IOH = −50 A VOH IOH = −24 mA 4.5 V 3.86 3.7 3.76 VVOH IOH = −24 mA 5.5 V 4.86 4.7 4.76 V IOH = −50 mA† 5.5 V 3.86 IOH = −75 mA† 5.5 V 3.85 IOL = 50 A VOL IOL = 24 mA 4.5 V 0.36 0.5 0.44 VVOL IOL = 24 mA 5.5 V 0.36 0.5 0.44 V IOL = 50 mA† 5.5 V 1.65 IOL = 75 mA† 5.5 V 1.65 II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA ICC VI = VCC or GND, IO = 0 5.5 V 2 40 20 µA ∆ICC ‡ One input at 3.4 V, Other inputs at GND or VCC 5.5 V 0.6 1.6 1.5 mA C i VI = VCC or GND 5 V 3 pF † Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms. ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC . timing characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) TA = 25°C SN54ACT74 SN74ACT74 UNITMIN MAX MIN MAX MIN MAX UNIT fclock Clock frequency 145 85 125 MHz tw Pulse duration PRE or CLR low 5 7 6 nstw Pulse duration CLK 5 7 6 ns tsu Setup time, data before CLK↑ Data 3 4 3.5 nstsu Setup time, data before CLK↑ PRE or CLR inactive 0 0.5 0 ns th Hold time, data after CLK↑ 1 1 1 ns switching characteristics over recommended operating free-air temperature (unless otherwise noted) (see Figure 1) FROM TO SN54ACT74 PARAMETER FROM (INPUT) TO (OUTPUT) TA = 25°C MIN MAX UNITPARAMETER (INPUT) (OUTPUT) MIN TYP MAX MIN MAX UNIT fmax 145 210 85 MHz tPLH PRE or CLR Q or Q 1 5.5 9.5 1 11.5 nstPHL PRE or CLR Q or Q 1 6 10 1 12.5 ns tPLH CLK Q or Q 1 7.5 11 1 14 ns tPHL CLK Q or Q 1 6 10 1 12 ns
NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-8752501M2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type 5962-8752501MCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type 5962-8752501MDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type SN74ACT74D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT74DBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI SN74ACT74DBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT74DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT74DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT74DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT74DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT74N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ACT74NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ACT74NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT74NSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT74PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT74PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT74PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI SN74ACT74PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT74PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54ACT74FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type SNJ54ACT74J ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type SNJ54ACT74W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Addendum-Page 1
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Addendum-Page 2
MLCC006B – OCTOBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 4040140/D 10/96
28 TERMINAL SHOWN
B 0.358 (9,09) MAX (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) ANO. OF MINMAX 0.358 0.660 0.761 0.458 0.342 (8,69) MIN (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32)(18,78) 0.020 (0,51) TERMINALS 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 121314151618 17 432 0.020 (0,51) 0.010 (0,25) 12826 27 B SQ A SQ 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01
28 PINS SHOWN
8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153
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