ACT72211L-15

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/C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0049/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0050/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0051/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0052/C0049/C0076 /C0053/C0049/C0050 × /C0057/C0044 /C0049/C0048/C0050/C0052 × /C0057/C0044 /C0050/C0048/C0052/C0056 × /C0057/C0044 /C0065/C0078/C0068 /C0052/C0048/C0057/C0054 × /C0057 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0070/C0073/C0082/C0083/C0084/C0262/C0073/C0078/C0044 /C0070/C0073/C0082/C0083/C0084/C0262/C0079/C0085/C0084 /C0077/C0069/C0077/C0079/C0082/C0073/C0069/C0083 SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Read and Write Clocks Can Be Asynchronous or Coincident /C0068Organization: − SN74ACT72211L − 512× 9 − SN74ACT72221L − 1024× 9 − SN74ACT72231L − 2048× 9 − SN74ACT72241L − 4096× 9 /C0068Write and Read Cycle Times of 15 ns /C0068Bit-Width Expandable /C0068Empty and Full Flags /C0068Programmable Almost-Empty and Almost-Full Flags With Default Offsets of Empty+7 and Full−7, Respectively /C0068TTL-Compatible Inputs /C0068Fully Compatible With the IDT72211/72221/72231/72241 /C0068Available in 32-Pin Plastic J-Leaded Chip Carrier (RJ)

description

The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241L are constructed with CMOS dual-port SRAM and are arranged as 512, 1024, 2048, and 4096 9-bit words, respectively. Internal write and read address counters provide data throughput on a first-in, first-out (FIFO) basis. Full and empty flags prevent memory overflow and underflow, and two programmable flags (almost full and almost empty) are provided. The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241L are synchronous FIFOs, which means the data input port and data output port each employ synchronous control. Write-enable (WEN1 WEN2/LD ) signals allow the low-to-high transition of the write clock (WCLK) to store data in memory, and read-enable (REN1, REN2) signals allow the low-to-high transition of the read clock (RCLK) to read data from memory. WCLK and RCLK are independent of one another and can operate asynchronously or be tied together for single-clock operation. The empty-flag (EF) output is synchronized to RCLK and the full-flag (FF) output is synchronized to WCLK to indicate absolute boundary conditions. Write operations are prohibited when FF is low, and read operations are prohibited when EF is low. Two programmable flags, programmable almost empty (PAE) and programmable almost full (PAF), can both be programmed to indicate any measure of memory fill. After reset, PAE defaults to empty+7 and PAF defaults to full−7. Flag-offset programming control is similar to a memory write with the use of the load (WEN2/LD) signal. These devices are suited for providing a data channel between two buses operating at asynchronous or synchronous rates. Applications include use as rate buffers for graphics systems and high-speed queues for communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus a parity bit or packet-framing information. The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241L are characterized for operation from 0°C to 70°C. Copyright  1993, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 3213 2 3 1 RS WEN1 WCLK WEN2/LD VCC PAF PAE GND REN1 RCLK REN2 OE 43 0 15 16 17 18 19EF FF RJ PACKAGE (TOP VIEW) 20Q4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

/C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0049/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0050/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0051/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0052/C0049/C0076 /C0053/C0049/C0050 × /C0057/C0044 /C0049/C0048/C0050/C0052 × /C0057/C0044 /C0050/C0048/C0052/C0056 × /C0057/C0044 /C0065/C0078/C0068 /C0052/C0048/C0057/C0054 × /C0057 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0070/C0073/C0082/C0083/C0084/C0262/C0073/C0078/C0044 /C0070/C0073/C0082/C0083/C0084/C0262/C0079/C0085/C0084 /C0077/C0069/C0077/C0079/C0082/C0073/C0069/C0083 SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional block diagram Input Register Dual-Port SRAM 512 × 9 or 1024 × 9 or 2048 × 9 or 4096 × 9 OE D0−D8 WEN2 RS LD Synchronous Read Control Synchronous Write Control Reset Logic Status- Flag Logic Read Pointer Write Pointer Output Register Offset Registers WCLK REN2 REN1 RCLK Q0−Q8 EF PAE PAF FF WEN1 † † 512 × 9 for the SN74ACT72211L; 1024× 9 for the SN74ACT72221L; 2048× 9 for the SN74ACT72231L; 4096× 9 for the SN74ACT72241L

/C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0049/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0050/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0051/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0052/C0049/C0076 /C0053/C0049/C0050 × /C0057/C0044 /C0049/C0048/C0050/C0052 × /C0057/C0044 /C0050/C0048/C0052/C0056 × /C0057/C0044 /C0065/C0078/C0068 /C0052/C0048/C0057/C0054 × /C0057 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0070/C0073/C0082/C0083/C0084/C0262/C0073/C0078/C0044 /C0070/C0073/C0082/C0083/C0084/C0262/C0079/C0085/C0084 /C0077/C0069/C0077/C0079/C0082/C0073/C0069/C0083 SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION D0−D8 6−1, 32−30 I Data inputs EF 14 O Empty-flag. When memory is empty, EF is low and further data reads are ignored by the device. When EF is high, the memory is not empty and data reads are allowed. EF is synchronized to RCLK by one flip-flop. FF 15 O Full-flag. When memory is full, FF is low and data writes are inhibited. FF is synchronized to WCLK by one flip-flop. GND 9 Ground OE 13 I Output-enable. Q0−Q8 are in the high-impedance state when OE is high. Q0−Q8 are active when OE is low. PAE 8 O Programmable almost-empty-flag. PAE is low when the FIFO is almost empty based on the value in its offset register. The default value for the register is empty+7. PAE is synchronized to RCLK by one flip-flop. PAF 7 O Programmable almost-full-flag. PAF is low when the FIFO is almost full based on the value in its offset register. The default value for the register is full −7. PAF is synchronized to WCLK by one flip-flop. Q0−Q8 16−24 O Data outputs RCLK 11 I Read-clock. A data read is performed by the low-to-high transition of RCLK when REN1 and REN2 are asserted and EF is high. REN1 , REN2 10, 11 I Read-enable. Data is read from the FIFO on a low-to-high transition of RCLK when REN1 and REN2 are low and EF is high. RS 29 I Reset. When RS is set low, the read and write pointers are initialized to the first RAM location and the FIFO is empty. FF and PAF are set high, and EF and PAE are set low. Each bit in the data output register is set low by a device reset. The FIFO must be reset after power up before data is written. VCC Supply voltage WCLK 27 I Write-clock. Data is written by the low-to-high transition of WCLK when WEN1 and WEN2/LD are asserted and FF is high. WEN1 28 I Write-enable 1. WEN1 is the only write enable terminal if the device is configured to have programmable flags. Data is written on a low-to-high transition of WCLK when WEN1 is low and FF is high. If the FIFO is not configured for programmable flags, data is written on a low-to-high transition of WCLK when WEN1 and WEN2 are asserted and FF is high. WEN2/LD 26 I Write-enable 2/load. This is a dual-purpose input. The FIFO can have either two write enables or programmable flags. To use WEN2/LD as a WEN2, WEN2/LD must be held high at reset. When WEN2 and WEN1 are asserted and FF is high, a low-to-high transition of WCLK writes data. To use WEN2/LD as the LD terminal, it must be held low at reset. In this case, LD is asserted low to write or read the programmable offset registers.

/C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0049/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0050/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0051/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0052/C0049/C0076 /C0053/C0049/C0050 × /C0057/C0044 /C0049/C0048/C0050/C0052 × /C0057/C0044 /C0050/C0048/C0052/C0056 × /C0057/C0044 /C0065/C0078/C0068 /C0052/C0048/C0057/C0054 × /C0057 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0070/C0073/C0082/C0083/C0084/C0262/C0073/C0078/C0044 /C0070/C0073/C0082/C0083/C0084/C0262/C0079/C0085/C0084 /C0077/C0069/C0077/C0079/C0082/C0073/C0069/C0083 SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 detailed description device reset A reset is performed by taking the reset (RS) input low. This initializes both the write and read pointers to the first memory location. After a reset, the full flag (FF) and programmable almost-full flag (PAF) are high and the empty flag (EF) and programmable almost-empty flag (PAE) are low. Each bit in the data output register (Q0−Q8) is set low, and the flag offset registers are loaded with the default offset values. A FIFO must be reset after power up before a write cycle is allowed. The logic level on the dual-purpose input write enable 2/load (WEN2/LD) during reset determines its function. If WEN2/LD is high when RS returns high at the end of the reset cycle, the input is a second write enable (see FIFO writes and reads) and the programmable flags (PAF, PAE) can only use the default values. If WEN2/LD is low when RS returns high at the end of the reset cycle, the input is the load (LD) enable for writing and reading flag offset registers (see flag programming). FIFO writes and reads Data is written to memory by a low-to-high transition of write clock (WCLK) when write enable 1 (WEN1) is low, WEN2/LD is high, and FF is high. This stores D0−D8 data in the dual-port SRAM and increments the write pointer. If no reads are performed after reset (RS = VIL), FF is set low upon the completion of 512 writes to the SN74ACT72211, 1024 writes to the SN74ACT72221, 2048 writes to the SN74ACT72231, and 4096 writes to the SN74ACT72241. Attempted write cycles are ignored when FF is low. FF is set high by the first low-to-high transition of WCLK after data is read from a full FIFO. FF and PAF are each synchronized to the low-to-high transition of WCLK by one flip-flop. If a device is configured to have two write enables (see device reset), data is read by the low-to-high transition of read clock (RCLK) when both read enables (REN1, REN2) are low and EF is high. WEN2/LD must also be high if the device is configured to have programmable flags. A read from the FIFO puts RAM data on Q0−Q8 and increments the read pointer in the same sequence as the write pointer. New data is not shifted to the output register while either one or both of the read enables are high. EF and PAE are each synchronized to the low-to-high transition of RCLK by one flip-flop. When the device is empty, the write and read pointers are equal and EF is set low. Attempted read cycles are ignored while EF is set low. EF is set high by the first low-to-high transition of RCLK after data is written to an empty FIFO. WCLK and RCLK can be asynchronous or coincident to one another. Writing data to FIFO memory is independent of reading data from FIFO memory and vice versa. flag programming When WEN2/LD is held low during a device reset (RS = VIL), the input is the load (LD) enable for flag offset programming. In this configuration, WEN2/LD can be used to access the four 8-bit offset registers contained in the SN74ACT72211L/-72221L/-72231L/-72241L for writing or reading data. When the device is configured for programmable flags and both WEN2/LD and WEN1 are low, the first low-to-high transition of WCLK writes data from the data inputs to the empty offset least significant bit (LSB) register. The second, third, and fourth low-to-high transitions of WCLK store data in the empty offset most significant bit (MSB) register, full offset LSB register, and full offset MSB register, respectively, when WEN2/LD and WEN1 are low. The fifth low-to-high transition of WCLK while WEN2/LD and WEN1 are low writes data to the empty LSB register again. Figure 1 shows the register sizes and default values for the various device types. It is not necessary to write to all the offset registers at one time. A subset of the offset registers can be written; then, by bringing the WEN2/LD input high, the FIFO is returned to normal read and write operation. The next time WEN2/LD is brought low, a write operation stores data in the next offset register in sequence.

should not be performed simultaneously on the offset registers (see Figure 1 and Table 1). Figure 1. Offset Register Location and Default Values

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 1. Writing the Offset Registers is performed on the low-to-high transition of RCLK. corresponding offset registers and the difference between the read and write pointers. low-to-high transition of RCLK when the FIFO contains (n + 1) or greater unread words. of available memory locations is greater than m (see Table 2). Table 2. Status Flags

load enable for the programmable flag offset registers. B. After reset, the outputs are low if OE is low and at the high-impedance level if OE is high. C. The clocks (RCLK, WCLK) can be free running during reset. Figure 2. Reset Timing

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

not change its logic level until the next WCLK rising edge. Figure 3. Write-Cycle Timing

not change its logic level until the next RCLK rising edge. Figure 4. Read-Cycle Timing

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 5. First-Data-Word-Latency Timing

not change its logic level until the next WCLK rising edge. Figure 6. Full-Flag Timing

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not change its logic level until the next RCLK rising edge. Figure 7. Empty-Flag Timing

may not change its logic level until the next WCLK rising edge. D. If a write is performed on this rising edge of the write clock, there will be [Full − (m − 1)] words in the FIFO when PAF goes low. Figure 8. Programmable Almost-Full Flag Timing

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

may not change its logic level until the next RCLK rising edge. C. If a write is performed on this rising edge of the write clock, there will be [Empty + (n − 1)] words in the FIFO when PAE goes low. Figure 9. Programmable Almost-Empty Flag Timing

/C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0049/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0050/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0051/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0052/C0049/C0076 /C0053/C0049/C0050 × /C0057/C0044 /C0049/C0048/C0050/C0052 × /C0057/C0044 /C0050/C0048/C0052/C0056 × /C0057/C0044 /C0065/C0078/C0068 /C0052/C0048/C0057/C0054 × /C0057 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0070/C0073/C0082/C0083/C0084/C0262/C0073/C0078/C0044 /C0070/C0073/C0082/C0083/C0084/C0262/C0079/C0085/C0084 /C0077/C0069/C0077/C0079/C0082/C0073/C0069/C0083 SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V IOH High-level output current −2 mA IOL Low-level output current 8 mA TA Operating free-air temperature 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT VOH High-level output voltage VCC = 4.5 V, IOH = − 2 mA 2.4 V VOL Low-level output voltage VCC = 4.5 V, IOL = 8 mA 0.4 V II Input current VCC = 5.5 V, VI = VCC or 0 V ±1 µA IOZ High-impedance output currentVCC = 5.5 V, VO = VCC or 0 V ±10 µA C i‡ Input capacitance VI = 0, f = 1 MHz 10 pF C o‡ Output capacitance VO = 0, f = 1 MHz, OE ≥ VIH 10 pF SN74ACT72211L 140§ ICC ¶ Active supply current fclock = 20 MHz SN74ACT72221L, SN74ACT72231L, SN74ACT72241L 160# mA ‡ Specified by design but not tested § ICC measurements are made with outputs open (only capacitive loading). Typical ICC = 65 + (fclock × 1.1/MHz) + (fclock × CL × 0.03/MHz-pF) mA (CL = external capacitive load). ¶ The ICC limits are valid for tc = 15, 20, 25, and 50 ns. # ICC measurements are made with outputs open (only capacitive loading). Typical ICC = 80 + (fclock × 2.1/MHz) + (fclock × CL × 0.03/MHz-pF) mA (CL = external capacitive load).

/C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0049/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0050/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0051/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0052/C0049/C0076 /C0053/C0049/C0050 × /C0057/C0044 /C0049/C0048/C0050/C0052 × /C0057/C0044 /C0050/C0048/C0052/C0056 × /C0057/C0044 /C0065/C0078/C0068 /C0052/C0048/C0057/C0054 × /C0057 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0070/C0073/C0082/C0083/C0084/C0262/C0073/C0078/C0044 /C0070/C0073/C0082/C0083/C0084/C0262/C0079/C0085/C0084 /C0077/C0069/C0077/C0079/C0082/C0073/C0069/C0083 SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figures 2 through 13) ′ACT72211L-15 ′ACT72221L-15 ′ACT72231L-15 ′ACT72241L-15 ′ACT72211L-20 ′ACT72221L-20 ′ACT72231L-20 ′ACT72241L-20 ′ACT72211L-25 ′ACT72221L-25 ′ACT72231L-25 ′ACT72241L-25 ′ACT72211L-50 ′ACT72221L-50 ′ACT72231L-50 ′ACT72241L-50 UNIT MIN MAX MIN MAX MIN MAX MIN MAX fclock Clock frequency, RCLK or WCLK 66.7 50 40 20 MHz tc Clock cycle time, RCLK or WCLK 15† 20 25 50 ns tw(CLKH) Pulse duration, RCLK or WCLK high 6 8 10 20 ns tw(CLKL) Pulse duration, RCLK or WCLK low 6 8 10 20 ns tw(RS) Pulse duration, RS low 15 20 25 50 ns tsu(D) Setup time, D0−D8 before RCLK↑ 4 5 6 10 ns tsu(EN) Setup time, WEN1, WEN2‡, and LD § before WCLK↑; REN1, REN2, and LD§ before RCLK↑ 4 5 6 10 ns tsu(RS) Setup time, REN1, REN2, WEN1, and WEN2/LD before RS high 15 20 25 50 ns th(D) Hold time, D0−D8 after RCLK↑ 1 1 1 2 ns th(EN) Hold time, WEN1, WEN2‡, and LD § after WCLK↑; REN1, REN2, and LD§ after RCLK↑ 1 1 1 2 ns th(RS) Hold time, REN1, REN2, WEN1, and WEN2/LD after RS high 15 20 25 50 tsk1 Skew time between RCLK↑ and WCLK ↑ to allow EF or FF to change logic levels during the current clock cycle 6 8 10 15 ns tsk2 Skew time between RCLK↑ and WCLK ↑ to allow PAF or PAE to change logic levels during the current clock cycle 28 35 40 45 ns † Valid for PAE or PAF program values as follows: ≤ 63 bytes from the respective boundary for the SN74ACT72211L; ≤ 511 bytes from the respective boundary for the SN74ACT72221L/-72231L/-72241L; minimum tc is 20 ns for program values greater than those indicated above. ‡ Applicable when the device is configured with two write-enable inputs (WEN2/LD = WEN2). § Applicable when the device is configured to have programmable flags (WEN2/LD = LD).

/C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0049/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0050/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0051/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0052/C0049/C0076 /C0053/C0049/C0050 × /C0057/C0044 /C0049/C0048/C0050/C0052 × /C0057/C0044 /C0050/C0048/C0052/C0056 × /C0057/C0044 /C0065/C0078/C0068 /C0052/C0048/C0057/C0054 × /C0057 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0070/C0073/C0082/C0083/C0084/C0262/C0073/C0078/C0044 /C0070/C0073/C0082/C0083/C0084/C0262/C0079/C0085/C0084 /C0077/C0069/C0077/C0079/C0082/C0073/C0069/C0083 SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figures 2 through 13) PARAMETER ′ACT72211L-15 ′ACT72221L-15 ′ACT72231L-15 ′ACT72241L-15 ′ACT72211L-20 ′ACT72221L-20 ′ACT72231L-20 ′ACT72241L-20 ′ACT72211L-25 ′ACT72221L-25 ′ACT72231L-25 ′ACT72241L-25 ′ACT72211L-50 ′ACT72221L-50 ′ACT72231L-50 ′ACT72241L-50 UNIT MIN MAX MIN MAX MIN MAX MIN MAX ta Access time, RCLK↑ to Q0−Q8 valid 2 10 2 12 3 15 3 25 ns tpd(OE-Q) Propagation delay time, OE low to Q0−Q8 valid 3 8 3 10 3 13 3 28 ns tpd(R-EF) Propagation delay time, RCLK↑ to EF low or high 10 12 15 30 ns tpd(W-FF) Propagation delay time, WCLK↑ to FF low or high 10 12 15 30 ns tpd(R-AE) Propagation delay time, RCLK↑ to PAE low or high 10 12 15 30 ns tpd(W-AF) Propagation delay time, WCLK↑ to PAF low or high 10 12 15 30 ns tpd(RS-O) Propagation delay time, RS low to FF and PAF high and EF, PAE, and Q0−Q8 low 15 20 25 50 ns ten Enable time, OE low to Q0−Q8 at the low-impedance level† 0 0 0 0 ns tdis Disable time, OE high to Q0−Q8 at the high-impedance level† 3 8 3 10 3 13 3 28 ns † These values are characterized but not tested.

/C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0049/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0050/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0051/C0049/C0076/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0055/C0050/C0050/C0052/C0049/C0076 /C0053/C0049/C0050 × /C0057/C0044 /C0049/C0048/C0050/C0052 × /C0057/C0044 /C0050/C0048/C0052/C0056 × /C0057/C0044 /C0065/C0078/C0068 /C0052/C0048/C0057/C0054 × /C0057 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0070/C0073/C0082/C0083/C0084/C0262/C0073/C0078/C0044 /C0070/C0073/C0082/C0083/C0084/C0262/C0079/C0085/C0084 /C0077/C0069/C0077/C0079/C0082/C0073/C0069/C0083 SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

APPLICATION INFORMATION

width-expansion configuration Word width is increased by connecting the corresponding input control signals of multiple devices. Composite empty and full flags should be created by monitoring all devices in width expansion. Almost-full and almost-empty status can be obtained from any one device. Figure 12 shows an 18-bit-wide data path formed by using two SN74ACT72211L/72221L/72231L/72241L devices. In Figure 12, read enable 2 (REN2 ) is grounded and read enable 1 (REN1) acts as the only read control. The write enable 2/load (WEN2/LD) input of only one device is set low at reset to configure the device for programmable flags and to have it act as a load control for reading and writing the programmable flag offset registers. RS WCLK WEN1 WEN2/LD PAF FF D0−D17 RS RCLK REN2 PAE EF Q0−Q 17 RCLK D0−D8 REN1 Q0−Q8 RS WCLK WEN1 WEN2/LD FF D0−D8 RCLK REN2 EF REN1 Q0−Q8 5 V 9 9 D0−D8 Q0−Q8 D9−D17 Q9−Q17 WCLK WEN1 LD PAF FF REN1 PAE EF SN74ACT72211L/72221L/72231L/72241L SN74ACT72211L/72221L/72231L/72241L Figure 12. Word-Width Expansion for 512/1024/2048/4096 × 18 FIFO

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 13. Load Circuit and Voltage Waveforms

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applications

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