CD54ACT174 TI | Alldatasheet
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CD54ACT174, CD74ACT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCHS344 – APRIL 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Inputs Are TTL-Voltage Compatible /C0068 Contain Six Flip-Flops With Single-Rail Outputs /C0068 Buffered Inputs /C0068 Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption /C0068 Balanced Propagation Delays /C0068 ±24-mA Output Drive Current – Fanout to 15 F Devices /C0068 SCR-Latchup-Resistant CMOS Process and Circuit Design /C0068 Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 /C0068 Applications Include: – Buffer/Storage Registers – Shift Registers description/ordering information The ’ACT174 devices are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input and are designed for 4.5-V to 5.5-V VCC operation. Information at the data (D) inputs that meets the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.
ORDERING INFORMATION
TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – E Tube CD74ACT174E CD74ACT174E 55°Ct o1 2 5°C SOIC M Tube CD74ACT174M ACT174M–55°C to 125°C SOIC – M Tape and reel CD74ACT174M96 ACT174M CDIP – F Tube CD54ACT174F3A CD54ACT174F3A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each flip-flop) INPUTS OUTPUT CLR CLK D Q L X X L H ↑ HH H ↑ LL H L X Q 0 CD54ACT174 ...F PACKAGE CD74ACT174 ...E O R M PACKAGE (TOP VIEW) CLR GND V CC CLK PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2003, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
CD54ACT174, CD74ACT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCHS344 – APRIL 2003
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logic diagram (positive logic) R To Five Other Channels CLR CLK absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) TA = 25°C –55°C to 125°C –40°C to 85°C UNIT MIN MAX MIN MAX MIN MAX VIH High-level input voltage 2 2 2 V VIL Low-level input voltage 0.8 0.8 0.8 V VI Input voltage 0 VCC 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC 0 VCC V IOH High-level output current –24 –24 –24 mA IOL Low-level output current 24 24 24 mA ∆t/∆v Input transition rise or fall rate 10 10 10 ns/V NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CD54ACT174, CD74ACT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCHS344 – APRIL 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C –55°C to 125°C –40°C to 85°C UNITCC MIN MAX MIN MAX MIN MAX IOH = –50 µA 4.5 V 4.4 4.4 4.4 VOH VI=V IH or VIL IOH = –24 mA 4.5 V 3.94 3.7 3.8 VVOH VI = VIH or VIL IOH = –50 mA† 5.5 V 3.85 V IOH = –75 mA† 5.5 V 3.85 IOL = 50 µA 4.5 V 0.1 0.1 0.1 VOL VI=V IH or VIL IOL = 24 mA 4.5 V 0.36 0.5 0.44 VVOL VI = VIH or VIL IOL = 50 mA† 5.5 V 1.65 V IOL = 75 mA† 5.5 V 1.65 II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA ICC VI = VCC or GND, IO = 0 5.5 V 8 160 80 µA C i 10 10 10 pF † Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C. ‡ Additional quiescent supply current per input pin, TTL inputs high, 1 unit load ACT INPUT LOAD TABLE INPUT UNIT LOAD Data 0.5 CLR 0.5 CLK 0.83 Unit Load is ∆ICC limit specified in electrical characteristics table (e.g., 2.4 mA at 25°C). timing requirements over recommended operating free-air temperature range, VCC = 5 V± 0.5 V (unless otherwise noted) –55°C to 125°C –40°C to 85°C UNIT MIN MAX MIN MAX fclock Clock frequency 80 91 MHz t Pulse duration CLR low 4 3.5 nstw Pulse duration CLK high or low 6.2 5.4 ns tsu Setup time before CLK↑ Data 2 2 ns th Hold time, data after CLK↑ 2.5 2.2 ns trec Recovery time, before CLK↑ CLR ↑ 1.5 1.5 ns
CD54ACT174, CD74ACT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCHS344 – APRIL 2003
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switching characteristics over recommended operating free-air temperature range, VCC = 5 V± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) –55°C to 125°C –40°C to 85°C UNIT(INPUT) (OUTPUT) MIN MAX MIN MAX fmax 80 91 MHz tPLH CLK Any Q 3.5 14 3.6 12.6 ns tPHL CLK Any Q 3.5 14 3.6 12.6 ns tPLH CLR Any Q 3.9 15.5 4 14.1 ns tPHL CLR Any Q 3.9 15.5 4 14.1 ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TYP UNIT C pd Power dissipation capacitance 37 pF
NOTES: A. C L includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω , tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. I. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CD54ACT174F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD74ACT174E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74ACT174EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74ACT174M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74ACT174M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74ACT174M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74ACT174ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Addendum-Page 1
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