ACT1284

SN54ACT1284 TI | Alldatasheet

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/C0083/C0078/C0053/C0052/C0065/C0067/C0084/C0049/C0050/C0056/C0052/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0049/C0050/C0056/C0052 /C0055/C0262/C0066/C0073/C0084 /C0066/C0085/C0083 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069/C0083 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCAS459D − NOVEMBER 1994 − REVISED OCTOBER 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C00684.5-V to 5.5-V VCC Operation /C0068Inputs Accept Voltages to 5.5 V /C0068Max tpd of 20 ns at 5 V /C00683-State Outputs Directly Drive Bus Lines /C0068Flow-Through Architecture Optimizes PCB Layout /C0068Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise /C0068ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) /C0068Designed for the IEEE 1284-I (Level-1 Type) and IEEE 1284-II (Level-2 Type) Electrical Specifications description/ordering information The ’ACT1284 devices are designed for asynchronous two-way communication between data buses. The control function minimizes external timing requirements. The devices allow data transmission in either the A-to-B or the B-to-A direction for bits 1, 2, 3, and 4, depending on the logic level at the direction-control (DIR) input. Bits 5, 6, and 7, however, always transmit in the A-to-B direction. The output drive for each mode is determined by the high-drive (HD) control pin. When HD is high, the high drive is delivered by the totem-pole configuration, and when HD is low, the outputs are open drain. This meets the drive requirements as specified in the IEEE 1284-I (level-1 type) and the IEEE 1284-II (level-2 type) parallel peripheral-interface specification.

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC − DW Tube SN74ACT1284DW ACT1284SOIC − DW Tape and reel SN74ACT1284DWR ACT1284 0°C to 70°C SOP − NS Tape and reel SN74ACT1284NSR ACT1284 0°C to 70°C SSOP − DB Tape and reel SN74ACT1284DBR AU284 TSSOP − PW Tube SN74ACT1284PW AU284TSSOP − PW Tape and reel SN74ACT1284PWR AU284 CDIP − J Tube SNJ54ACT1284J SNJ54ACT1284J −55°C to 125°C CFP − W Tube SNJ54ACT1284W SNJ54ACT1284W−55 C to 125C LCCC − FK Tube SNJ54ACT1284FK SNJ54ACT1284FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright  2003, Texas Instruments Incorporated/C0085/C0078/C0076/C0069/C0083/C0083 /C0079/C0084/C0072/C0069/C0082/C0087/C0073/C0083/C0069 /C0078/C0079/C0084/C0069/C0068 /C0116/C0104/C0105/C0115 /C0100/C0111/C0099/C0117/C0109/C0101/C0110/C0116 /C0099/C0111/C0110/C0116/C0097/C0105/C0110/C0115 /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. GND GND DIR V CC VCC HD SN54ACT1284 ...J O R W PACKAGE SN74ACT1284 . . . DB, DW, NS, OR PW PACKAGE (TOP VIEW) 321 2 0 1 9 9 10 11 12 13 V CC VCC GND GND SN54ACT1284 . . . FK PACKAGE (TOP VIEW)A3 B6 B2 DIR HD

/C0083/C0078/C0053/C0052/C0065/C0067/C0084/C0049/C0050/C0056/C0052/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0049/C0050/C0056/C0052 /C0055/C0262/C0066/C0073/C0084 /C0066/C0085/C0083 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069/C0083 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCAS459D − NOVEMBER 1994 − REVISED OCTOBER 2003

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OUTPUT MODEDIR HD OUTPUT MODE L L Open drain A to B: Bits 5, 6, 7 L L Totem pole B to A: Bits 1, 2, 3, 4 L H Totem pole B to A: Bits 1, 2, 3, 4 and A to B: Bits 5, 6, 7 H L Open drain A to B: Bits 1, 2, 3, 4, 5, 6, 7 H H Totem pole A to B: Bits 1, 2, 3, 4, 5, 6, 7 logic diagram (positive logic) HD DIR A1, A2, A3, A4 A5, A6, A7 B1, B2, B3, B4 B5, B6, B7

/C0083/C0078/C0053/C0052/C0065/C0067/C0084/C0049/C0050/C0056/C0052/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0049/C0050/C0056/C0052 /C0055/C0262/C0066/C0073/C0084 /C0066/C0085/C0083 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069/C0083 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCAS459D − NOVEMBER 1994 − REVISED OCTOBER 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The ac input voltage pulse duration is limited to 20 ns if the input voltage goes more negative than −0.5 V. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) SN54ACT1284 SN74ACT1284 UNITMIN MAX MIN MAX UNIT VCC Supply voltage 4.7 5.5 4.7 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V VO Open-drain output voltage HD low 0 5.5 0 5.5 V IOH High-level output current B port, HD high −14 −14 mAIOH High-level output current A port −4 −4 mA IOL Low-level output current B port 14 14 mAIOL Low-level output current A port 4 4 mA TA Operating free-air temperature −55 125 0 70 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. /C0080/C0082/C0079/C0068/C0085/C0067/C0084 /C0080/C0082/C0069/C0086/C0073/C0069/C0087 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0099/C0111/C0110/C0099/C0101/C0114/C0110/C0115 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0105/C0110 /C0116/C0104/C0101 /C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0118/C0101 /C0111/C0114 /C0100/C0101/C0115/C0105/C0103/C0110 /C0112/C0104/C0097/C0115/C0101 /C0111/C0102 /C0100/C0101/C0118/C0101/C0108/C0111/C0112/C0109/C0101/C0110/C0116/C0046 /C0067/C0104/C0097/C0114/C0097/C0099/C0116/C0101/C0114/C0105/C0115/C0116/C0105/C0099 /C0100/C0097/C0116/C0097 /C0097/C0110/C0100 /C0111/C0116/C0104/C0101/C0114 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0097/C0114/C0101 /C0100/C0101/C0115/C0105/C0103/C0110 /C0103/C0111/C0097/C0108/C0115/C0046 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0114/C0101/C0115/C0101/C0114/C0118/C0101/C0115 /C0116/C0104/C0101 /C0114/C0105/C0103/C0104/C0116 /C0116/C0111 /C0099/C0104/C0097/C0110/C0103/C0101 /C0111/C0114 /C0100/C0105/C0115/C0099/C0111/C0110/C0116/C0105/C0110/C0117/C0101 /C0116/C0104/C0101/C0115/C0101 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0119/C0105/C0116/C0104/C0111/C0117/C0116 /C0110/C0111/C0116/C0105/C0099/C0101/C0046

/C0083/C0078/C0053/C0052/C0065/C0067/C0084/C0049/C0050/C0056/C0052/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0084/C0049/C0050/C0056/C0052 /C0055/C0262/C0066/C0073/C0084 /C0066/C0085/C0083 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069/C0083 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCAS459D − NOVEMBER 1994 − REVISED OCTOBER 2003

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of operating free-air temperature and supply voltage (unless otherwise noted) PARAMETER TEST CONDITIONS VCC † SN54ACT1284 SN74ACT1284 UNITPARAMETER TEST CONDITIONS VCC † MIN TYP MAX MIN TYP MAX UNIT Vhys Input VIT+ − VIT− for all inputs 5 V 0.4 0.4 VVhys Input hysteresis VIT+ − VIT− for all inputs 4.7 V 0.2 0.2 V B port IOH = −14 mA 4.7 V 2.4 2.4 VOH A port IOH = −50 µA MIN to MAX VCC −0.2 VCC −0.2 V A port IOH = −4 mA 4.7 V 3.7 3.7 B port IOL =14 mA 4.7 V 0.4 0.4 VOL A port IOL = 50 µA 4.7 V V II VI = VCC or GND 5.5 V ±1 ±1 µA IOZ A or B ports‡ VO = VCC or GND 5.5 V ±20 ±20 µA Ioff B port VI or VO ≤ 7 V 0 V ±100 ±100 µA ICC VI = VCC or GND, IO = 0 5.5 V 1.5 1.5 mA C i Control inputsVI = VCC or GND 5 V 4 4 pF C io A or B ports VO = VCC or GND 5 V 12 12 pF ZO B port IOH = −20 mA, IOH = −50 mA 5 V 8 30 8 30 Ω † For I/O ports, the parameter IOZ includes the input leakage current II. ‡ For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER FROM TO SN54ACT1284 SN74ACT1284 UNITPARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX MIN MAX UNIT tPLH Totem pole A or B B or A 1 20 1 20 nstPHL Totem pole A or B B or A 1 20 1 20 ns SR Totem pole B output 0.05 0.4 0.05 0.4 V/ns tpd(EN) Totem pole HD B 1 20 1 20 nstpd(DIS) Totem pole HD B 1 20 1 20 ns tr, tf Open drain A B 120 120 ns /C0080/C0082/C0079/C0068/C0085/C0067/C0084 /C0080/C0082/C0069/C0086/C0073/C0069/C0087 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0099/C0111/C0110/C0099/C0101/C0114/C0110/C0115 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0105/C0110 /C0116/C0104/C0101 /C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0118/C0101 /C0111/C0114 /C0100/C0101/C0115/C0105/C0103/C0110 /C0112/C0104/C0097/C0115/C0101 /C0111/C0102 /C0100/C0101/C0118/C0101/C0108/C0111/C0112/C0109/C0101/C0110/C0116/C0046 /C0067/C0104/C0097/C0114/C0097/C0099/C0116/C0101/C0114/C0105/C0115/C0116/C0105/C0099 /C0100/C0097/C0116/C0097 /C0097/C0110/C0100 /C0111/C0116/C0104/C0101/C0114 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0097/C0114/C0101 /C0100/C0101/C0115/C0105/C0103/C0110 /C0103/C0111/C0097/C0108/C0115/C0046 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0114/C0101/C0115/C0101/C0114/C0118/C0101/C0115 /C0116/C0104/C0101 /C0114/C0105/C0103/C0104/C0116 /C0116/C0111 /C0099/C0104/C0097/C0110/C0103/C0101 /C0111/C0114 /C0100/C0105/C0115/C0099/C0111/C0110/C0116/C0105/C0110/C0117/C0101 /C0116/C0104/C0101/C0115/C0101 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0119/C0105/C0116/C0104/C0111/C0117/C0116 /C0110/C0111/C0116/C0105/C0099/C0101/C0046

2 V2 V

NOTES: A. CL includes probe and jig capacitance. B. The outputs are measured one at a time with one transition per measurement. C. Input rise and fall times are 3 ns, 150 ns < pulse duration <10 µs for both low-to-high and high-to-low transitions. D. Slew rate is defined as 10% and 90% of the transition times. E. Rise and fall times, open drain, are <120 ns. F. Input rise and fall times are 3 ns. Figure 1. Load Circuits and Voltage Waveforms

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SN74ACT1284DBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI SN74ACT1284DBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT1284DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT1284DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT1284DWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT1284DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT1284DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT1284NSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT1284NSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT1284PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT1284PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT1284PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT1284PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Addendum-Page 1

information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Addendum-Page 2

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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