ACT1073

SN74ACT1073 TI | Alldatasheet

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16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems /C0068 4.5-V to 5.5-V VCC Operation /C0068 Inputs Accept Voltages to 5.5 V /C0068 Reduces Undershoot and Overshoot Caused By Line Reflections /C0068 Repetitive Peak Forward Current...I FRM = 100 mA /C0068 Inputs Are TTL-Voltage Compatible /C0068 Low Power Consumption (Like CMOS) /C0068 Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise /C0068 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) description/ordering information This device is designed to terminate bus lines in CMOS systems. The integrated low-impedance diodes clamp the voltage of undershoots and overshoots caused by line reflections and ensure signal integrity. The device also contains a bus-hold function that consists of a CMOS-buffer stage with a high-resistance feedback path between its output and its input. The SN74ACT1073 prevents bus lines from floating without using pullup or pulldown resistors. The high-impedance inputs of these internal buffers are connected to the input terminals of the device. The feedback path on each internal buffer stage keeps a bus line tied to the bus holder at the last valid logic state generated by an active driver before the bus switches to the high-impedance state.

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC DW Tube SN74ACT1073DW ACT1073 –40°C to 85°C SOIC – DW Tape and reel SN74ACT1073DWR ACT1073 SOP – NS Tape and reel SN74ACT1073NSR ACT1073 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright  2002, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. GND GND D16 D15 D14 D13 V CC VCC D12 D11 D10 DW OR NS PACKAGE (TOP VIEW)

16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram, one of sixteen channels (positive logic) TG VCC VCC GND 6 GND 5 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input negative-voltage rating may be exceeded if the input clamp-current rating is observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) MIN MAX UNIT VCC Supply voltage 4.5 5.5 V VIH High-level input voltage 2.5 V VIL Low-level input voltage 0.8 V VI Input voltage 0 VCC V TA Operating free-air temperature –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25°C MIN MAX UNITPARAMETER TEST CONDITIONS MIN TYP † MAX MIN MAX UNIT VIKL IIN = –18 mA –1.5 –1.5 V VIKH IIN = 18 mA VCC +2 VCC +2 V ICC ‡ VCC = 5.5 V, Inputs open 4 40 µA ∆ICC § One input at 3.4 V, Other inputs at VCC or GND 0.9 1 mA C i VI = VCC or GND 3 pF † All typical values are at VCC = 5 V. ‡ Inputs may be set high or low prior to the ICC measurement. § This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC .

16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

–30 –40 –50 –60 –20 –0.5 –0.25 0 0.2 –0.2 –0.6 01 2 3 0.6 456 0123 4 5 5.5 VI – Input Voltage – VV I – Input Voltage – V VI – Input Voltage – VV I – Input Voltage – V I – Input Current – mAI I – Supply Current – mACC –10 –0.8 –0.4 0.4 0.8 –15 –25 –35 –45 –55 4.5 3.5 2.5 1.5 0.5 5.5 6 6.5 7 7.5 8 8.5 9 FORWARD CURRENT vs INPUT VOLTAGE (UPPER CLAMPING DIODE) FORWARD CURRENT vs INPUT VOLTAGE (LOWER CLAMPING DIODE) SUPPLY CURRENT vs INPUT VOLTAGE INPUT CURRENT vs INPUT VOLTAGE I – Forward Current – mAF I – Forward Current – mAF Figure 1 Figure 2 Figure 3 Figure 4

16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

The SN74ACT1073 terminates the output of a driving device and holds the input of the driven device at the logic level of the driver output prior to establishment of the high-impedance state on that output (see Figure 5). Typical Output SN74ACT1073 CMOS Input VCC GND D1 (external connection point) Bus Input Output Figure 5. Bus-Hold Application

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SN74ACT1073DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT1073DWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT1073DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT1073DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT1073NSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ACT1073NSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2005 Addendum-Page 1

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