CD54ACT00 TI | Alldatasheet
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Technical content
CD54ACT00, CD74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS308B – JANUARY 2001 – REVISED JUNE 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Inputs Are TTL-Voltage Compatible /C0068 Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption /C0068 Balanced Propagation Delays /C0068 ±24-mA Output Drive Current – Fanout to 15 F Devices /C0068 SCR-Latchup-Resistant CMOS Process and Circuit Design /C0068 Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015
description
The ‘ACT00 devices contain four independent 2-input NAND gates. Each gate performs the Boolean function of Y = A /C0083 B or Y = A + B in positive logic.
ORDERING INFORMATION
TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – E Tube CD74ACT00E CD74ACT00E 55°Ct o1 2 5°C SOIC M Tube CD74ACT00M ACT00M–55°C to 125°C SOIC – M Tape and reel CD74ACT00M96 ACT00M CDIP – F Tube CD54ACT00F3A CD54ACT00F3A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS OUTPUT A B Y H H L L XH X L H logic diagram, each gate (positive logic) A B Y PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. GND V CC CD54ACT00 ...F PACKAGE CD74ACT00 ...E O R M PACKAGE (TOP VIEW) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
CD54ACT00, CD74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS308B – JANUARY 2001 – REVISED JUNE 2002
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) TA = 25°C –40°C TO 85°C –55°C TO 125°C UNIT MIN MAX MIN MAX MIN MAX VIH High-level input voltage 2 2 2 V VIL Low-level input voltage 0.8 0.8 0.8 V VI Input voltage 0 VCC 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC 0 VCC V IOH High-level output current –24 –24 –24 mA IOL Low-level output current 24 24 24 mA ∆t/∆v Input transition rise or fall rate 10 10 10 ns/V NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C –40°C TO 85°C –55°C TO 125°C UNITCC MIN MAX MIN MAX MIN MAX IOH = –50 µA 4.5 V 4.4 4.4 4.4 VOH VI=V IH or VIL IOH = –24 mA 4.5 V 3.94 3.8 3.7 VVOH VI = VIH or VIL IOH = –50 mA‡ 5.5 V 3.85 V IOH = –75 mA‡ 5.5 V 3.85 IOL = 50 µA 4.5 V 0.1 0.1 0.1 VOL VI=V IH or VIL IOL = 24 mA 4.5 V 0.36 0.44 0.5 VVOL VI = VIH or VIL IOL = 50 mA‡ 5.5 V 1.65 V IOL = 75 mA‡ 5.5 V 1.65 II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA ICC VI = VCC or GND, IO = 0 5.5 V 4 40 80 µA C i 10 10 10 pF ‡ Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
CD54ACT00, CD74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS308B – JANUARY 2001 – REVISED JUNE 2002 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ACT INPUT LOAD TABLE INPUT UNIT LOAD A or B 0.15 Unit load is ∆ICC limit specified in electrical characteristics table (e.g., 2.4 mA at 25°C). switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) –40°C TO 85°C –55°C TO 125°C UNIT(INPUT) (OUTPUT) MIN MAX MIN MAX tPLH Ao rB Y 3.4 9.5 3.2 10.8 ns tPHL A or B Y 2.8 8 2.7 13.2 ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TYP UNIT C pd Power dissipation capacitance 45 pF
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NOTES: A. C L includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω , tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. Figure 1. Load Circuit and Voltage Waveforms
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