ACS8510REV2.1

ACS8510_03 SEMTECH | Alldatasheet

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Technical content

with the required specifications and standards. and a 2 kHz Multi-Frame Synchronization clock. tem protection against a single ACS8510 failure. supports IEEE 1149.1 JTAG boundary scan.

• Suitable for Stratum 3E*, 3, 4E and 4 SONET or SDH Equipment Clock (SEC) applications
• Meets AT&T, ITU-T, ETSI and Telcordia specifications
• Accepts 14 individual input reference clocks
• Generates 11 output clocks
• Supports Free-run, Locked and Holdover modes of operation
• Robust input clock source quality monitoring on all inputs
• Automatic ‘hit-less’ source switchover on loss of input
• Phase build out for output clock phase continuity during input switchover and mode transitions
• Microprocessor interface - Intel, Motorola, Serial, Multiplexed, EPROM
• Programmable wander and jitter tracking attenuation 0.1 Hz to 20 Hz
• Support for Master/Slave device configuration alignment and hot/standby redundancy
• IEEE 1149.1 JTAG Boundary Scan
• Single +3.3 V operation, +5 V I/O compatible
• Operating temperature (ambient) -40°C to +85°C
• Available in 100 pin LQFP package * Meets Holdover requirements, lowest bandwidth 0.1 Hz. DPLL/Freq. Synthesis TOUT0 selector TOUT4 selector Chip Clock Generator Divider PFD DPLL/Freq. Synthesis Divider Monitors Digital Loop Filter APLL Frequency Dividers Microprocessor Port 2 x AMI 10 x TTL 2 x PECL/LVDS Programmable; 64/8kHz 2kHz 4kHz N x 8kHz 1.544/2.048MHz 6.48MHz 19.44MHz 25.92MHz 38.88MHz 51.84MHz 77.76MHz 155.52MHz DTO Digital Loop Filter PFD 1 x AMI 6 x TTL 2 x PECL/LVDS Programmable: 64/8kHz 1.544/2.048MHz 3.088/4.096MHz 6.176/8.182MHz 12.352/16.384MHz 6.48MHz 19.44MHz 25.92MHz 38.88MHz 51.84MHz 77.76MHz 155.52MHz 311.04MHz 2kHz MFrSync 8kHz FrSync Input Ports 14xSEC MFrSync Output Ports TCXO (*OCXO) IEEE 1149.1 JTAG TCK TDI TMS TRST TDO Priority Table Register Set DTO 9xSEC FrSync MFrSync

www.semtech.com2 ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL Revision 2.00/September 2003  Semtech Corp. T T T T T able of Contable of Contable of Contable of Contable of Cont entsentsentsentsents List of SectionsList of SectionsList of SectionsList of SectionsList of Sections

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Revision 2.00/September 2003  Semtech Corp. NC - Not Connected; leave to Float. IC - Internally Connected; leave to Float.

100 SONSDHB

99 MSTSLVB

95 TO9

94 TO5

93 TO4

92 DGND

91 VDD

90 TO3

89 TO2

88 TO1

87 DGND

86 VDD

85 VDD

84 DGND

83 AD0

82 AD1

81 AD2

80 AD3

79 AD4

78 AD5

77 AD6

76 AD7

74 PORB

73 ALE

72 RDB

71 WRB

70 CSB

62 DGND

61 VDD

60 UPSEL0

59 UPSEL1

58 UPSEL2

57 I14

56 I13

55 I12

54 I11

53 I10

1 AGND

2 TRST

5 AGND

6 VA1+

7 TMS

8 INTREQ

9 TCK

11 DGND

12 VD+

13 VD+

14 DGND

15 DGND

16 VD+

18 SRCSW

19 VA2+

20 AGND

21 TDO

23 TDI

26 VAMI+

27 TO8NEG

28 TO8POS

29 GND_AMI

31 MFrSync

34 TO6POS

35 TO6NEG

36 TO7POS

37 TO7NEG

40 I5POS

41 I5NEG

42 I6POS

43 I6NEG

44 VDD5

45 SYNC2K

49 DGND

50 VDD

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445 DDVP -

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Revision 2.00/September 2003  Semtech Corp. noise clock signal from an internal oscillator. frequency of the last selected reference source. 2 kHz Multi-Frame Synchronization clock. protection against a single ACS8510 failure.

881 OTO LTT

982 OTO LTT

093 OTO LTT

394 OTO LTT

495 OTO LTT

599 OTO LTT

www.semtech.com10 ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL Revision 2.00/September 2003  Semtech Corp. reference input and generate the T OUT0 clock, the 8 kHz Frame Synchronization clock and the 2 kHz Multi-Frame Synchronization clock with the same phase. The ACS8510 includes a microprocessor port, providing access to the configuration and status registers for device setup and monitoring. Local Oscillator ClockLocal Oscillator ClockLocal Oscillator ClockLocal Oscillator ClockLocal Oscillator Clock The Master system clock on the ACS8510 should be provided by an external clock oscillator of frequency 12.80 MHz. The clock specification is important for meeting the ITU/ETSI and Telcordia performance requirements for Holdover mode. ITU and ETSI specifications permit a combined drift characteristic, at constant temperature, of all non-temperature- related parameters, of up to 10 ppb per day. The same specifications allow a drift of 1 ppm over a temperature range of 0 to +70 °C. Telcordia specifications are somewhat tighter, requiring a non-temperature-related drift of less than 40 ppb per day and a drift of 280 ppb over the temperature range 0 to +50 °C. ITU and ETSI SpecificationITU and ETSI SpecificationITU and ETSI SpecificationITU and ETSI SpecificationITU and ETSI Specification Tolerance: +/- 4.6 ppm over 20 year life time. Drift*: +/- 0.05 ppm/15 seconds @ constant temp. +/- 0.01 ppm/day @ constant temp. +/- 1 ppm over temp. range 0 to +70 °C *Frequency drift over supply range of +2.7V to +3.3V. Telcordia GR-1244 CORE SpecificationTelcordia GR-1244 CORE SpecificationTelcordia GR-1244 CORE SpecificationTelcordia GR-1244 CORE SpecificationTelcordia GR-1244 CORE Specification Tolerance: +/- 4.6 ppm over 20 year life time. Drift*: +/- 0.05 ppm/15 seconds @ constant temp. +/- 0.04 ppm/day @ constant temp. +/- 0.28 ppm over temp. range 0 to +50 °C *Frequency drift over supply range of +2.7V to +3.3V. Please contact Semtech for information on crystal oscillator suppliers. Crystal Frequency CalibrationCrystal Frequency CalibrationCrystal Frequency CalibrationCrystal Frequency CalibrationCrystal Frequency Calibration The absolute crystal frequency accuracy is less important than the stability since any frequency offset can be compensated by adjustment of register values in the IC. This allows for calibration and compensation of any crystal frequency variation away from its nominal value. +/- 50 ppm adjustment would be sufficient to cope with most crystals, in fact the range is an order of magnitude larger due to the use of two 8 bit register locations. The setting of the conf_nominal_frequency register allows for this adjustment. An increase in the register value increases the output frequencies by 0.02 ppm for each LSB step. The default value (in decimal) is 39321. The minimum being 0 and the maximum 65535, gives a -700 ppm to +500 ppm adjustment range of the output frequencies. For example, if the crystal was oscillating at

12.8 MHz + 5 ppm, then the calibration value

in the register to give a -5 ppm adjustment in output frequencies to compensate for the crystal inaccuracy, would be : 39321 - (5 / 0.02) = 39071 (decimal) Input InterfacesInput InterfacesInput InterfacesInput InterfacesInput Interfaces The ACS8510 supports up to fourteen input reference clock sources from input types T IN1, TIN2 and T IN3 using TTL, CMOS, PECL, LVDS and AMI buffer I/O technologies. These interface technologies support +3.3 V and +5 V operation. Over-Voltage ProtectionOver-Voltage ProtectionOver-Voltage ProtectionOver-Voltage ProtectionOver-Voltage Protection The ACS8510 may require Over-Voltage Protection on input reference clock ports according to ITU Recommendation K.41. Semtech protection devices are recommended for this purpose (see separate Semtech data book).

www.semtech.com11 ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL Revision 2.00/September 2003  Semtech Corp. Input Reference Clock PortsInput Reference Clock PortsInput Reference Clock PortsInput Reference Clock PortsInput Reference Clock Ports Table 4 gives details of the input reference ports, showing the input technologies and the range of frequencies supported on each port; the default spot frequencies and default priorities assigned to each port on power-up or by reset are also shown. Note that SDH and SONET networks use different default frequencies; the network type is pin-selectable (using the SONSDHB pin). Specific frequencies and priorities are set by configuration. Although each input port is shown as belonging to one of the types, T IN1, T IN2 or T IN3, they are fully interchangeable as long as the selected speed is within the maximum operating speed of the input port technology. SDH and SONET networks use different default frequencies; the network type is selectable using the config_mode register 34 Hex, bit 2. For SONET, config_mode register 34 Hex, bit 2 = 1, for SDH config_mode register 34 Hex, bit 2 = 0. On power-up or by reset, the default will be set by the state of the SONSDHB pin (pin 100). Specific frequencies and priorities are set by configuration. TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. The actual spot frequencies supported are:

• 2 kHz
• 4 kHz
• 8 kHz (and N x 8 kHz)
• 1.544 MHz (SONET)/2.048 MHz (SDH)
• 6.48 MHz,
• 19.44 MHz,
• 25.92 MHz,
• 38.88 MHz,
• 51.84 MHz,
• 77.76 MHz. The frequency selection is programmed via the cnfg_ref_source_frequency register. The internal DPLL will normally lock to the selected input at the frequency of the input, eg. 19.44 MHz will lock the DPLL phase comparisons at 19.44 MHz. It is, however, possible to utilise an internal pre-divider to the DPLL to divide the input frequency before it is used for phase comparisons in the DPLL. This pre-divider can be used in one of 2 ways: 1. Any of the supported spot frequencies can be divided to 8 kHz by setting the ‘lock8K’ bit (bit 6) in the appropriate cnfg_ref_source_frequency register location. For good jitter tolerance for all frequencies and for operation at 19.44 MHz and above, use lock8K. It is possible to choose which edge of the 8kHz input to lock to, by setting the appropriate bit of the cnfg_control1 register. 2. Any multiple of 8 kHz between 1544 kHz to 100 MHz can be supported by using the ‘DivN’ feature (bit 7 of the cnfg_ref_source_frequency register). Any reference input can be set to use DivN independently of the frequencies and configurations of the other inputs. Any reference input with the DivN bit set in the cnfg_ref_source_frequency register will employ the internal pre-divider prior to the DPLL locking. The cnfg_freq_divn register contains the divider ratio N where the reference input will get divided by (N+1) where 0<N<2 14-1. The cnfg_ref_source_frequency register must be set to the closest supported spot frequency to the input frequency, but must be lower than the input frequency. When using the DivN feature the post-divider frequency must be 8 kHz, which is indicated by setting the ‘lock8k’ bit high (bit 6 in cnfg_ref_source_frequency register). Any input set to DivN must have the frequency monitors disabled (If the frequency monitors are disabled, they are disabled for all inputs regardless of the input configurations, in this case only activity monitoring will take place). Whilst any number of inputs can be set to use the DivN feature, only one N can be programmed, hence all inputs using the DivN feature must require the same division to get to 8 kHz.

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www.semtech.com13 ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL Revision 2.00/September 2003  Semtech Corp. Note 1: TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz (and N x 8 kHz), 1.544 MHz is selected using the SONSDHB pin. When the SONSDHB pin is High SONET is selected, when the SONSDHB pin is Low SDH is selected. Note 2: PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz and 311.04 MHz. Note 3: Input port <I_11> is set at 12 on the Master SETS IC and 1 on the Slave SETS IC, as default on power up (or PORB). The default setup of Master or Slave <I_11> priority is determined by the MSTSLVB pin. PECL and LVDS ports support the spot clock frequencies listed plus 155.52 MHz and 311.04 MHz. The choice of PECL or LVDS compatibility is programmed via the cnfg_differential_inputs register. Unused PECL/ LVDS differential inputs should be fixed with one input high (VDD) and the other input low (GND), or set in LVDS mode and left floating, in which case one input is internally pulled high and the other low. An AMI port supports a composite clock, consisting of a 64 kHz AMI clock with 8 kHz boundaries marked by deliberate violations of the AMI coding rules, as specified in ITU recommendation G.703. Departures from the nominal pattern are detected within the ACS8510, and may cause reference-switching if too frequent. See section DC Characteristics: AMI Input/Output Port, for more details. If the AMI port is unused, the pins (I1 and I2) should be tied to GND and the VAMI+ supply pin (pin 26) disconnected. Input Wander and Jitter ToleranceInput Wander and Jitter ToleranceInput Wander and Jitter ToleranceInput Wander and Jitter ToleranceInput Wander and Jitter Tolerance The ACS8510 is compliant to the requirements of all relevant standards, principally ITU Recommendation G.825, ANSI DS1.101-1994 and ETS 300 462-5 (1997). All reference clock inputs have a tight frequency tolerance but a generous jitter tolerance. Pull- in, hold-in and pull-out ranges are specified for each input port in Table 5. Minimum jitter DivN examplesDivN examplesDivN examplesDivN examplesDivN examples To lock to 2.000 MHz. (1) The cnfg_ref_source_frequency register is set to 11XX0001 (binary) to set the DivN, lock8k bits, and the frequency to E1/DS1. (XX = ‘leaky bucket’ ID for this input). (2) The cnfg_mode register (34Hex) bit 2 needs to be set to 1 to select SONET frequencies (DS1). (3) The frequency monitors are disabled in cnfg_monitors register (48Hex) by writing 00 to bits 0 and 1. (4) The DivN register is set to F9 Hex (249 decimal). To lock to 10.000 MHz. (1) The cnfg_ref_source_frequency register is set to 11XX0010 (binary) to set the DivN, lock8k bits, and the frequency to 6.48 MHz. (XX = ‘leaky bucket’ ID for this input). (2) The frequency monitors are disabled in cnfg_monitors register (48Hex) by writing 00 to bits 0 and 1. (3) The DivN register is set to 4E1 Hex (1249 decimal).

Revision 2.00/September 2003  Semtech Corp. currently locked source is varying in value e.g. external crystal frequency accuracy is within a tolerance of +/- 4.6 ppm.

Revision 2.00/September 2003  Semtech Corp. are supported, as defined in Table 8. depending on the setting of the SONSDHB pin. 11 different frequencies up to 51.84 MHz. and can support clocks up to 155.52 MHz.

Revision 2.00/September 2003  Semtech Corp. MFrSync clocks have a 50:50 mark space ratio. using the cnfg_T0_output_frequencies register.

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1. The magnitude of wander and jitter on the selected
2. The internal wander and jitter transfer characteristic
3. The jitter on the local oscillator clock
4. The wander on the local oscillator clock (in Holdover

of a low pass filter, with a programmable pole. frequency output. Where the SONSDHB pin is High SONET is default, and when SONSDHB pin is Low SDH is default.

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1. ETSI 300 462-5, Section 9.1, requires that the short-

than 0.05 ppm during a 15 second interval.

1. ETSI 300 462-5, Section 9.2, requires that the long-

c = 120 ns (allowance for entry into Holdover mode).

1. ANSI Tin1.101-1994, Section 8.2.2, requires that the

(of 125 µs each) occur during the first day of Holdover. the normal bounds of 0 to 50 °C.

1. ITU G.822, Section 2.6, requires that the slip rate during

Revision 2.00/September 2003  Semtech Corp. is dependent on the frequency being locked to. performance should be better than 0.05 ppm. control pins UPSEL(2:0) as defined in Table 10. for use with Motorola's 68x0 type bus. for use with Intel's 80x86 type bus. processor which use a serial interface.

www.semtech.com22 ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL Revision 2.00/September 2003  Semtech Corp. Interrupt Enable and ClearInterrupt Enable and ClearInterrupt Enable and ClearInterrupt Enable and ClearInterrupt Enable and Clear Interrupt requests are flagged on pin INTREQ (active High). Bits in the interrupt status register are set (high) by the following conditions: 1. Any reference source becoming valid or going invalid 2. A change in the operating state (eg. Locked, Holdover etc.) 3. A brief loss of the currently selected reference source 4. An AMI input error All interrupt sources are maskable via the mask register, each one being enabled by writing a '1' to the appropriate bit. Any unmasked bit set in the interrupt status register will cause the interrupt request pin to be asserted (high). All interrupts are cleared by writing a '1' to the bit(s) to be cleared in the status register. When all pending unmasked interrupts are cleared the interrupt pin will go inactive (low). The loss of the currently selected reference source will eventually cause the input to be considered invalid, triggering an interrupt. The time taken to raise this interrupt is dependant on the leaky bucket configuration of the activity monitors. The fastest leaky bucket setting will still take up to 128 ms to trigger the interrupt. The interrupt caused by the brief loss of the currently selected reference source is provided to facilitate very fast source failure detection if desired. It is triggered after missing just a couple of cycles of the reference source. Some applications require the facility to switch downstream devices based on the status of the reference sources. In order to provide extra flexibility, it is possible to flag the ‘main reference failed’ interrupt (addr 06, bit 6) on the pin TDO. This is simply a copy of the status bit in the interrupt register and is independent of the mask register settings. The bit is reset by writing to the interrupt status register in the normal way. This feature can be enabled and disabled by writing to bit 6 of register 48Hex. from the ROM is used to set the internal register values. Only 64 locations in the ROM are required. Register SetRegister SetRegister SetRegister SetRegister Set All registers are 8-bits wide, organised with the most-significant bit positioned in the left-most bit, with bit significance decreasing towards the right most bit. Some registers carry several individual data fields of various sizes, from single-bit values (e.g. flags) upwards. Several data fields are spread across multiple registers; their organisation is shown in the register map, Table 11. Configuration RegistersConfiguration RegistersConfiguration RegistersConfiguration RegistersConfiguration Registers Each configuration register reverts to a default value on power-up or following a reset. Most default values are fixed, but some will be pin- settable. All configuration registers can be read out over the microprocessor port. Status RegistersStatus RegistersStatus RegistersStatus RegistersStatus Registers The Status Registers contain readable registers. They may all be read from outside the chip but are not writeable from outside the chip (except for a clearing operation). All status registers are read via shadow registers to avoid data hits due to dynamic operation. Each individual status register has a unique location. Register AccessRegister AccessRegister AccessRegister AccessRegister Access Most registers are of one of two types, configuration registers or status registers, the exceptions being the chip_ID and chip_revision registers. Configuration registers may be written to or read from at any time (the complete 8-bit register must be written, even if only one bit is being modified). All status registers may be read at any time and, in some status registers (such as the sts_interrupts register), any individual data field may be cleared by writing a ‘1’ into each bit of the field (writing a ‘0’ value into a bit will not affect the value of the bit). A description of each register is given in the Register Map, and Register Map Description.

Revision 2.00/September 2003  Semtech Corp. result in the device operating in an unexpected way. undefined registers are at default values.

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534 T_gfnc

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www.semtech.com37 ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL Revision 2.00/September 2003  Semtech Corp. a locked state on the failed reference. This is the case even if there are lower priority references available or the currently selected reference fails. When the ONLY valid reference sources that are available have a lower priority than the selected reference, a failure of the selected reference will always trigger a switch- over, regardless of whether Revertive or Non- Revertive mode has been chosen. Also, in a Master/Slave redundancy-protection scheme, the Slave device(s) must follow the Master device. The alignment of the Master and Slave devices is part of the protection mechanism. The availability of each source is determined by a combination of local and remote monitoring of each source. Each input reference source supplied to each ACS8510 device is monitored locally and the results are made available to other devices. Forced Control SelectionForced Control SelectionForced Control SelectionForced Control SelectionForced Control Selection A configuration register, cnfg_ref_selection , controls both the choice of automatic or forced selection and the selection itself (when forced selection is required). The forced selection of an input reference source occurs when the cnfg_ref_selection variable contains a non-zero value, the value then representing the input port required to be selected. This is not the normal mode of operation, and the cnfg_ref_selection variable is defaulted to the all-one value on reset, thereby adopting the automatic selection of the reference source. Automatic Control SelectionAutomatic Control SelectionAutomatic Control SelectionAutomatic Control SelectionAutomatic Control Selection When an automatic selection is required, the cnfg_ref_selection register must be set to all zero or all one. The configuration registers, cnfg_ref_selection_priority, held in the µP port block, consists of seven, 8 bit registers organised as one 4 bit register per input reference port. Each register holds a 4-bit value which represents the desired priority of that particular port. Unused ports should be given the value, '0000' or '1111', in the relevant register to indicate they are not to be included in the priority table. On power-up, or following a reset, the whole of the configuration file will be defaulted to the values defined by Table 4. The selection priority values are all relative to each other, with lower-valued numbers taking higher priorities. Each reference source should be given a unique number, the valid values are 1 to 15 (dec). A value of 0 disables the reference source. However if two or more inputs are given the same priority number those inputs will be selected on a first in, first out basis. If the first of two same priority number sources goes invalid the second will be switched in. If the first then becomes valid again, it becomes the second source on the first in, first out basis, and there will not be a switch. If a third source with the same priority number as the other two becomes valid, it joins the priority list on the same first in, first out basis. There is no implied priority based on the channel numbers. The input port <I_11> is for the connection of the synchronous clock of the T OUT0 output of the Master device (or the active-Slave device), to be used to align the T OUT0 output with the Master (or active-Slave) device if this device is acting in a subordinate-Slave or subordinate- Master role. Ultra Fast SwitchingUltra Fast SwitchingUltra Fast SwitchingUltra Fast SwitchingUltra Fast Switching A reference source is normally disqualified after the leaky bucket monitor thresholds have been crossed. An option for a faster disqualification has been implemented, whereby if register 48H, bit 5 (Ultra Fast Switching), is set then a loss of activity of just a few reference clock cycles will set the ‘no activity alarm’ and cause a reference switch. This can be chosen to cause an interrupt to occur instead of or as well as causing the reference switch. The sts_interrupts register 05 Hex Bit 14 (main_ref_failed) of the interrupt status register is used to flag inactivity on the reference that the device is locked to much faster than the activity monitors can support. If bit 6 of the cnfg_monitors register (flag ref loss on TDO) is set, then the state of this bit is driven onto the TDO pin of the device.

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1. Frequency (This monitoring is only performed when

www.semtech.com39 ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL Revision 2.00/September 2003  Semtech Corp. monitored by the AMI-decoder blocks. Loss of signal is declared by the decoders when either the signal amplitude falls below +0.3 V or there is no activity for 1 ms. Any reference source which suffers a loss-of- signal, loss-of-activity, loss-of-regularity or clock- out-of-band condition will be declared as unavailable. Clock quality monitoring is a continuous process which is used to identify clock problems. There is a difference in dynamics between the selected clock and the other reference clocks. Anomalies occurring on non-selected reference sources affect only that source's suitability for selection, whereas anomalies occurring on the selected clock could have a detrimental impact on the accuracy of the output clock. Anomalies, whether affecting signal purity or signal frequency, could induce jitter or frequency offsets in the output clock, leading to anomalous behaviour. Anomalies on the selected clock, therefore, have to be detected as they occur and the phase locked loop must be temporarily isolated until the clock is once again pure. The clock monitoring process cannot be used for this because the high degree of accuracy required dictates that the process be slow. To achieve the immediacy required by the phase locked loop requires an alternative mechanism. The phase locked loop itself contains appropriate circuitry, based around the phase detector, and isolates itself from the selected reference source as soon as a signal impurity is detected. It can likewise respond to frequency offsets outside the permitted range since these result in saturation of the phase detector. When the phase locked loop is isolated from the reference source, it is essentially operating in a Holdover state; this is preferable to feeding the loop with a standby source, either temporarily or permanently, since excessive phase excursions on the output clock are avoided. Anomalies detected by the phase detector are integrated in a leaky bucket accumulator. The time taken to raise an inactivity alarm on a reference source that has previously been fully active (leaky bucket empty) will be: ( cnfg_activ_upper_threshold N) where N is the number of the relevent leaky bucket configuration. If an input is intermittently inactive then this time can be longer. The default setting of cnfg_activ_upper_threshold is 6, therefore the default time is 0.75 s. The time taken to cancel the activity alarm on a previously completely inactive reference source is calculated as: 2 x (( cnfg_bucket_size N) - ( cnfg_activ_lower_thrshold N)) where N is the number of the relevent leaky bucket configuration in each case. The default setting are shown in the following: 2 x (8-4) = 1.0 s secs secs (cnfg_decay_rate N) Leaky bucket timing Leaky bucket timing Leaky bucket timing Leaky bucket timing Leaky bucket timing

www.semtech.com40 ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL Revision 2.00/September 2003  Semtech Corp. Occasional anomalies do not cause the accumulator to cross the alarm setting threshold, so the selected reference source is retained. Persistent anomalies cause the alarm setting threshold to be crossed and result in the selected reference source being rejected. Activity MonitoringActivity MonitoringActivity MonitoringActivity MonitoringActivity Monitoring The ACS8510 has a combined inactivity and irregularity monitor. The ACS8510 uses a ‘leaky bucket’ accumulator, which is a digital circuit which mimics the operation of an analog integrator, in which input pulses increase the output amplitude but die away over time. Such integrators are used when alarms have to be triggered either by fairly regular defect events, which occur sufficiently close together, or by defect events which occur in bursts. Events which are sufficiently spread out should not trigger the alarm. By adjusting the alarm setting threshold, the point at which the alarm is triggered can be controlled. The point at which the alarm is cleared depends upon the decay rate and the alarm clearing threshold. On the alarm setting side, if several events occur close together, each event adds to the amplitude and the alarm will be triggered quickly; if events occur a little more spread out, but still sufficiently close together to overcome the decay, the alarm will be triggered eventually. If events occur at a rate which is not sufficient to overcome the decay, the alarm will not be triggered. On the alarm clearing side, if no defect events occur for a sufficient time, the amplitude will decay gradually and the alarm will be cleared when the amplitude falls below the alarm clearing threshold. The ability to decay the amplitude over time allows the importance of defect events to be reduced as time passes by. This means that, in the case of isolated events, the alarm will not be set, whereas, once the alarm becomes set, it will be held on until normal operation has persisted for a suitable time (but if the operation is still erratic, the alarm will remain set). See Figure 9. The ‘leaky bucket’ accumulators are programmable for size, alarm set & reset thresholds and decay rate. Each source is monitored over a 128 ms period. If, within a 128 ms period, an irregularity occurs that is not deemed to be due to allowable jitter/wander, then the accumulator is incremented. The accumulator will continue to increment up to the point that it reaches the programmed bucket size. The ‘fill rate’ of the leaky bucket is, therefore, 8 units/second. The ‘leak rate’ of the leaky bucket is programmable to be in multiples of the fill rate (x1, x0.5, x0.25 and x0.125) to give a programmable leak rate from 8 units/sec down to 1 unit/sec. A conflict between trying to ‘leak’ at the same time as a ‘fill’ is avoided by preventing a ‘leak’ when a ‘fill’ event occurs. Disqualification of a non-selected reference source is based on inactivity, or on an out of band result from the frequency monitors. The currently selected reference source can be disqualified for phase, frequency, inactivity or if the source is outside the DPLL lock range. If the currently selected reference source is disqualified, the next highest priority, active reference source is selected. Frequency MonitoringFrequency MonitoringFrequency MonitoringFrequency MonitoringFrequency Monitoring The ACS8510 performs frequency monitoring to identify reference sources which have drifted outside the acceptable frequency range of +/- 16.6 ppm (measured with respect to the output clock). The sts_reference_sources out- of-band alarm for a particular reference source is raised when the reference source is outside the acceptable frequency range. The ACS8510 DPLL has a programmable frequency limit of +/- 80 ppm. If the range is programmed to be > 16.6 ppm, the frequency monitors should be disabled so the input reference source is not automatically rejected as out of frequency range.

www.semtech.com41 ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL Revision 2.00/September 2003  Semtech Corp. Modes of OperationModes of OperationModes of OperationModes of OperationModes of Operation The ACS8510 has three primary modes of operation (Free-run, Locked and Holdover) supported by three secondary, temporary modes (Pre-Locked, Lost_Phase and Pre- Locked2). These are shown in the State Transition Diagram, Figure 11. The ACS8510 can operate in Forced or Automatic control. On reset, the ACS8510 reverts to Automatic Control, where transitions between states are controlled completely automatically. Forced Control can be invoked by configuration, allowing transitions to be performed under external control. This is not the normal mode of operation, but is provided for special occasions such as testing, or where a high degree of hands-on control is required. Free-run modeFree-run modeFree-run modeFree-run modeFree-run mode The Free-run mode is typically used following a power-on-reset or a device reset before network synchronization has been achieved. In the Free-run mode, the timing and synchronization signals generated from the ACS8510 are based on the Master clock frequency provided from the external oscillator and are not synchronized to an input reference source. The frequency of the output clock is a fixed multiple of the frequency of the external oscillator, and the accuracy of the output clock is equal to the accuracy of the Master clock. The transition from Free-run to Pre-locked occurs when the ACS8510 selects a reference source. Pre-Locked modePre-Locked modePre-Locked modePre-Locked modePre-Locked mode The ACS8510 will enter the Locked state in a maximum of 100 seconds, as defined by GR- 1244-CORE specification, if the selected reference source is of good quality. If the device cannot achieve lock within 100 seconds, it reverts to Free-run mode and another reference source is selected. Locked modeLocked modeLocked modeLocked modeLocked mode The Locked mode is used when an input reference source has been selected and the PLL has had time to lock. When the Locked mode is achieved, the output signal is in phase and locked to the selected input reference source. The selected input reference source is determined by the priority table. When the ACS8510 is in Locked mode, the output frequency and phase follows that of the selected input reference source. Variations of the external crystal frequency have a minimal effect on the output frequency. Only the minimum to maximum frequency range is affected. Note that the term, 'in phase', is not applied in the conventional sense when the ACS8510 is used as a frequency translator (e.g., when the input frequency is 2.048 MHz and the output frequency is 19.44 MHz) as the input and output cycles will be constantly moving past each other; however, this variation will itself be cyclical over time unless the input and output are not locked. Lost_Phase modeLost_Phase modeLost_Phase modeLost_Phase modeLost_Phase mode Lost-phase mode is entered when the current phase error, as measured within the DPLL, is larger than a preset limit (see register 04, bits 5:3), as a result of a frequency or phase transient on the selected reference source. This mode is similar in behavior to the Pre-locked or Pre-locked(2) modes, although in this mode the DPLL is attempting to regain lock to the same reference rather than attempt lock to a new reference. If the DPLL cannot regain lock within 100 s, the source is disqualified, and one of the following transitions takes place: 1. Go to Pre-Locked(2); - If a known-good standby source is available. 2. Go to Holdover; - If no standby sources are available.

www.semtech.com42 ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL Revision 2.00/September 2003  Semtech Corp. Holdover modeHoldover modeHoldover modeHoldover modeHoldover mode The Holdover mode is used when the ACS8510 has been in Locked mode for long enough to acquire stable frequency data, but the final selected reference source has become unavailable and a replacement has not yet been qualified for selection. In Holdover mode, the ACS8510 provides the timing and synchronisation signals to maintain the Network Element (NE), but they are not phase locked to any input reference source. The timing is based on a stored value of the frequency ratio obtained during the last Locked mode period. To allow for further development of the way the internal algorithm operates, and to allow for customised switching behaviour, the switch to and from Holdover state may be controlled by external software. The device must be set in either ‘manual’ mode or ‘automatic’ mode: 1. Register cnfg_mode bit ‘holdover offset en’ set high (manual mode). The Holdover frequency is determined by the value in register cnfg_holdover_offset . This is a 19 bit signed number, with a LSB resolution of 0.0003 ppm, which gives an adjustment range of ± 80 ppm. This value can be derived from a reading of the register sts_curr_inc_offset (addr 0D, 0C and 07) which gives, in the same format, an indication of the current output frequency deviation, which would be read when the device is locked. If required, this value could be read by an external microcontroller and averaged over the time required. The averaged value could then be fed to the cnfg_holdover_offset register ready for setting of the averaged frequency value when the device enters Holdover mode. The sts_curr_inc_offset value is internally derived from the Digital Phase Locked Loop (DPLL) integral path value, which already represents a well averaged measure of the current frequency, depending on the loop bandwidth selected. 2. Register cnfg_mode bit ‘holdover offset en’ set low (automatic mode). In automatic control, the device can be run in one of two ways:

2.1 Register cnfg_holdover_offset register 40 bit 7 ‘auto

holdover averaging’ is set high. The value is averaged internally over 32 samples at 32 seconds apart, giving the average frequency over approximatley the last 20 minutes. The proportional DPLL path is ignored so that recent signal disturbances do not affect the Holdover frequency value. If the device has been previously correctly locked, missing pulses in the input clock stream fed to the SETS IC are ignored, hence also avoiding any frequency disturbances to the output frequency value when an input clock source fails.

2.2 Register cnfg_holdover_offset register 40 bit 7 ‘auto

holdover averaging’ is set low. This simply freezes the DPLL at the current frequency (as reported by the sts_curr_inc_offset register). The proportional DPLL path is ignored so that recent signal disturbances do not affect the Holdover frequency value. Automatic control with internal averaging (option 2.1) is the default condition. If the TCXO frequency is varying due to temperature fluctuations in the room, then the instantaneous value can be different from the average value, and then it may be possible to exceed the 0.05 ppm limit (depending on how extreme the temperature flucuations are). It is advantageous to shield the TCXO to slow down frequency changes due to drift and external temperature fluctuations. The frequency accuracy of Holdover mode has to meet the ITU-T, ETSI and Telcordia performance requirements. The performance of the external oscillator clock is critical in this mode, although only the frequency stability is important - the stability of the output clock in Holdover is directly related to the stability of the external oscillator. Pre-Locked(2) modePre-Locked(2) modePre-Locked(2) modePre-Locked(2) modePre-Locked(2) mode This state is very similar to the Pre-Locked state. It is entered from the Holdover state when a reference source has been selected and applied to the phase locked loop. It is also entered if the device is operating in Revertive mode and a higher-priority reference source is restored. Upon applying a reference source to the phase locked loop, the ACS8510 will enter the Locked state in a maximum of 100 seconds, as defined

www.semtech.com43 ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL Revision 2.00/September 2003  Semtech Corp. by GR-1244-CORE specification, if the selected reference source is of good quality. If the device cannot achieve lock within 100 seconds, it reverts to Holdover mode and another reference source is selected. Protection FacilityProtection FacilityProtection FacilityProtection FacilityProtection Facility The ACS8510 supports redundancy protection. The primary functions of this include: - Alignment of the priority tables of both Master and Slave ACS8510 devices so as to align the selection of reference sources of both Master and Slave ACS8510 devices. - Alignment of the phases of the 8 kHz and 2 kHz clocks in both Master and Slave ACS8510 devices to within one cycle of the 77.76 MHz internal clock. When two ACS8510 devices are to be used in a redundancy-protection scheme within an NE, one will be designated as the Master and the other as the Slave. It is expected that an NE will use the T OUT0 output for its internal operations because the T OUT4 output is intended to feed an SSU/BITS system. An SSU/BITS will not be bothered by phase differences between signals arriving from different sources because it typically incorporates line build-out functions to absorb phase differences on reference inputs. This means that the phasing of the composite clocks between two ACS8510 devices do not have to be mutually-aligned. The same is not true, however, of the T OUT0 output signals (T 01 - T 07, Frame clock and Multi-Frame clock). It is usually important to align the phases of all equivalent T OUT0 signals generated by different sources so that switch-over from one device to another does not affect the internal operations of the NE. Both ACS8510 devices will produce the same signals, which will be routed around the NE to the various consumers (clock sinks). With the possible exception of a through-timing mode, the signals from the Master device will be used by all consumers, unless the Master device fails, when each consumer will switch over to the signals generated by the Slave device. Switchover to a new T OUT0 clock should be as hitless as possible. This requires the signals of both ACS8510 devices to be phase aligned at each consumer. Phase alignment requires frequency alignment. To ensure that both devices can generate output clocks locked to the same source, both devices are supplied with the same reference sources on the same input ports and will have identical priority tables. Failures of selected reference sources will result in both ACS8510 devices making the same updates to their priority tables as availability information will be updated in both devices. Although, in principle, the priority tables will be the same if the same reference sources are used on the same input port on each device, in practice, this is only true if the reference sources actually arrive at each device - failures of a source seen only by one device and not by the other, such as could be caused, for example, by a backplane connector failure, would result in the priority tables becoming misaligned. It is thus necessary to force the priority tables to be aligned under normal operating conditions so that the devices can make the same decisions - this can be achieved by loading the availability seen by one device (via the sts_reference_sources register) into the cnfg_sts_remote_sources_valid register of the other device. Another factor which could affect hit-less switching is the frequency of the local oscillator clock used by each ACS8510 device: these clocks are not mutually aligned and, whilst this has no impact on the frequency of the output clocks during locked mode, it could cause the output frequencies to diverge during Holdover mode if no action were taken to avoid it. In order to maintain alignment of the output frequencies of each ACS8510 device even

www.semtech.com44 ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL Revision 2.00/September 2003  Semtech Corp. during Holdover, the Master device's 6.48 MHz output is fed into the Slave device on its <I_11> pin, whilst the Multi-Frame Sync (2 kHz) output is fed to the Sync2k input of the Slave. In this way, the Slave locks to the master's output and remains locked whilst the Master moves between operating states. Only when the Master fails does the Slave use its own reference inputs - should the Master have been in the Holdover state, the Slave device will see the same lack of reference sources and also enter the Holdover state. This scheme also provides a convenient way to phase-align all TOUT0 output clocks in Master and Slave devices, and also to detect the failure of the Master device. If a Master device fails, the Slave has to take over responsibility for the generation of the output clocks, including the 8 kHz and 2 kHz Frame and Multi-Frame clocks. The Slave device is also given responsibility for building the priority table and performing the reference switching operations. The Slave device, therefore, adopts a more active role when the Master has failed. The cnfg_mode register 34 (Hex) Bit 1 contains the ‘Master/Slave’ control bit to determine the designation of the device. To restore redundancy protection, the Master has to be repaired and replaced. When this occurs, the new Master cannot immediately adopt its normal role because it must not cause phase hits on the output clocks. It has, therefore, to adopt a subordinate role to the active Slave device, at least until such time as it has acquired alignment to the 8 kHz and 2 kHz frame and Multi-Frame clocks and the priority table of the Slave device; then, when a switch-back (restoration) is ordered, the Master can take over responsibility. These activities, in Master or Slave operation, are summarized in Table 12 and described in detail in Application Note AN-SETS-2. Alignment of Priority Tables in Master and SlaveAlignment of Priority Tables in Master and SlaveAlignment of Priority Tables in Master and SlaveAlignment of Priority Tables in Master and SlaveAlignment of Priority Tables in Master and Slave ACS8510ACS8510ACS8510ACS8510ACS8510 Correct protection will only be achieved by connecting individual reference sources to the same input ports on each device and priority tables in each device must be aligned to each other. The Master device must take account of the availability of each reference source seen by another device and a Slave device must adopt the same order of priority as the Master device (except that the Slave's highest-priority input is <I_11>). Both devices monitor the reference sources and decide the availability of each source; if the failure of a reference source is seen by both devices, they will both update their priority tables - however, if the reference source failure is only seen by one device and not by both, the priority tables could get out of step: this could be catastrophic if it resulted in two devices choosing different reference sources since any slight differences in frequency variation over time (e.g. wander) would mis-align the phase of the 8 kHz Frame and 2 kHz Multi- Frame clocks produced by the individual devices, resulting in phase hits on switch-over. It is therefore important that the same priority table be built by each device, using the reference source availability seen by each device. The monitoring of the reference sources performed by a Master ACS8510 results in a list of available sources being placed in a sts_valid_sources register. This information is used within the device as one of the masks used to build the device's priority table. The information is passed to the Slave device and used to configure the cnfg_sts_remote_ sources_valid register so that it can use it as a mask in building its own priority tables. The information is passed between devices using the microprocessor port.

www.semtech.com45 ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL Revision 2.00/September 2003  Semtech Corp. Alignment of the Selection of Reference SourcesAlignment of the Selection of Reference SourcesAlignment of the Selection of Reference SourcesAlignment of the Selection of Reference SourcesAlignment of the Selection of Reference Sources for Tfor Tfor Tfor Tfor T OUT4OUT4OUT4OUT4OUT4 Generation in the Master and Slave Generation in the Master and Slave Generation in the Master and Slave Generation in the Master and Slave Generation in the Master and Slave ACS8510ACS8510ACS8510ACS8510ACS8510 As stated previously, there is no need to align the phases of the T OUT4 outputs in Master and Slave devices. There is a need, however, to ensure that all devices select the same reference source. But, since there is no Holdover mode required for the generation of the T OUT4 clock, and every reference source is continuously monitored within each device, it is permissible to rely on external intelligence to command a switch-over to an alternative source should the selected one fail. The time delay involved in detecting the failure, indicating it to the outside and selecting a new source, will result only in the SSU/BITS entering its Holdover mode for a short time. Alignment of the Phases of the 8kHz and 2kHzAlignment of the Phases of the 8kHz and 2kHzAlignment of the Phases of the 8kHz and 2kHzAlignment of the Phases of the 8kHz and 2kHzAlignment of the Phases of the 8kHz and 2kHz Clocks in both Master and Slave ACS8510Clocks in both Master and Slave ACS8510Clocks in both Master and Slave ACS8510Clocks in both Master and Slave ACS8510Clocks in both Master and Slave ACS8510 In addition to aligning the edges of the T OUT0 outputs of Master and Slave devices, it is necessary to align the edges of the Frame and Multi-Frame clocks. If this is not performed, frame alignment may be lost in distant equipment on switch-over to an alternative device, resulting in anomalous network operation of a very serious nature. In accordance with the alignment mechanism used with the main T OUT0 clock (described in the opening paragraphs of this section), whereby the 6.48 MHz output of the Master device is supplied to the Slave device, the alignment of both the 8 kHz and 2 kHz clocks is accomplished (they are already synchronous to the T OUT0 clocks) by feeding the 2 kHz clock of the Master device into the Slave device. The Multi-Frame Sync clock output of the Slave device is also fed to the Sync2K input of the Master device. Alignment of the Multi-Frame Sync input occurs only when cnfg_mode register, bit 3, address 34Hex External 2 kHz Sync Enable is set to 1. JTAGJTAGJTAGJTAGJTAG The JTAG connections on the ACS8510 allow a full boundary scan to be made. The JTAG implementation is fully compliant to IEEE 1149.1, with the following minor exceptions, and the user should refer to the standard for further information. 1. The output boundary scan cells do not capture data from the core, and so do not support EXTEST. However this does not affect board testing. 2. In common with some other manufacturers, pin TRST is internally pulled low to disable JTAG by default. The standard is to pull high. The polarity of TRST is as the standard: TRST high to enable JTAG boundary scan mode, TRST low for normal operation. 3. The device does not support the optional tri-state capability (HIGHZ). This will be supported on the next revision of the device. The JTAG timing diagram is shown in Figure 17. PORBPORBPORBPORBPORB The Power On Reset (PORB) pin resets the device if forced Low for a power on reset to be initiated. The reset is asynchronous, the minimum Low pulse width is 5 ns. Reset is needed to initialize all of the register values to their defaults. Asserting Reset is required at power on, and may be re-asserted at any time to restore defaults. This is implemented most simplistically by an external capacitor to GND along with the internal pull-up resistor. The ACS8510 is held in a reset state for 250 ms after the PORB pin has been pulled High. In normal operation PORB should be held High.

Revision 2.00/September 2003  Semtech Corp.

6.48 MHz

source as the Master ACS8510 if the Master fails (when the Master is OK, the Slave locks to the Master's output).

Revision 2.00/September 2003  Semtech Corp. active, 'in-band' and have no phase alarm set. Only the main source is checked for phase.

Revision 2.00/September 2003  Semtech Corp. period may reduce the reliability or useful lifetime of the product.

Revision 2.00/September 2003  Semtech Corp.

Revision 2.00/September 2003  Semtech Corp. to VDD and GND respectively. Note 1. Assuming a differential input voltage of at least 100 mV. Note 2. Unused differential input terminated to VDD-1.4 V.

Revision 2.00/September 2003  Semtech Corp.

155.52 MHz

311.04 MHz & DIG1

Revision 2.00/September 2003  Semtech Corp. Note 1. With 100 load between the differential outputs.

Revision 2.00/September 2003  Semtech Corp.

155.52 MHz100R

Revision 2.00/September 2003  Semtech Corp. pulses with a peak to peak voltage of 2.0 +/- 0.2 V. centralized clock interface, from ITU G.703. Nominal bit rate: 64 kbit/s. The tolerance is determined by the network clock stability. use of transformers is recommended. Over-voltage protection requirement; refer to Recommendation K.41. signals and voltage levels are shown in Figures 14 and 15.

Revision 2.00/September 2003  Semtech Corp. The AMI differential output TO8POS/TO8NEG should be coupled to a line transformer with a turns ration of 3:1. load must be used to achieve the required 1 V pp voltage level for the positive and negative pulses.

Revision 2.00/September 2003  Semtech Corp. TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

Revision 2.00/September 2003  Semtech Corp. TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

Revision 2.00/September 2003  Semtech Corp. TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

Revision 2.00/September 2003  Semtech Corp. TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

Revision 2.00/September 2003  Semtech Corp.

Revision 2.00/September 2003  Semtech Corp.

77.76 MHz

51.84 MHz

38.88 MHz

19.44 MHz

25.92 MHz

6.48 MHz input

6.48 MHz output

19.44 MHz input

19.44 MHz output

25.92 MHz input

25.92 MHz output

38.88 MHz input

38.88 MHz output

51.84 MHz input

51.84 MHz output

77.76 MHz input

77.76 MHz output

Revision 2.00/September 2003  Semtech Corp. following figures show the timing diagrams of write and read accesses for this mode. Note 1: Timing with RDY. If RDY not used, t pw1 becomes 178 ns.

Revision 2.00/September 2003  Semtech Corp. Note 1: Timing with RDY. If RDY not used, t pw1 becomes 178 ns.

Revision 2.00/September 2003  Semtech Corp. figures show the timing diagrams of write and read accesses for this mode. Note 1: Timing with RDY. If RDY not used, t pw1 becomes 180 ns.

Revision 2.00/September 2003  Semtech Corp. Note 1: Timing with RDY. If RDY not used, t pw1 becomes 180 ns. Note 2: Timing if t h2 is greater than 170 ns, otherwise 5 ns after CSB rising edge.

Revision 2.00/September 2003  Semtech Corp. data bus. The following figures show the timing diagrams of write and read accesses for this mode. Note 1: Timing with RDY. If RDY not used, t pw1 becomes 180 ns.

Revision 2.00/September 2003  Semtech Corp. Note 1: Timing with RDY. If RDY not used, t pw1 becomes 180 ns.

Revision 2.00/September 2003  Semtech Corp. High and Low times for SCLK define the maximum clock rate. affected by the setting of CLKE, being either 2.0 MHz (500 ns) or 1 MHz (1 us). a maximum clock rate of 2 MHz. With CLKE=1, SCLK has a maximum clock rate of 1 MHz. diagrams for Write and Read access for this mode.

Revision 2.00/September 2003  Semtech Corp.

Revision 2.00/September 2003  Semtech Corp. machine in the up interface sequences the accesses. Further details can be found in the AMD AM27C64 data sheet.

Revision 2.00/September 2003  Semtech Corp. The top package body may be smaller than the bottom package body by as much as 0.15 mm. To be determined at seating plane. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. Details of pin 1 identifier are optional but will be located within the zone indicated. Exact shape of corners can vary. A1 is defined as the distance from the seating plane to the lowest point of the package body. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.

Revision 2.00/September 2003  Semtech Corp. (1) Solderable to this limit. Square package - dimensions apply in both X and Y directions. Typical example. The user is reponsible for ensuring compatibility with PCB manufacturing process, etc.

Revision 2.00/September 2003  Semtech Corp.

Revision 2.00/September 2003  Semtech Corp.

1 Non-Revertive

www.semtech.com76 ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL Revision 2.00/September 2003  Semtech Corp. Ordering Information Ordering Information Ordering Information Ordering Information Ordering Information ISO9001 CERTIFIED REBMUNTRAPR EBMUNTRAP REBMUNTRAP REBMUNTRAPR EBMUNTRAP NOITPIRCSEDN OITPIRCSED NOITPIRCSED NOITPIRCSEDN OITPIRCSED 1.2veR0158SCA PFQLnip001,noitasinorhcnySHDS/TENOS For additional information, contact the following: Semtech Corporation Advanced Communications ProductsSemtech Corporation Advanced Communications ProductsSemtech Corporation Advanced Communications ProductsSemtech Corporation Advanced Communications ProductsSemtech Corporation Advanced Communications Products E-Mail: sales@semtech.com acsupport@semtech.com Internet: http://www.semtech.com USA: Mailing Address: P.O. Box 6097, Camarillo, CA 93011-6097 Street Address: 200 Flynn Road, Camarillo, CA 93012-8790 Tel: +1 805 498 2111, Fax: +1 805 498 3804 FAR EAST: 11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, Taiwan, R.O.C. Tel: +886 2 2748 3380, Fax: +886 2 2748 3390 EUROPE: Units 2 & 3 Park Court, Premier Way, Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN, UK Tel: +44 1794 527 600, Fax: +44 1794 527 601 DisclaimersDisclaimersDisclaimersDisclaimersDisclaimers Life support - This product is not designed or intended for use in life suport equipment, devices or systems, or other critical applications. This product is not authorized or warranted by Semtech Corporation for such use. Right to change - Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised to obtain the latest version of the relevant information before placing orders. Compliance to relevant standards - Operation of this device is subject to the user’s implementation, and design practices. The user is responsible to ensure equipment using this device is compliant to any relevant standards.