ACS8509T

ACS8509 SEMTECH | Alldatasheet

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Revision 2.00/January 2006 © Semtech Corp. Page 1 www.semtech.com ACS8509 SETS ADVANCED COMMUNICATIONS FINAL Synchronous Equipment Timing Source for SONET or SDH Network Elements ADVANCED COMMUNICATIONS FINAL DATASHEET The ACS8509 is a highly integrated, single-chip solution for the Synchronous Equipment Timing Source (SETS) function in a SONET or SDH Network Element. The device generates SONET or SDH Equipment Clocks (SEC) and Frame Synchronization clocks. The ACS8509 is fully compliant with the required international specifications and standards. The device supports Free-run, Locked and Holdover modes. It also supports all three types of reference clock source: recovered line clock, PDH network, and node synchronization. The ACS8509 generates independent SEC and BITS/SSU clocks, an 8 kHz Frame Synchronization clock and a 2 kHz Multi-Frame Synchronization clock. Two ACS8509 devices can be used together in a Master/ Slave configuration mode allowing system protection against a single ACS8509 failure. A microprocessor port is incorporated, providing access to the configuration and status registers for device setup and monitoring. The ACS8509 includes a choice of edge alignment for 8 kHz input, as well as a low jitter n x E1/DS1 output mode. The User can choose between OCXO or TCXO to define the Stratum and/or Holdover performance required. ‹ Suitable for Stratum 3E*, 3, 4E, 4 and SONET Minimum Clock (SMC) or SONET/SDH Equipment Clock (SEC) applications ‹ Meets AT&T, ITU-T, ETSI and Telcordia specifications ‹ Accepts four individual input reference clocks ‹ Generates six output clocks ‹ Supports Free-run, Locked and Holdover modes of operation ‹ Robust input clock source quality monitoring on all inputs ‹ Automatic “hit-less” source switchover on loss of input ‹ Phase build-out for output clock phase continuity during input switchover and mode transitions ‹ Microprocessor interface - Intel, Motorola, Serial, Multiplexed, EPROM ‹ Programmable wander and jitter tracking attenuation

0.1 Hz to 20 Hz

‹ Support for Master/Slave device configuration alignment and hot/standby redundancy ‹ IEEE 1149.1 JTAG Boundary Scan ‹ Single +3.3 V operation, +5 V I/O compatible ‹ Operating temperature (ambient) -40°C to +85°C ‹ Available in 100 pin LQFP package. ‹ Lead (Pb)-free version available (ACS8509T), RoHS and WEEE compliant. Figure 1 Block Diagr am of the ACS8509 SETS Block Diagram Description Features IEEE 1149.1 JTAG Input Port Monitors and Selection Control 4 x SEC PFD Digital Loop Filter Chip Clock Generator DTO TCK TDI TMS TRST TDO F85509 001BLOCKDIA 01 TOUT4 Selector TOUT0 Selecor PFD Digital Loop Filter DTO T0 APLL (output) Frequency Dividers Programmable Outputs: 01 (PECL (default)/LVDS) = Programmable: 19.44 MHz (default), 51.84 MHz (OC-1), 77.76 MHz and

155.52 MHz (OC-3)

02 (TTL/CMOS) = 6.48 MHz (default) 19.44 MHz and 25.92 MHz, and E1/DS1 multiples: 1 x, 2 x, 4 x, 8 x (1.544/2.048 MHz) 03 (TTL/CMOS) = 19.44 MHz (fixed) 04 (TTL/CMOS) = 1.544 MHz/2.048 MHz (E1/DS1) FrSync (TTL/CMOS) = 8 kHz Frame Sync, Fixed 50:50 MSR MFrSync (TTL/CMOS) = 2 kHz Multiframe Sync, Fixed 50:50 MSR 4 x TTL Programmable; 2 kHz 4 kHz N x 8 kHz 1.544/2.048 MHz

6.48 MHz

19.44 MHz

25.92 MHz

38.88 MHz

51.84 MHz

77.76 MHz

T4 DPLL/Freq. Synthesis T0 DPLL/Freq. Synthesis Divider Divider

Revision 2.00/January 2006 © Semtech Corp. Page 2 www.semtech.com ACS8509 SETS Section Page ADVANCED COMMUNICATIONS FINAL DATASHEET Table of Contents

Revision 2.00/January 2006 © Semtech Corp. Page 3 www.semtech.com ACS8509 SETS Section Page ADVANCED COMMUNICATIONS FINAL DATASHEET

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 4 www.semtech.com ACS8509 SETS Figure 2 ACS8509 Pin Diagram Synchronous Equipment T iming Source for SONET or SDH Network Elements Pin Diagram F8509D_002PINDIAG_01

1 AGND

2 TRST

5 AGND

6 VA1+

7 TMS

8 INTREQ

9 TCK

10 REFCLK

11 DGND1

12 VD+

13 VD+

14 DGND

15 DGND

16 VD+

19 VA2+

20 AGND

21 TDO

23 TDI

24 DGND

25 DGND

75 RDY

74 PORB

73 ALE

72 RDB

71 WRB

70 CSB

62 DGND

61 VDD

60 UPSEL0

59 UPSEL1

58 UPSEL2

56 SEC4

54 SEC3

51 SEC2

29 DGND

30 FrSync

31 MFrSync

32 GND_DIFF

33 VDD_DIFF

36 O1POS

37 O1NEG

38 GND_DIFF

39 VDD_DIFF

44 VDD5

45 SYNC2K

48 SEC1

49 DGND

50 VDD

100 SONSDHB

99 MSTSLVB

92 DGND

91 VDD

87 DGND

86 VDD

85 VDD

84 DGND

83 AD0

82 AD1

81 AD2

80 AD3

79 AD4

78 AD5

77 AD6

76 AD7

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 5 www.semtech.com ACS8509 SETS Note...I = Input, O = Output, P = Power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor. Pin Description Table 1 Power Pins Pin Number Symbol I/O Type Description 12, 13, 16 VD+ P - Supply Voltage: Digital supply to gates in analog section, +3.3 Volts ±10%. 33, 39 VDD_DIFF P - Supply Voltage: Digital suppl y for differential ports, +3.3 Volts ±10%. 44 VDD5 P - Digital Supply for +5 Volts Tolerance to Input Pins. Connect to +5 Volts (±10%) for clamping to +5 Volts. Connect to VDD for clamping to +3.3 Volts. Leave floating for no clamping, input pins tolerant up to +5.5 Volts. 50, 61, 85, 86 91 VDD P - Supply Voltage: Digital supply to logic, +3.3 Volts ±10%. 6 VA1+ P - Supply Voltage: Analog supply to clock multiplying PLL, +3.3 Volts ±10%. 19 VA2+ P - Supply Voltage: Analog supply to output PLLs, +3.3 Volts ±10%. 11, 14, 15, 24, 25, 29, 49, 62, 84, 87,92 DGND P - Supply Ground: Digi tal ground for logic 32, GND_DIFF P - Supply Ground: Digital ground for differential ports. 1, 5, AGND P - Supply Ground: Analog grounds. Table 2 Not Connected or Internally Connected Pins Pin Number Symbol I/O Type Description 4, 17, 26 NC NC - Not connected: Leave to Float 3, 18, 22, 27, 28, 34, 35, 40, 41, 42, 43, 46, 47, 52, 53, 55, 57, 89, 93, 94, 96, 97, 98 IC IC - Internally Connected: Leave to Float. Table 3 Other Pins Pin Number Symbol I/O Type Description 2T R S T I T T L D JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan mode. TRST = 0 for Boundary Scan stand-by mode, still allowing correct device operation. If not used connect to GND or leave floating. 7T M S I T T L U JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge of TCK. If not used connect to VDD or leave floating.

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 6 www.semtech.com ACS8509 SETS 8 INTREQ O TTL/CMOS Interru pt Request: Active High software Interrupt output. 9T C K I T T L D JTAG Clock: Boundary Scan clock input. If not used connect to GND or leave floating. This pin may require a capacitor placed between the pin and the nearest GND, to reduce noise pickup. A value of 10 pF should be adequate, but the value is dependent on PCB layout. 10 REFCLK I TTL Reference Clock: 12.800 MHz (refer to “Local Oscillator Clock” on page 8). 21 TDO O TTL/CMOS JTAG Output: Serial test data output. Updated on falling edge of TCK. If not used leave floating. 23 TDI I TTL U JTAG Input: Serial test data Input. Sampled on rising edge of TCK. If not used connect to VDD or leave floating. 30 FrSync O TTL/CMOS Output Reference: 8 kHz Frame Sync output (square wave). 31 MFrSync O TTL/CMOS Output Reference: 2 kHz Multi-Frame Sync output (square wave). 36, O1POS, O1NEG O PECL/LVDS Output Reference O1: Pr ogrammable, default 19.44 MHz. Also 51.84 MHz, 77.76 MHz, 155.52 MHz. MHz, default type PECL.

45 SYNC2K I TTL

D Synchronize 2 kHz: Connect to 2 kHz Multi-Frame Sync output of partner ACS8509 in redundancy system. 48 SEC1 I TTL D Input Reference SEC1: Programmable, default 19.44 MHz (Default Priority 7). 51 SEC2 I TTL D Input Reference SEC2 : Programmable, default 19.44 MHz (Default Priority 8).

54 SEC3 I TTL D Input Reference SEC3: Programmable, default (Master mode)

1.544/2.048 MHz, default (Slave mode) 6.48 MHz. (Default Priority 11).

56 SEC4 I TTL

D Input Reference SEC4 (Priority 13): Programmable, default 1.544/2.048 MHz (Default Priority 13). 58 - 60 UPSEL(2:0) I TTL D Microprocessor Select: Configures the interface for a particular microprocessor type at reset. 63 - 69 A(6:0) I TTL D Microprocessor Interface Address: Address bus for the microprocessor interface registers. A(0) is SDI in Serial mode - output in EPROM mode only.

70 CSB I TTL U Chip Select (Active Low): This pin is asserted Low by the microprocessor to

enable the microprocessor interface - output in EPROM mode only.

71 WRB I TTL U Write (Active Low): This pin is asserted Low by the microprocessor to

initiate a write cycle. In Motorola mode, WRB = 1 for Read.

72 RDB I TTL U Read (Active Low): This pin is asserted Low by the microprocessor to

initiate a read cycle.

73 ALE I TTL D Address Latch Enable: This pin becomes the address latch enable from the

microprocessor. When this pin transitions from High to Low, the address bus inputs are latched into the internal registers. ALE = SCLK in Serial mode. 74 PORB I TTL U Power-On Reset: Master reset. If PORB is forced Low, all internal states are reset back to default values. Table 3 Other Pins (cont...) Pin Number Symbol I/O Type Description

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 7 www.semtech.com ACS8509 SETS

75 RDY O TTL/CMOS Ready/Data Acknowle dge: This pin is asserted High to indicate the device

has completed a read or write operation. 76 - 83 AD(7:0) IO TTL D Address/Data: Multiplexed data/address bus depending on the microprocessor mode selection. AD(0) is SDO in Serial mode. 88 O2 O TTL/CMOS Output Reference 2: Default 6.48 MHz. Also Dig1 (1.544 MHz/2.048 MHz and 2, 4, 8 x), 19.44 MHz, 25.92 MHz 90 O3 O TTL/CMOS Output Reference 3: 19.44 MHz - fixed. 95 O4 O TTL/CMOS Output Reference 4: 1.544/2.048 MHz, (T4 BITS).

99 MSTSLVB I TTL U Master/Slave Select: Sets the initial power-up state (or state after a PORB)

of the Master/Slave selection register, Reg. 34, Bit 1. The register state can be changed after power up by software.

100 SONSDHB I TTL D SONET or SDH Frequency Select: Sets the initial power-up state (or state

after a PORB) of the SONET/SDH frequency selection registers, Reg. 34, Bit 2 and Reg. 38, Bit 5 and Bit 6. When set Low, SDH rates are selected (2.048 MHz etc.) and when set High, SONET rates are selected (1.544 MHz etc.) The register states can be changed after power-up by software. Table 3 Other Pins (cont...) Pin Number Symbol I/O Type Description

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 8 www.semtech.com ACS8509 SETS The ACS8509 is a highly integrated, single-chip solution for the SETS function in a SONET/SDH Network Element, for the generation of SEC and frame synchronization pulses. In Free-run mode, the ACS8509 generates a stable, low noise clock signal from an internal oscillator. In Locked mode, the ACS8509 selects the most appropriate input reference source and generates a stable, low-noise clock signal locked to the selected reference. In Holdover mode, the ACS8509 generates a stable, low- noise clock signal from the internal oscillator, adjusted to match the last known good frequency of the last selected reference source. In all modes, the frequency accuracy, jitter and drift performance of the clock meet the requirements of ITU G.812 [10], G.813[11], G.823[13], and Telcordia GR-1244- CORE[19]. The ACS8509 supports all three types of reference clock source: recovered line clock (TIN1), PDH network synchronization timing (TIN2) and node synchronization (TIN3). The ACS8509 generates independent TOUT0 and TOUT4 clocks, an 8 kHz Frame Synchronization clock and a 2 kHz Multi-Frame Synchronization clock. The ACS8509 has a high tolerance to input jitter and wander. The jitter/wander transfer is programmable (0.1 Hz up to 20 Hz cut-off points). The ACS8509 supports protection. Two ACS8509 devices can be configured to provide protection against a single ACS8509 failure. The protection maintains alignment of the two ACS8509 devices (Master and Slave) and ensures that both ACS8509 devices maintain the same priority table, choose the same reference input and generate the T OUT0 clock, the 8 kHz Frame Synchronization clock and the 2 kHz Multi-Frame Synchronization clock with the same phase. The ACS8509 includes a microprocessor port, providing access to the configuration and status registers for device setup and monitoring. Local Oscillator Clock The Master system clock on the ACS8509 should be provided by an external clock oscillator of frequency 12.80 MHz. The clock specification is important for meeting the ITU/ETSI and Telcordia performance requirements for Holdover mode. ITU and ETSI specifications permit a combined drift characteristic, at constant temperature, of all non-temperature related parameters, of up to 10 ppb per day. The same specifications allow a drift of 1 ppm over a temperature range of 0 to +70°C. Telcordia specifications are somewhat tighter, requiring a non-temperature-related drift of less than 40 ppb per day and a drift of 280 ppb over the temperature range 0 to +50°C. Please contact Semtech for information on crystal oscillator suppliers. Crystal Frequency Calibration The absolute crystal frequency accuracy is less important than the stability since any frequency offset can be compensated by adjustment of register values in the IC. This allows for calibration and compensation of any crystal frequency variation away from its nominal value. ± 50 ppm adjustment would be sufficient to cope with most crystals, in fact the range is an order of magnitude larger due to the use of two 8-bit register locations. The setting of the conf_nominal_frequency register allows for this adjustment. An increase in the register value increases the output frequencies by 0.02 ppm for each LSB step. The default value (in decimal) is 39321. Functional Description Table 4 ITU and ETSI Specification Parameter Value Tolerance ±4.6 ppm over 20 year lifetime Drift (Frequency Drift over supply voltage range of +2.7 V to +3.3 V) ±0.05 ppm/15 seconds @ constant temp. ±0.01 ppm/day @ constant temp. ±1 ppm over temp. range 0 to +70°C Table 5 Telcordia GR-1244 CORE Specification Parameter Value Tolerance ±4.6 ppm over 20 year lifetime Drift (Frequency Drift over supply voltage range of +2.7 V to +3.3 V) ±0.05 ppm/15 seconds @ constant temp. ±0.04 ppm/15 seconds @ constant temp. ±0.28 ppm/over temp. range 0 to +50°C

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 9 www.semtech.com ACS8509 SETS The minimum being 0 and the maximum 65535, gives a -700 ppm to +500 ppm adjustment range of the output frequencies. For example, if the crystal was oscillating at 12.8 MHz + 5 ppm, then the calibration value in the register to give a -5 ppm adjustment in output frequencies to compensate for the crystal inaccuracy, would be: 39321 - (5 / 0.02) = 39071 (decimal) Input Interfaces The ACS8509 supports up to four input reference clock sources from input types TIN1, TIN2 and TIN3 using TTL/ CMOS I/O technologies. These interface technologies support +3.3 V and +5 V operation. Over-Voltage Protection The ACS8509 may require Over-Voltage Protection on input reference clock ports according to ITU Recommendation K.41. Semtech protection devices are recommended for this purpose (see separate Semtech data book). Input Reference Clock Ports Table 6 gives details of the input reference ports, showing the input technologies and the range of frequencies supported on each port; the default spot frequencies and default priorities assigned to each port on power-up or by reset are also shown. Note that SDH and SONET networks use different default frequencies; the network type is pin- selectable using the SONSDHB pin). Specific frequencies and priorities are set by configuration. Although each input port is shown as belonging to one of the types, T IN1, TIN2 or TIN3, they are fully interchangeable as long as the selected speed is within the maximum operating speed of the input port technology. SDH and SONET networks use different default frequencies; the network type is selectable using the config_mode register 34 Hex, bit 2. For SONET, config_mode register 34 Hex, bit 2 = 1, for SDH config_mode register 34 Hex, bit 2 = 0. On power-up or by reset, the default will be set by the state of the SONSDHB pin (pin 100). Specific frequencies and priorities are set by configuration. TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. The actual spot frequencies supported are:

• 2 kHz,
• 4 kHz,
• 8 kHz (and N x 8 kHz),
• 1.544 MHz (SONET)/2.048 MHz (SDH),
• 6.48 MHz,
• 19.44 MHz,
• 25.92 MHz,
• 38.88 MHz,
• 51.84 MHz,
• 77.76 MHz. The frequency selection is programmed via the cnfg_ref_source_frequency register. The internal DPLL will normally lock to the selected input at the frequency of the input, e.g. 19.44 MHz will lock the DPLL phase comparisons at 19.44 MHz. It is, however, possible to utilize an internal pre-divider to the DPLL to divide the input frequency before it is used for phase comparisons in the DPLL. This pre-divider can be used in one of 2 ways: 1. Any of the supported spot frequencies can be divided to 8 kHz by setting the lock8K bit (bit 6) in the appropriate cnfg_ref_source_frequency register location. For good jitter tolerance for all frequencies and for operation at 19.44 MHz and above, use lock8K. It is possible to choose which edge of the 8 kHz input to lock to, by setting the appropriate bit of the cnfg_control1 register. 2. Any multiple of 8 kHz between 1544 kHz to 100 MHz can be supported by using the DivN feature (bit 7 of the cnfg_ref_source_frequency register). Any reference input can be set to use DivN independently of the frequencies and configurations of the other inputs. Any reference input with the DivN bit set in the cnfg_ref_source_frequency register will employ the internal pre-divider prior to the DPLL locking. The cnfg_freq_divn register contains the divider ratio N where the reference input will get divided by (N+1) where 0<N<2 14-1. The cnfg_ref_source_frequency register must be set to the closest supported spot frequency to the input frequency, but must be lower than the input frequency. When using the DivN feature the post-divider

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 10 www.semtech.com ACS8509 SETS Notes: (i) TTL ports (compatible also with C MOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being SONSDHB pin is High SONET is selected, when the SONSDHB pin is Low SDH is selected. (ii) Input port SEC4 is set at 12 on the Master SETS IC and 1 on the Slave SETS IC, as default on power up (or PORB). The default setup of Master or Slave SEC4 priority is determined by the MSTSLVB pin. frequency must be 8 kHz, which is indicated by setting the lock8k bit high (bit 6 in cnfg_ref_source_frequency register). Any input set to DivN must have the frequency monitors disabled (If the frequency monitors are disabled, they are disabled for all inputs regardless of the input configurations, in this case only activity monitoring will take place). Whilst any number of inputs can be set to use the DivN feature, only one N can be programmed, hence all inputs using the DivN feature must require the same division to get to 8 kHz. DivN Examples To lock to 2.000 MHz: 1. The cnfg_ref_source_frequency register is set to 11XX0001 (binary) to set the DivN, lock8k bits, and the frequency to E1/DS1. (XX = “leaky bucket” ID for this input). 2. The cnfg_mode register (34Hex) bit 2 needs to be set to 1 to select SONET frequencies (DS1). 3. The frequency monitors are disabled in cnfg_monitors register (48Hex) by writing 00 to bits 0 and 1. 4. The DivN register is set to F9 Hex (249 decimal). To lock to 10.000 MHz: 1. The cnfg_ref_source_frequency register is set to 11XX0010 (binary) to set the DivN, lock8k bits, and the frequency to 6.48 MHz. (XX = “leaky bucket” ID for this input). 2. The frequency monitors are disabled in cnfg_monitors register (48Hex) by writing 00 to bits 0 and 1. 3. The DivN register is set to 4E1 Hex (1249 decimal). Input Wander and Jitter Tolerance The ACS8509 is compliant to the requirements of all relevant standards, principally ITU Recommendation G.825 [15], ANSI T1.101-1999[1] and ETSI ETS 300 462-5 (1996)[4]. All reference clock inputs have a tight frequency tolerance but a generous jitter tolerance. Pullin, hold-in and pull-out ranges are specified for each input port in Table 7. Minimum jitter tolerance masks are specified in Figures 3 and 4, and Tables 8 and 9, respectively. The ACS8509 will tolerate wander and jitter components greater than those shown in Figure 3 and Figure 4, up to a limit determined by a combination of the apparent long-term frequency offset caused by wander and the eye-closure caused by jitter (the input source will be rejected if the offset pushes Table 6 Input Reference Source Selection and Priority Table Port Number Channel Number (Bin) Port Type Input Port Technology Frequencies Supported Default Priority SEC1 0111 T IN1 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz SEC2 1000 T IN1 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz SEC3 1011 T IN2 TTL/CMOS Up to 100 MHz (see Note (i)) Default (Master) (SONET): 1.544 MHz Default (Master) (SDH): 2.048 MHz Default (Slave) 6.48 MHz 12/1 (Note (ii)) SEC4 1101 T IN2 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 1.544 MHz Default (SDH): 2.048 MHz

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 11 www.semtech.com ACS8509 SETS the frequency outside the hold-in range for long enough to be detected, whilst the signal will also be rejected if the eye closes sufficiently to affect the signal purity). The “8klock” mode should be engaged for high jitter tolerance according to these masks. All reference clock ports are monitored for quality, including frequency offset and general activity. Single short-term interruptions in selected reference clocks may not cause rearrangements, whilst longer interruptions, or multiple, short-term interruptions, will cause rearrangements, as will frequency offsets which are sufficiently large or sufficiently long to cause loss-of-lock in the phase-locked loop. The failed reference source will be removed from the priority table and declared as unserviceable, until its perceived quality has been restored to an acceptable level. The registers sts_curr_inc_offset (address 0C, 0D, 07) report the frequency of the DPLL with respect to the external TCXO frequency. This is a 19-bit signed number with one LSB representing 0.0003 ppm (range of ±80 ppm). Reading this regularly can show how the currently locked source is varying in value e.g. due to wander on its input. The ACS8509 performs automatic frequency monitoring with an acceptable input frequency offset range of ±16.6 ppm. The ACS8509 DPLL has a programmable frequency limit of ±80 ppm. If the range is programmed to be > 16.6 ppm, the frequency monitors should be disabled so the input reference source is not automatically rejected as out of frequency range. Notes: (i) The frequency acceptance and generation range will be ±4.6 ppm around the required frequency when the external crystal frequency accuracy is within a tolerance of ±4.6 ppm. (ii) The fundamental acceptance range and generation range is ± 9.2 ppm with an exact external crystal frequency of 12.8 MHz. This is the default DPLL range, the range is also programmable from 0 to 80 ppm in 0.08 ppm steps. Table 7 Input Reference So urce Jitter Tolerance Jitter Tolerance Frequency Monitor Acceptance Range Frequency Acceptance Range (Pull-in) Frequency Acceptance Range (Hold-in) Frequency Acceptance Range (Pull-out) G.703 ±16.6 ppm ±4.6 ppm (see Note (i)) ±4.6 ppm (see Note (i)) ±4.6 ppm (see Note (i))G.783 G.823 ±9.2 ppm (see Note (ii)) ±9.2 ppm (see Note (ii)) ±9.2 ppm (see Note (ii))GR-1244-CORE

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 12 www.semtech.com ACS8509 SETS Figure 3 Minimum Input Jitter Tolerance (OC-3/STM-1) Frame Sync and Multi-Frame Sync Clocks (Part of TOUT0) Frame Sync (8 kHz) and Multi-Frame Sync (2 kHz) clocks are provided on outputs “FrSync” and “MFrSync”. The FrSync and MFrSync clocks have a 50:50 mark space ratio. These are driven from the TOUT0 clock. They are synchronized with their counterparts in a second ACS8509 device (if used), using the technique described later. Output Clock Ports The device supports a set of main output clocks, TOUT0 and TOUT4, and a pair of secondary output clocks, “Frame Sync” and “Multi-Frame Sync”. The two main output clocks, TOUT0 and TOUT4, are independent of each other and are individually selectable. The two secondary output clocks, Frame Sync and Multi-Frame Sync, are derived from T OUT0. The frequencies of the output clocks are selectable from a range of pre-defined spot frequencies and a variety of output technologies are supported, as defined in Table 10. Low-speed Output Clock (TOUT4) The TOUT4 clock is supplied on output port O4. This port will provide a TTL/CMOS signal at either 1.544 MHz or

2.048 MHz, depending on the setting of the SONSDHB

pin. High-speed Output Clock (Part of TOUT0) The TOUT0 port has multiple outputs. Output O1 is differential and can support clocks up to 155.52 MHz. Output O2 is a TTL/CMOS output with a choice of 11 different frequencies up to 51.84 MHz. Output O3 is a TTL/CMOS output with fixed frequency of 19.44 MHz. Each output is individually configured to operate at the frequencies shown in Table 10 (configuration must be consistent between ACS8509 devices for protection- switching to be effective - output clocks will be phase- aligned between devices). Using the cnfg_differential_outputs register, output O1 can be made to be LVDS or PECL compatible. f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 A4 Jitter and Wander Frequency (log scale) F8530_003MINIPJITTOLOC3STM1_02 Table 8 Amplitude and Frequency Values for Jitter Tolerance (OC-3/STM-1) STM level Peak to peak amplitude (unit Interval) Frequency (Hz) A0 A1 A2 A3 A4 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 13 www.semtech.com ACS8509 SETS Figure 4 Minimum Input Jitter Tolerance (DS1/E1) Low Jitter Multiple E1/DS1 Outputs This feature is activated using the cnfg_control1 register. This sends a frequency of twice the Dig2 rate (see reg addr 39h, bits 7:6) to the APLL instead of the normal 77.76 MHz. For this feature to be used, the Dig2 rate must only be set to 12352 kHz/16384 kHz using the cnfg_T0_output_frequencies register. The normal OC-3 rate outputs are then replaced with E1/DS1 multiple rates. The E1(SONET)/DS1(SDH) selection is made in the same way as for Dig2 using the cnfg_T0_output_enable register. Table 11 shows the relationship between primary output frequencies and the corresponding output in E1/DS1 mode, and from which output they are available. Output Wander and Jitter Wander and jitter present on the output clocks are dependent on: 1. The magnitude of wander and jitter on the selected input reference clock (in Locked mode). 2. The internal wander and jitt er transfer characteristic (in Locked mode). 3. The jitter on the local oscillator clock. 4. The wander on the local oscillator clock (in Holdover mode). Wander and jitter are treated in different ways to reflect their differing impacts on network design. Jitter is always strongly attenuated, whilst wander attenuation can be varied to suit the application and operating state. Wander and jitter attenuation is performed using a digital phase locked loop (DPLL) with a programmable bandwidth. This gives a transfer characteristic of a low pass filter, with a programmable pole. It is sometimes necessary to change the filter dynamics to suit particular circumstances - one example being when locking to a new source, the filter can be opened up to reduce locking time and can then be gradually tightened again to remove wander. Since wander represents a relatively long-term deviation from the nominal operating frequency, it affects the rate of supply of data to the network element. Strong wander attenuation limits the rate of consumption of data to within a smaller range, so a larger buffer store is required to prevent data loss. But, since any buffer store potentially Jitter and Wander Frequency (log scale) Peak-to-peak Jitter and Wander Amplitude (log scale) f1 f2 f3 f4 F8530D_004MINIPJITTOLDS1E1_02 Table 9 Amplitude and Frequency Values for Jitter Tolerance (DS1/E1) Type Spec. Amplitude (UI p-p)F r e q u e n c y ( H z ) A1 A2 F1 F2 F3 F4 DS1 GR-1244-CORE [19] 5 0.1 10 500 8 k 40 k E1 ITU G.823 [13] 1.5 0.2 20 2.4 k 18 k 100k

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 14 www.semtech.com ACS8509 SETS increases latency, wander may often only need to be removed at specific points within a network where buffer stores are acceptable, such as at digital cross connects. Otherwise, wander is sometimes not required to be attenuated and can be passed through transparently. The ACS8509 has programmable wander transfer characteristics in a range from 0.1 Hz to 20 Hz. The wander and jitter transfer characteristic is shown in Figure 5. Wander on the local oscillator clock will not have significant effect on the output clock whilst in Locked mode, so long as the DPLL bandwidth is set high enough so that the DPLL can compensate quickly enough for any frequency changes in the crystal. In Free-run or Holdover mode wander on the crystal is more significant. Variation in crystal temperature or supply voltage both cause drifts in operating frequency, as does ageing. These effects must be limited by careful selection of a suitable component for the local oscillator, as specified in the Section “Local Oscillator Clock” on page 8. Phase Variation There will be a phase shift across the ACS8509 between the selected input reference source and the output clock. This phase shift may vary over time but will be constrained to lie within specified limits. The phase shift is characterized using two parameters, MTIE (Maximum Time Interval Error), and TDEV (Time Deviation), which, although being specified in all relevant specifications, differ in acceptable limits in each one. Typical measurements for the ACS8509 are shown in Figures 6 and 7, for Locked mode operation. Figure 8 shows a typical measurement of Phase Error accumulation in Holdover mode operation. Table 10 Output Reference Source Selection Table Port Name Output Port Technology Frequencies Supported O1 PECL/LVDS (PECL default) 19.44 MHz (default), 51.84 MHz, 77.76 MHz, 155.52 MHz MHz/16.384 MHz, 19.44 MHz, 25.92 MHz O3 TTL/CMOS 19.44 MHz - fixed O4 TTL/CMOS 1.544 MHz/2.048 MHz FrSync TTL/CMOS FrSync, 8 kHz - with a 50:50 MSR MFrSync TTL/CMOS MFrSync, 2 kHz - with a 50:50 MSR Table 11 Multiple E1/DS1 Outputs in Relation to Standard Outputs Mode Freq to APLL APLL Multiplier APLL Freq clk_ filt clk_ filt/2 clk_ filt/4 clk_ filt/6 clk_ filt/8 clk_ filt/12 clk_ filt/16 clk_ filt/48 DPLL Freq n value 16 8 4 Frequencies Available by Output O1 O1

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 15 www.semtech.com ACS8509 SETS Figure 5 Sample of Wander and Jitter Measured Transfer Characteristics The required performance for phase variation during Holdover is specified in several ways depending upon the particular circumstances pertaining: 1. ETSI 300 462-5, Section 9.1, requires that the short term phase error during switchover (i.e., Locked to Holdover to Locked) be limited to an accumulation rate no greater than 0.05 ppm during a 15 second interval. 2. ETSI 300 462-5, Section 9.2, requires that the long term phase error in the Holdover mode should not exceed: {(a1+a2)S+0.5bS 2+c} where: a1 = 50 ns/s (allowance for initial frequency offset) a2 = 2000 ns/s (allowance for temperature variation) b = 1.16 x 10-4 ns/s2 (allowance for ageing) c = 120 ns (allowance for entry into Holdover mode). 3. ANSI Tin1.101-1994, Section 8.2.2, requires that the phase variation be limited so that no more than 255 slips (of 125 µs each) occur during the first day of Holdover. This requires a frequency accuracy better than: Temperature variation is not restricted, except to within the normal bounds of 0 to 50 °C. shows that an initial frequency offset of 50 ppb is permitted on entering Holdover, whilst a drift over temperature of 280 ppb is allowed; an allowance of 40 ppb is permitted for all other effects. 5. ITU G.822, Section 2.6, requires that the slip rate during category (b) operation (interpreted as being applicable to Holdover mode operation) be limited to less than 30 slips (of 125 µs each) per hour: F8530D_005WANJITTXFR_04bitmap.bmp

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 17 www.semtech.com ACS8509 SETS Phase Build-Out Phase Build-Out (PBO) is the function to minimize phase transients on the output SEC clock during input reference switching. If the currently selected input reference clock source is lost (due to a short interruption, out of frequency detection, or complete loss of reference), the second, next highest priority reference source will be selected. During this transition, the Lost_Phase mode is entered. The typical phase disturbance on clock reference source switching will be less than 12 ns on the ACS8509. For clock reference switching caused by the main input failing or being disconnected, then the phase disturbance on the output will still be less than the 120 ns allowed for in the G.813 spec. The actual value is dependent on the frequency being locked to. ITU-T G.813 states that the max allowable short term phase transient response, resulting from a switch from one clock source to another, with Holdover mode entered in between, should be a maximum of 1 µs over a 15 second interval. The maximum phase transient or jump should be less than 120 ns at a rate of change of less than 7.5 ppm and the Holdover performance should be better than 0.05 ppm. On the ACS8509, PBO can be enabled, disabled or frozen using the µP interface. By default, it is enabled. When PBO is enabled, it can also be frozen, which will disable the PBO operation on the next input reference switch, but will remain with the current offset. If PBO is disabled while the device is in the Locked mode, there will be a phase jump on the output SEC clocks as the DPLL locks back to 0 degree phase error. Microprocessor Interface The ACS8509 incorporates a microprocessor interface, which can be configured for the following modes via the bus interface mode control pins UPSEL(2:0) as defined in Table 12. Motorola Mode Parallel data + address: this mode is suitable for use with Motorola's 68x0 type bus. Intel Mode Parallel data + address: this mode is suitable for use with Intel's 80x86 type bus. Multiplexed Mode Data/address: this mode is suitable for use with microprocessors which share bus signals between address and data (e.g., Intel's 80x86 family). Serial Mode This mode is suitable for use with microprocessor which use a serial interface. EPROM Mode This mode is suitable for simple standalone applications where it is required to change the default loading of the register values to suit different applications. This can be done by loading values from an external ROM. The data is read from the ROM automatically after power- up when the UPSEL(2:0) pins are set to “001”. Each register value is stored sequentially, with ROM address 0 corresponding to register address 0 and so on. Table 12 Microprocessor Interface Mode Selection UPSEL(2:0) Mode Description 111 (7) OFF Interface disabled 110 (6) OFF Interface disabled 101 (5) SERIAL Serial uP bus interface 100 (4) MOTOROLA Motorola interface 011 (3) INTEL Intel compatible bus interface 010 (2) MULTIPLEXED Multiplexed bus interface 001 (1) EPROM EPROM read mode 000 (0) OFF Interface disabled

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 18 www.semtech.com ACS8509 SETS The value in the chip_id location (address 00 & 01) is checked to see if it matches the ID number of the ACS8509 (value 213E). Upon a successful number match, the remaining data from the ROM is used to set the internal register values. Only 64 locations in the ROM are required. Register Set All registers are 8-bits wide, organized with the most- significant bit positioned in the left-most bit, with bit significance decreasing towards the right most bit. Some registers carry several individual data fields of various sizes, from single-bit values (e.g. flags) upwards. Several data fields are spread across multiple registers; their organization is shown in the register map, Table 13. Configuration Registers Each configuration register reverts to a default value on power-up or following a reset. Most default values are fixed, but some will be pinsettable. All configuration registers can be read out over the microprocessor port. Status Registers The Status Registers contain readable registers. They may all be read from outside the chip but are not writeable from outside the chip (except for a clearing operation). All status registers are read via shadow registers to avoid data hits due to dynamic operation. Each individual status register has a unique location. Register Access Most registers are of one of two types, configuration registers or status registers, the exceptions being the chip_ID and chip_revision registers. Configuration registers may be written to or read from at any time (the complete 8-bit register must be written, even if only one bit is being modified). All status registers may be read at any time and, in some status registers (such as the sts_interrupts register), any individual data field may be cleared by writing a “1” into each bit of the field (writing a “0” value into a bit will not affect the value of the bit). A description of each register is given in the Register Map, and Register Map Description. Interrupt Enable and Clear Interrupt requests are flagged on pin INTREQ (active High). Bits in the interrupt status register are set (high) by the following conditions: 1. Any reference source becoming valid or going invalid. 2. A change in the operating state (e.g. Locked, Holdover etc.) 3. A brief loss of the currently selected reference source. All interrupt sources are maskable via the mask register, each one being enabled by writing a “1” to the appropriate bit. Any unmasked bit set in the interrupt status register will cause the interrupt request pin to be asserted (high). All interrupts are cleared by writing a “1” to the bit(s) to be cleared in the status register. When all pending unmasked interrupts are cleared the interrupt pin will go inactive (low). The loss of the currently selected reference source will eventually cause the input to be considered invalid, triggering an interrupt. The time taken to raise this interrupt is dependant on the leaky bucket configuration of the activity monitors. The fastest leaky bucket setting will still take up to 128 ms to trigger the interrupt. The interrupt caused by the brief loss of the currently selected reference source is provided to facilitate very fast source failure detection if desired. It is triggered after missing just a couple of cycles of the reference source. Some applications require the facility to switch downstream devices based on the status of the reference sources. In order to provide extra flexibility, it is possible to flag the “main reference failed” interrupt (addr 06, bit 6) on the pin TDO. This is simply a copy of the status bit in the interrupt register and is independent of the mask register settings. The bit is reset by writing to the interrupt status register in the normal way. This feature can be enabled and disabled by writing to bit 6 of register 48Hex. Register Map Shaded areas in the map are “don’t care” and writing either 0 or 1 will not affect any function of the device. Bits labelled Set to 0 or Set to 1 must be set as stated during initialization of the device, either following power-up, or after a power-on reset (POR). Failure to correctly set these bits may result in the device operating in an unexpected way. Some registers do not appear in this list. These are either not used, or have test functionality. Do not write to any undefined registers as this may cause the device to operate in a test mode. If an undefined register has been inadvertently addressed, the device should be reset to ensure the undefined registers are at default values.

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 19 www.semtech.com ACS8509 SETS Table 13 Register Map Addr (Hex) Register Name Data Bit 7 ( m s b ) 654321 0 ( l s b ) 00 chip_id (read only) Device part number (7:0)

01 Device part number (15:8)

02 chip_revision (read only) Chip revision number (7:0) 03 cnfg_control1 (read/write) Multiple E1/T1 O/P Analog div sync Set to 0 8k Edge Polarity Set to 0 Set to 0 04 cnfg_control2 (read/write) Phase loss flag limit Set to 0 Set to 1 Set to 0 05 sts_interrupts (read/write) <SEC2> valid change <SEC1> valid change

06 Operating

Main ref. failed <SEC4> valid change <SEC3> valid change 08 sts_T4_inputs (read/write) T4 ref failed 09 sts_operating_mode (read only) Operating mode (2:0) 0A sts_priority_table (read only) Highest priority valid source Curre ntly selected reference source 0B 3rd highest priority valid source 2nd highest priority valid source 0C sts_curr_inc_offset (read only) Current increment offset (7:0) 0D Current increment offset (15:8)

07 Current increment offset (18:16)

0E sts_sources_valid (read only) <SEC2> <SEC1> 0F <SEC4> <SEC3> 13 sts_reference_sources (read/write) status <SEC2> status <SEC1> 15 status <SEC3> 16 status <SEC4> 1B cnfg_ref_selection_ priority (read/write) programmed_priority <SEC2> programmed_priority <SEC1> 1D programmed_priority <SEC3> 1E programmed_priority <SEC4> 26 cnfg_ref_source_ frequency (read/write) divn lock8k bucket_id <SEC1>(1:0) refe rence_source_frequency <SEC1>(3:0) 27 divn lock8k bucket_id <SEC2>(1:0) refe rence_source_frequency <SEC2>(3:0) 2A divn lock8k bucket_id <SEC3>(1:0) refe rence_source_frequency <SEC3>(3:0) 2C divn lock8k bucket_id <SEC4>(1:0) refe rence_source_frequency <SEC4>(3:0)

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 20 www.semtech.com ACS8509 SETS 30 cnfg_sts_remote_ sources_ valid (read/write) SEC2 SEC1 Set to 0

31 SEC4 SEC3 Set to 0

32 cnfg_operating_mode (read/write) Forced operating mode 33 cnfg_ref_selection (read/write) force_select_reference_source 34 cnfg_mode (read/write) Auto external 2K enable Phase alarm timeout enable Clock edge Holdover Offset enable External 2K Sync enable SONET/ SDH I/P Master/ Slave Reversion mode 35 cnfg_T4 (read/write) Squelch Select T0/T1 Force T1 input source selection (only valid for inputs SEC1 and SEC2) 37 cnfg_uPsel_pins (read only) Microprocessor type 38 cnfg_T0_output_enable (read/write) 1=SONET 0=SDH for Dig2 1=SONET 0=SDH for Dig1 O2 Set to 0 O3 39 cnfg_T0_output_ frequencies (read/write) Digital2 Digital1 3A cnfg_differential_ outputs (read/write) O1 Frequency selection O1 LVDS enable O1 PECL enable 3B cnfg_bandwidth (read/write) Auto b/w switch Acq/lock Acquisition bandwidth Set to 0 Normal/locked bandwidth 3C cnfg_nominal_frequency (read/write) Nominal frequency (7:0) 3D Nominal frequency (15:8) 3E cnfg_holdover_offset (read/write) Holdover offset (7:0) 3F Holdover offset (15:8)

40 Auto

Holdover offset (18:16) 41 cnfg_freq_limit (read/write) DPLL Frequency offset limit (7:0)

42 DPLL Frequency offset

limit (9:8) Table 13 Register Map (cont...) Addr (Hex) Register Name Data Bit 7 ( m s b ) 654321 0 ( l s b )

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 21 www.semtech.com ACS8509 SETS 43 cnfg_interrupt_mask (read/write) <SEC2> valid change <SEC1> valid change Set to 0

44 Operating

Main ref. failed Set to 0 <SEC4> valid change Set to 0 <SEC3> valid change Set to 0 Set to 0

45 T4 ref Set to 0 Set to 0 Set to 0 Set to 0

46 cnfg_freq_divn (read/write) Divide-input-by-n ratio (7:0)

47 Divide-input-by-n ratio (13:8)

48 cnfg_monitors (read/write) Flag ref lost on TDO Ultra-fast switching Freeze phase buildout Phase buildout enable Frequency monitors configuration (1:0) 50 cnfg_activ_upper_ threshold0 (read/write) Configuration 0: Activity alarm set threshold (7:0) 51 cnfg_activ_lower_ threshold0 (read/write) Configuration 0: Activity alarm reset threshold (7:0) 52 cnfg_bucket_size0 (read/write) Configuration 0: Activity alarm bucket size (7:0) 53 cnfg_decay_rate0 (read/write) Cfg 0:decay_rate (1:0) 54 cnfg_activ_upper_ threshold1 (read/write) Configuration 1: Activity alarm set threshold (7:0) 55 cnfg_activ_lower_ threshold1 (read/write) Configuration 1: Activity alarm reset threshold (7:0) 56 cnfg_bucket_size1 (read/write) Configuration 1: Activity alarm bucket size (7:0) 57 cnfg_decay_rate1 (read/write) Cfg 1:decay_rate (1:0) 58 cnfg_activ_upper_ threshold2 (read/write) Configuration 2: Activity alarm set threshold (7:0) 59 cnfg_activ_lower_ threshold2 (read/write) Configuration 2: Activity alarm reset threshold (7:0) 5A cnfg_bucket_size2 (read/write) Configuration 2: Activity alarm bucket size (7:0) Table 13 Register Map (cont...) Addr (Hex) Register Name Data Bit 7 ( m s b ) 654321 0 ( l s b )

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 22 www.semtech.com ACS8509 SETS 5B cnfg_decay_rate2 (read/write) Cfg 2:decay_rate (1:0) 5C cnfg_activ_upper_ threshold3 (read/write) Configuration 3: Activity alarm set threshold (7:0) 5D cnfg_activ_lower_ threshold3 (read/write) Configuration 3: Activity alarm reset threshold (7:0) 5E cnfg_bucket_size3 (read/write) Configuration 3: Activity alarm bucket size (7:0) 5F cnfg_decay_rate3 (read/write) Cfg 3:decay_rate (1:0) 7F cnfg_uPsel (read/write) Microprocessor type Table 13 Register Map (cont...) Addr (Hex) Register Name Data Bit 7 ( m s b ) 654321 0 ( l s b )

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 23 www.semtech.com ACS8509 SETS Register Map Description Table 14 Register Description Addr. (Hex) Register Name Description Default Value (Bin) chip_id This register contains the chip ID. 00 Bits (7:0) Chip ID bits (7:0). 00111110 01 Bits (7:0) Chip ID bits (15:8). 00100001 02 chip_revision This read only register contains the chip revision number. This revision = 1 Last revision (engineering samples) = 0. 00000001 03 cnfg_control1 Bits (7:6) Unused. Bit 5 =1 32/24 MHz to APLL: Feeds 2x Dig2 frequency to the APLL instead of the normal 77.76 MHz. Thus the normal OC-3/STM1 outputs are replaced with multiple E1/T1 rates. Note: Dig2 set bits (Reg. 39h Bits (7:6)) must be set to 11 for this mode. =0 77.76MHz to APLL. Bit 4 =1 Synchronizes the dividers in the output APLL section to the dividers in the DPLL section such that their phases align. This is necessary in order to have phase alignment between inputs and output clocks at OC-3 derived rates (6.48 MHz to 77.76 MHz). Keeping this bit high may be necessary to avoid the dividers getting out of synchronization when quick changes in frequency occur such as a force into Free-run. =0 The dividers may get out of phase following step changes in frequency, but in this mode the correct number of high frequency edges is guaranteed within any synchronization period. The output will frequency lock (default). The device will always remain in synchronization 2 seconds from a reset, before the default setting applies. Bit 3 Test control - leave unchanged, or set to 0. Bit 2 =1 When in 8k locking mode the system will lock to the rising input clock edge. =0 When in 8k locking mode the system will lock to the falling input clock edge. Bits (1:0) Test controls - leave unchanged, or set to 00. XX000000 04 cnfg_control2 Bits (7:6) Unused. Bits (5:3) define the phase loss flag limit. By default set to 4 (100) which corresponds to approximately 140°. A lower value sets a corresponding lower phase limit. The flag limit determines the value at which the DPLL indicates phase lost as a result of input jitter, a phase jump, or a frequency jump on the input. Bits (2:0) Test controls - leave unchanged, or set to 010. XX100010

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 24 www.semtech.com ACS8509 SETS 05 sts_interrupts Bit 7 SEC2 valid change. Bit 6 SEC1 valid change. Bits (5:0) Unused. 00000000 06 Bit 7 Operating mode. Bit 6 Main ref failed. Bit 5 Unused. Bit 4 SEC4 valid change. Bit 3 Unused. Bit 2 SEC3 valid change. Bits (1:0) Unused. 00000000 08 sts_T4_inputs This register holds the status flags of the T OUT4 reference. The alarm once set will hold its state until reset. The bit may be cleared by writing a “1” to it, thus resetting the interrupt. Writing “0”s will have no effect. This bit can also generate an nterrupt. Bits (7:5) Unused. Bit 4 =1 T4 reference failed - no valid T IN1 input (SEC2 or SEC1), T4 DPLL cannot lock to source (default). =0 T4 reference good - valid T IN1 input available. Bits (3:0) Unused. XXX10000 09 sts_operating_mode This read-only register holds the current operating state of the main state machine. Figure 10 shows how the values of the “operating state” variable match with the individual states. Bits (7:3) Unused. Bits (2:0) State:

001 Free-Run (default),

010 Holdover,

100 Locked,

110 Pre-locked,

101 Pre-locked2,

111 Phase lost. XXXXX001 Table 14 Register De scription (cont...) Addr. (Hex) Register Name Description Default Value (Bin)

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 25 www.semtech.com ACS8509 SETS sts_priority_table This is a 16-bit read-only register. Bits (15:12) Third highest priority valid source: this is the channel number of the input reference source which is valid and has the next-highest priority to the second- highest-priority valid source. Bits (11:8) Second highest priority valid source: this is the channel number of the input reference source which is valid and has the next-highest priority to the highest- priority valid source. Bits (7:4) Highest priority valid source: this is the channel number of the input reference source which is valid and has the highest priority - it may not be the same as the currently selected reference source (due to failure history or changes in programmed priority). Bits (3:0) Currently selected reference source: this is the channel number of the input reference source which is currently input to DPLL. Note that these registers are updated by the state machine in response to the contents of the cnfg_ref_selection_priority register and the ongoing status of individual channels; channel number “0000”, appearing in any of these registers, indicates that no channel is available for that priority. 0A Bits (7:4) Highest priority valid source ( sts_priority_table bits (7:4)) Bits (3:0) Currently selected reference source ( sts_priority_table bits (3:0)) 0000000 0B Bits (7:4) 3rd-highest priority valid source ( sts_priority_table bits (15:12)) Bits (3:0) 2nd-highest priority valid source ( sts_priority_table bits (11:8)) 0000000 sts_curr_inc_offset This read-only register contains a signed-integer value representing the 19 significant bits of the current increment offset of the digital PLL. The register may be read periodically to build up a historical database for later use during holdover periods (this would only be necessary if an external oscillator which did not meet the stability criteria described in Local Oscillator Clock section is used). The register will read 00000000 immediately after reset. 0C Bits (7:0) sts_curr_inc_offset bits (7:0) 00000000 0D Bits (7:0) sts_curr_inc_offset bits (15:8) 00000000

07 Bits (7:3) Unused

Bits (2:0) sts_curr_inc_offset bits (18:16) XXXXX000 sts_sources_valid This register contains a bit to show validity for every reference source. =1 Valid source =0 Invalid source (default) 0E Bit 7 SEC2 Bit 6 SEC1 Bits (5:0) Unused 00000000 0F Bits (7:5) Unused Bit 4 SEC4 Bit 3 Unused Bit 2 SEC3 Bits (1:0) Unused XX000000 Table 14 Register De scription (cont...) Addr. (Hex) Register Name Description Default Value (Bin)

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 26 www.semtech.com ACS8509 SETS sts_reference_sources This is a 3-byte register which holds the status of each of the 4 input reference sources. The status of each reference source is shown in a 4-bit field. Each bit is active high. To aid status checking, a copy of each status bit 3 is provided in the sts_sources_valid register. The status is reported as follows: (Each bit may be cleared individually.) Status bit 3 = Source valid (no alarms) (bit 3 is combination of bits (2:0)) (default 0) Status bit 2 = out-of-band alarm (default 1) Status bit 1 = no activity alarm (default 1) Status bit 0 = phase lock alarm (default 0) 13 Bits (7:4) Status of input reference source <SEC2>. Bits (3:0) Status of input reference source <SEC1>. 01100110 15 Bits (7:4) Unused. Bits (3:0) Status of input reference source <SEC3>. 01100110 16 Bits (7:4) Unused. Bits (3:0) Status of input reference source <SEC4>. 01100110 cnfg_ref_selection_ priority This register holds the priority of each of the 4 input reference sources. The priority values are all relative to each other, with lower-valued numbers taking higher priorities. Only the values “1” to “15” (dec) are valid - “0” disables the reference source. Each reference source should be given a unique number, however two sources given the same priority number will be assigned on a first in first out basis. It is recommended to reserve the priority value “1” as this is used when forcing reference selection via the cnfg_ref_selection register. If the User does not intend to use the cnfg_ref_selection register then the priority value “1” need not be reserved. 1B Bits (7:4) Programmed priority of input reference source <SEC2>. Bits (3:0) Programmed priority of input reference source <SEC1>. 10011000 1D Bits (7:4) Unused. Bits (3:0) Programmed priority of input reference source <SEC3>. 11010001 (MSTSLVB=0) 11011100 (MSTSLVB=1) 1E Bits (7:4) Unused. Bits (3:0) Programmed priority of input reference source <SEC4>. 11111110 Table 14 Register De scription (cont...) Addr. (Hex) Register Name Description Default Value (Bin)

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 27 www.semtech.com ACS8509 SETS cnfg_ref_source_ frequency This register is used to set up each of the 4 input reference sources. Bits (7:6) of each byte defines the operation undertaken on the input frequency, in accordance with the following key: 00 The input frequency is fed directly into the DPLL. (default).

01 The input frequency is internally divided down to 8 kHz, before being fed into

the DPLL. (For high jitter tolerance). 10 Unsupported configuration - do not use.

11 Uses the division coefficient stored in registers 46 and 47 (cnfg_freq_divn) to

divide the input by this value prior to being fed into the DPLL. The frequency monitors must be disabled. The divided down frequency should equal 8 kHz. The frequency (3:0) should be set to the nearest spot frequency just below the actual input frequency. The DivN feature works for input frequencies between 1.544 MHz and 100 MHz. Bits (5:4) define which leaky bucket group (0-3) is used, as defined in registers 50 to 5F. (default 00). Bits (3:0) defines the frequency of the reference source in accordance with the following: 0000 8 kHz, 0001 1.544 MHz (SONET)/2.048 MHz (SDH) (a s defined by register 34, bit 2) (default SEC4), 0010 6.48 MHz (default <SEC3> when MSTSLVB = 1), 0011 19.44 MHz (default <SEC3> when MSTSLVB=0, and <SEC1> <SEC2>), 0100 25.92 MHz, 0101 38.88 MHz, 0110 51.84 MHz, 0111 77.76 MHz, 1000 155.52 MHz, 1001 2 kHz, 1010 4 kHz. 26 Frequency of reference source <SEC1>. 00000011 27 Frequency of reference source <SEC2>. 00000011 2A Frequency of reference source <SEC3>. 00000010 (MSTSLVB=0) 00000011 (MSTSLVB=1) 2C Frequency of reference source <SEC4>. 00000001 Table 14 Register De scription (cont...) Addr. (Hex) Register Name Description Default Value (Bin)

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 28 www.semtech.com ACS8509 SETS cnfg_sts_remote_ sources_ valid This register holds the status of the reference sources supplied to the other device in a master/slave configuration. It is a copy of the other device's sts_sources_valid register. The register is part of the protection mechanism.

30 Bits (7:6) Reference sources SEC2:SEC1,

Bits (5:0) Unused, set to 0. 11111111 31 Bits (7:5) Unused. Bits 4 Reference sources SEC4. Bit 3 Unused, set to 0. Bit 2 Reference sources SEC3 Bits (1:0) Unused, set to 0. XX111111 32 cnfg_operating_mode This register is used to force the device into a desired operating state, represented by the binary values shown in Figure 10. Value 0 (hex) allows the control state machine to operate automatically. Bits (7:3) Unused. Bits (2:0) Desired operating state (as per Figure 10). XXXXX000 33 cnfg_ref_selection This register is used to force the device to select a particular input reference source, irrespective of its priority. Writing to this register temporarily raises the selected input to priority “1”. Provided no other input is already programmed with priority “1”, and revertive mode is on, this source will be selected. Bits (7:4) Unused. Bits (3:0) 0110 SEC1,

1010 SEC3,

0111 SEC2,

1100 SEC4. XXXX1111 Table 14 Register De scription (cont...) Addr. (Hex) Register Name Description Default Value (Bin)

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 29 www.semtech.com ACS8509 SETS 34 cnfg_mode This register contains several individual configuration fields, as detailed below: Bit 7 =1 Auto 2 kHz Sync enable: External 2 kHz Sync will be enabled only when the source is locked to 6.48 MHz. Otherwise it will be disabled (default) =0 Auto 2 kHz Sync disable: The user controls this function using bit 3 of this register, as described below. Bit 6 =1 Phase Alarm Timeout enable: The phase alarm will timeout after 100 seconds (default). =0 Phase Alarm Timeout disable: The phase alarm will not timeout and must be reset by software. Bit 5 =1 Rising Clock Edge selected: The device will reference to the rising edge of the external 12.8 MHz crystal oscillator signal =0 Falling edge Edge selected: The device will reference to the falling edge of the external 12.8 MHz crystal oscillator signal (default). Bit 4 =1 Holdover offset enable: The device will adopt the Holdover offset value stored in the cnfg_holdover_offset register, in order to set the frequency in Holdover =0 Holdover offset disable: The device will ignore the value and Holdover will freeze the frequency of the DPLL on entering Holdover mode (default). Bit 3 = 1 External 2 kHz Sync Enable: The device will align the phase of its internally generated Frame Sync signal (8 kHz) and Multi-Frame Sync signal (2 kHz) with that of the signal supplied to the Sync2K pin. The device should be locked to a 6.48 MHz output from another ACS8509. = 0 External 2 kHz Sync Disable: The device will ignore the Sync2k pin. Bit 2 = 1 SONET Mode: The device expects the input frequency of any input channel given the value '0001' in the cnfg_ref_source_frequency register to be 1544 kHz = 0 SDH Mode: The device expects the input frequency of any input channel given the value “0001” in the cnfg_ref_source_frequency register to be 2048 kHz. At start-up or reset the bit value will be defaulted to the setting of pin SONSDHB. This setting can subsequently be altered by changing this bit value. Bit 1 = 1 Master Mode: The device will adopt the master mode and make the active decisions of which source to select, etc. This bit is writeable, but its default value is determined by the pin, MSTSLVB. = 0 Slave Mode: The device will adopt the slave mode and will follow the master device. At start-up or reset the bit value will be defaulted to the setting of pin MSTSLVB. This setting can subsequently be altered by changing this bit value. Bit 0 = 1 Revertive Mode: The device will switch to the highest priority source available shown in the sts_priority_table register, bits (7:4) = 0 Non Revertive Mode: The device will retain the presently selected source (default). 11001000 (MSTSLVB=0) (SONSDHB=0) 11001100 (MSTSLVB=0) (SONSDHB=1) 11000010 (MSTSLVB=1) (SONSDHB=0) 11000110 (MSTSLVB=1) (SONSDHB=1) Table 14 Register De scription (cont...) Addr. (Hex) Register Name Description Default Value (Bin)

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 30 www.semtech.com ACS8509 SETS 35 cnfg_T4 This controls DPLL _T4 (output on O4) and input source selection: Bits (7:6) Unused. Bit 5 =1 DPLL_T4 is turned off (squelched). =0 DPLL_T4 is on (default). Bit 4 Selects which DPLL (T4 or T0) source feeds output O4: =1 DPLL_T0 output is fed to output O4. =0 DPLL_T4 output is fed to output O4. Bits (3:0) Input source selection. The device will switch to the source shown in this field for the generation of the T OUT4 signal. If '0' it will select the highest priority active TIN1. XX000000 37 cnfg_uPsel_pins This read only register returns a value indicating the microprocessor type selected at power up or reset. This is set by the configuration of the UPSEL pins (pins 58 - 60). If the UPSEL pin configuration is changed while the device is operating no effect will take place, but this register will reflect that change, so indicating the configuration that will be implemented at the next power up or reset. The microprocessor type can be changed with the device operational, though register 7F. Bits (7:3) Unused. Bit (2:0) Microprocessor type:

000 OFF (interface disabled),

001 EPROM,

010 MULTIPLEXED,

011 INTEL,

100 MOTOROLA,

101 SERIAL,

110 OFF (interface disabled),

111 OFF (interface disabled). Bits(7:3)= XXXXX Bits(2:0)= UPSEL pin configuration Table 14 Register De scription (cont...) Addr. (Hex) Register Name Description Default Value (Bin)

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 31 www.semtech.com ACS8509 SETS 38 cnfg_T0_output_enable This register contains several individual configuration fields, as follows: Bit 7 Unused. Bit 6 =1 SONET mode selected for Dig2, =0 SDH mode selected for Dig2 (default) - see register cnfg_T0_output_frequencies, Bit 5 =1 SONET mode selected for Dig1, =0 SDH mode selected for Dig1 (default) - see register cnfg_T0_output_frequencies. Bit 4 =1 Output port O2 enabled (default), =0 Output port O2 disabled** - see register cnfg_T0_output_frequencies. Bit 3 Set to 0. Bit 2 =1 Output port O3 enabled (19.44 MHz*) (default), =0 Output port O3 disabled**. Bits (1:0) Set to 0. Notes: * Defaults frequencies are changed to multiples of E1/T1 if the appropriate bit of the cnfg_control1 register is set to 1. For details, see Table 10. ** “Disabled” means that the output port holds a static logic value (the port is not Tri- stated). 00011111 39 cnfg_T0_output_ frequencies This register holds the frequency selections for each output port, as detailed below.* Bits (7:6) Dig2: Bits (5:4) Dig1: 00 1544 kHz/2048 kHz (default), 00 1544 kHz/2048 kHz (default), 01 3088 kHz/4096 kHz, 01 3088 kHz/4096 kHz, 10 6176 kHz/8192 kHz, 10 6176 kHz/8192 kHz, 11 12352 kHz/16384 kHz. 11 12352 kHz/16384 kHz Bits (3:2) Unused. Bits (1:0)O2 00 6.48 MHz (default) 01 25.92 MHz 10 19.44 MHz 11 Dig1. For Dig1/Dig2 the frequency values are shown for SONET/SDH. They are selected via the SONET/SDH bits in register cnfg_T0_output_enable. Note: * The above frequencies are changed to multiples of E1/T1 if the appropriate bit of the cnfg_control1 register is set to 1. For details, see Table 10. 0000100 Table 14 Register De scription (cont...) Addr. (Hex) Register Name Description Default Value (Bin)

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 32 www.semtech.com ACS8509 SETS 3A cnfg_differential_ outputs This register holds the frequency selections and the port-technology type for the differential output O1 as detailed below. Bits (7:6) Output O1: Bits (5:4) Unused 00 155.52 MHz, 01 51.84 MHz, 10 77.76 MHz, 11 19.44 MHz (default). Bits (3:2) Output O1: Bits (1:0) Unused

00 Port disabled,

01 PECL-compatible (default),

10 LVDS-compatible,

11 Unused. 11000110 3B cnfg_bandwidth This register contains information used to control the operation of the digital PLL. When bandwidth selection is set to automatic, the DPLL will use the acquisition bandwidth setting when out of lock, and the normal/locked bandwidth setting when in lock. When set to manual, the DPLL will always use the normal/locked bandwidth setting. Bit 7 =1 Automatic operation, =0 Manual operation (default). Bits (6:4) Acquisition bandwi dth:Bit (2:0) Loop bandwidth: 000 0.1 Hz, 000 0.1 Hz, 001 0.3 Hz, 001 0.3 Hz, 010 0.5 Hz, 010 0.5 Hz, 011 1.0 Hz, 011 1.0 Hz, 100 2.0 Hz, 100 2.0 Hz, 101 4.0 Hz, 101 4.0 Hz (default), 110 8.0 Hz, 110 8.0 Hz, 111 17 Hz (default). 111 17 Hz. Bit 3 Unused. 0111X101 cnfg_nominal_frequency This register holds a 16 bit unsigned integer allowing compensation for offset of the crystal oscillator from the nominal 12.8 MHz. See “Crystal Frequency Calibration” on page 8. Default results in 0 ppm adjustment. 3C Bits (7:0) cnfg_nominal_frequency bits (7:0). 10011001 3D Bits (7:0) cnfg_nominal_frequency bits (15:8). 10011001 Table 14 Register De scription (cont...) Addr. (Hex) Register Name Description Default Value (Bin)

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 33 www.semtech.com ACS8509 SETS cnfg_holdover_offset This register holds a 19-bit signed integer, representing the holdover offset value, which can be used to set the holdover mode frequency when enabled via the holdover offset enabled bit in the cnfg_mode register. 3E Bits (7:0) cnfg_holdover_offset bits (7:0). 00000000 3F Bits (7:0) cnfg_holdover_offset bits (15:8). 00000000

40 Bit 7

=1 Auto Holdover Averaging enable. This enables the frequency average to be taken from 32 samples. One sample taken every 32 seconds, after the frequency has been confirmed to be in-band by the frequency monitors. This gives a 17 minute history of the currently locked to reference source for use in Holdover. (default). =0 Auto Holdover Averaging disabled. Bits (6:3) Unused. Bits (2:0) cnfg_holdover_offset bits (18:16). 1XXXX000 cnfg_freq_limit This register holds a 10 bit unsigned integer representing the pull-in range of the DPLL. It should be set according to the accuracy of crystal implemented in the application, using the following formula: Frequency range ±(ppm) = (cnfg_freq_limit x 0.0785)+0.01647 or cnfg_freq_limit = (Frequency range ± (ppm) - 0.01647) / 0.0785. Default value is ±9.3 ppm. 41 Bits (7:0) cnfg_freq_limit bits (7:0). 01110101 42 Bits (7:2) Unused. Bits (1:0) cnfg_freq_limit bits (9:8). XXXXXX00 cnfg_interrupt_mask Each bit, if set to 0 will disable the appropriate interrupt source in either the interrupt status register or the sts_T4_inputs register. 43 cnfg_interrupt_mask bits (7:0): Bit 7 SEC2. Bit 6 SEC1. Bits (5:0) Set to 0. 11111111 44 cnfg_interrupt_mask bits (15:8): Bit 7 Operating mode. Bit 6 Main Ref failed. Bit 5 Set to 0. Bit 4 SEC4. Bit 3 Set to 0. Bit 2 SEC3. Bits (1:0) Set to 0. 11111111 45 cnfg_interrupt_mask bits (20:16): Bits (7:5) Set to 0. Bit 4 T4 ref. Bits (3:0) Set to 0. XXX11111 Table 14 Register De scription (cont...) Addr. (Hex) Register Name Description Default Value (Bin)

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 34 www.semtech.com ACS8509 SETS cnfg_freq_divn This 14-bit integer is used as the divisor for any input applied to SEC1 to SEC4 to get the phase locking frequency desired. Only active for inputs with the DivN bit set to “1”. This will cause the input frequency to be divided by (N+1) prior to phase comparison, e.g. program N to: ((input freq)/ 8 kHz) -1 The reference_source_frequency bits should be set to reflect the closest spot frequency to the input frequency, but must be lower than the input frequency. 46 Bits (7:0) cnfg_freq_divn bits (7:0). 00000000 47 Bits (7:6) Unused. Bits (5:0) cnfg_freq_divn bits (13:8). XX000000 48 cnfg_monitors This 7-bit register allows global configuration of monitors and control of phase build- out. Bit 7 Unused. Bit 6 =1 Enables value of the main_ref_failed interrupt to be driven out of pin TDO, =0 Disables value of the main_ref_failed interrupt from being driven out of pin TDO (default). Bit 5 =1 Enables ultra fast switching: Allows the DPLL to raise an inactivity alarm on the currently selected source after missing only a few cycles. See “Ultra Fast Switching” on page 37, =0 Normal operation (default). Bit 4 Unused. Bit 3 =1 Will freeze the output phase relationship with the current input to output phase offset, =0 Allows changes in input to output phase offset (Normal phase buildout mode) (default). Bit 2 =1 Enables phase build out (default), =0 DPLL will always lock to 0°. Bits (1:0) are for configuring frequency monitors- 00 = off, 01 = 15 ppm (default), others are reserved for future use. X0000101 50 cnfg_activ_upper_ threshold0 Bits (7:0) set the value in the leaky bucket that causes the activity alarm to be raised. 00000110 51 cnfg_activ_lower_ threshold0 Bits (7:0) set the value in the leaky bucket that causes the activity alarm to be cleared. 00000100 52 cnfg_bucket_size0 Bits (7:0) set the maximum value that the leaky bucket can reach given an inactive input. 00001000 Table 14 Register De scription (cont...) Addr. (Hex) Register Name Description Default Value (Bin)

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 35 www.semtech.com ACS8509 SETS 53 cnfg_decay_rate0 Bits (7:2)Unused Bits (1:0) control the leak rate of the leaky bucket. The fill-rate of the bucket is +1 for every 128 ms interval that has experienced some level of inactivity. The decay rate is programmable in ratios of the fill rate. The ratio can be set to 1:1, 2:1, 4:1, 8:1 by using values of 00, 01, 10, 11 respectively. However, these buckets are not “true” leaky buckets in nature. The bucket stops “leaking” when it is being filled. This means that the fill and decay rates can be the same (00 = 1:1) with the net effect that an active input can be recognized at the same rate as an inactive one. XXXXXX01 54 cnfg_activ_upper_ threshold1 As for Reg. 50 but for bucket 1 00000110 55 cnfg_activ_lower_ threshold1 As for Reg. 51 but for bucket 1 00000100 56 cnfg_bucket_size1 As for Reg. 52 but for bucket 1 00001000 57 cnfg_decay_rate1 As for Reg. 53 but for bucket 1 XXXXXX01 58 cnfg_activ_upper_ threshold2 As for Reg. 50 but for bucket 2 00000110 59 cnfg_activ_lower_ threshold2 As for Reg. 51 but for bucket 2 00000100 5A cnfg_bucket_size2 As for Reg. 52 but for bucket 2 00001000 5B cnfg_decay_rate2 As for Reg. 53 but for bucket 2 XXXXXX01 5C cnfg_activ_upper_ threshold3 As for Reg. 50 but for bucket 3 00000110 5D cnfg_activ_lower_ threshold3 As for Reg. 51 but for bucket 3 00000100 5E cnfg_bucket_size3 As for Reg. 52 but for bucket 3 00001000 5F cnfg_decay_rate3 As for Reg. 53 but for bucket 3 XXXXXX01 7F cnfg_uPsel Bits (7:3) Unused. Bits (2:0) can be used to change the mode of the microprocessor interface. The interface will initially be set as the pins UPSEL (pins 58 - 60) - the pin set up can be read via register 37 (cnfg_uPsel_pins). At power up or reset the device will default to this setting. This register can be used to change the microprocessor mode after start up, supporting booting from EPROM and subsequently communicating via another mode. At start up the EPROM will down load the pre-programmed settings for all the registers, and as the last operation, action the change of interface with this last register. It is recommended that this function is only used for EPROM start up applications, as subsequent versions of this device may only allow operation in this way. The bits are defined in Table 11 or as given in Reg. 37 of the register map description. Bits(7:3)= XXXXX Bits(2:0)= Pin dependent Table 14 Register De scription (cont...) Addr. (Hex) Register Name Description Default Value (Bin)

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 36 www.semtech.com ACS8509 SETS Selection of Input Reference Clock Source Under normal operation, the input reference sources are selected automatically by an order of priority. But, for special circumstances, such as chip or board testing, the selection may be forced by configuration. Automatic operation selects a reference source based on its pre-defined priority and its current availability. A table is maintained which lists all reference sources in the order of priority. This is initially downloaded into the ACS8509 via the microprocessor interface by the Network Manager, and is subsequently modified by the results of the ongoing quality monitoring. In this way, when all the defined sources are active and valid, the source with the highest programmed priority is selected but, if this source fails, the next-highest source is selected, and so on. Restoration of repaired reference sources is handled carefully to avoid inadvertent disturbance of the output clock. The ACS8509 has two modes of operation; Revertive and Non-Revertive. In Revertive mode, if a revalidated (or newly validated) source has a higher priority than the reference source which is currently selected, a switchover will take place. Many applications prefer to minimize the clock switching events and choose Non-Revertive mode. In Non-Revertive mode, when a re-validated (or newly validated) source has a higher priority then the selected source will be maintained. The re-validation of the reference source will be flagged in the sts_sources_valid register and, if not masked, will generate an interrupt. Selection of the re-validated source can only take place under software control - the software should briefly enable Revertive mode to affect a switchover to the higher priority source. If the selected source fails under these conditions the device will indicate that it is still locked to the failed reference. It will not select the higher priority source until instructed to do so by the software; by briefly setting the Revertive mode bit. When there is a reference available with higher priority than the selected reference, there will be NO change of reference source as long as the Non-Revertive mode remains on AND the device will remain indicating a locked state on the failed reference. This is the case even if there are lower priority references available or the currently selected reference fails. When the ONLY valid reference sources that are available have a lower priority than the selected reference, a failure of the selected reference will always trigger a switchover, regardless of whether Revertive or Non-Revertive mode has been chosen. Also, in a Master/Slave redundancy-protection scheme, the Slave device(s) must follow the Master device. The alignment of the Master and Slave devices is part of the protection mechanism. The availability of each source is determined by a combination of local and remote monitoring of each source. Each input reference source supplied to each ACS8509 device is monitored locally and the results are made available to other devices. Forced Control Selection A configuration register, cnfg_ref_selection, controls both the choice of automatic or forced selection and the selection itself (when forced selection is required). The forced selection of an input reference source occurs when the cnfg_ref_selection variable contains a non-zero value, the value then representing the input port required to be selected. This is not the normal mode of operation, and the cnfg_ref_selection variable is defaulted to the all-one value on reset, thereby adopting the automatic selection of the reference source. Automatic Control Selection When an automatic selection is required, the cnfg_ref_selection register must be set to all zero or all one. The configuration registers, cnfg_ref_selection_priority, held in the µP port block, consists of 3, 8-bit registers organised as one 4-bit register per input reference port. Each register holds a 4- bit value which represents the desired priority of that particular port. Unused ports should be given the value, “0000” or “1111”, in the relevant register to indicate they are not to be included in the priority table. On power-up, or following a reset, the whole of the configuration file will be defaulted to the values defined by Table 6. The selection priority values are all relative to each other, with lower- valued numbers taking higher priorities. Each reference source should be given a unique number, the valid values are 1 to 15 (dec). A value of 0 disables the reference source. However if two or more inputs are given the same priority number those inputs will be selected on a first in, first out basis. If the first of two same priority number sources goes invalid the second will be switched in. If the first then becomes valid again, it becomes the second source on the first in, first out basis, and there will not be a switch. If a third source with the same priority number as the other two becomes valid, it joins the priority list on the same first in, first out basis. There is no implied priority based on the channel numbers.

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 37 www.semtech.com ACS8509 SETS The input port <SEC3> is for the connection of the synchronous clock of the TOUT0 output of the Master device (or the active-Slave device), to be used to align the T OUT0 output with the Master (or active-Slave) device if this device is acting in a subordinate-Slave or subordinate-Master role. Ultra Fast Switching A reference source is normally disqualified after the leaky bucket monitor thresholds have been crossed. An option for a faster disqualification has been implemented, whereby if register 48H, bit 5 (Ultra Fast Switching), is set then a loss of activity of just a few reference clock cycles will set the “no activity alarm” and cause a reference switch. This can be chosen to cause an interrupt to occur instead of or as well as causing the reference switch. The sts_interrupts register 05 Hex Bit 14 (main_ref_failed) of the interrupt status register is used to flag inactivity on the reference that the device is locked to much faster than the activity monitors can support. If bit 6 of the cnfg_monitors register (flag ref loss on TDO) is set, then the state of this bit is driven onto the TDO pin of the device. The flagging of the loss of the main reference failure on TDO is simply allowing the status of the sts_interrupt bit 14 to be reflected in the state of the TDO output pin. The pin will, therefore remain High until the interrupt is cleared. This functionality is not enabled by default so the usual JTAG functions can be used. When JTAG is normally used straight out of power-up, then this feature will have no bearing on the functionality. The TDO flagging feature will need to be disabled if JTAG is not enabled on power- up and the feature has since been enabled. When the TDO output from the ACS8509 is connected to the TDI pin of the next device in the JTAG scan chain, the implementation should be such that a logic change caused by the action of the interrupt on the TDI input should not effect the operation when JTAG is not active. Clock Quality Monitoring Clock quality is monitored and used to modify the priority tables of the local and remote ACS8509 devices. The following parameters are monitored: 1. Activity (toggling) 2. Frequency (This monitoring is only performed when there is no irregular operation of the clock or loss of clock condition) Any reference source which suffers a loss-of-signal, loss- of-activity, loss-of-regularity or clock out-of-band condition will be declared as unavailable. Clock quality monitoring is a continuous process which is used to identify clock problems. There is a difference in dynamics between the selected clock and the other reference clocks. Anomalies occurring on non-selected reference sources affect only that source's suitability for selection, whereas anomalies occurring on the selected clock could have a detrimental impact on the accuracy of the output clock. Anomalies, whether affecting signal purity or signal frequency, could induce jitter or frequency offsets in the output clock, leading to anomalous behavior. Anomalies on the selected clock, therefore, have to be detected as they occur and the phase locked loop must be temporarily isolated until the clock is once again pure. The clock monitoring process cannot be used for this because the high degree of accuracy required dictates that the process be slow. To achieve the immediacy required by the phase locked loop requires an alternative mechanism. The phase locked loop itself contains appropriate circuitry, based around the phase detector, and isolates itself from the selected reference source as soon as a signal impurity is detected. It can likewise respond to frequency offsets outside the permitted range since these result in saturation of the phase detector. When the phase locked loop is isolated from the reference source, it is essentially operating in a Holdover state; this is preferable to feeding the loop with a standby source, either temporarily or permanently, since excessive phase excursions on the output clock are avoided. Anomalies detected by the phase detector are integrated in a leaky bucket accumulator. Occasional anomalies do not cause the accumulator to cross the alarm setting threshold, so the selected reference source is retained. Persistent anomalies cause the alarm setting threshold to be crossed and result in the selected reference source being rejected.

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 38 www.semtech.com ACS8509 SETS Figure 9 Inactivity and Irregularity Monitoring Leaky Bucket Timing The time taken (in seconds) to raise an inactivity alarm on a reference source that has previously been fully active (Leaky Bucket empty) will be: (cnfg_upper_threshold_n) / 8 where n is the number (0 to 3) of the Leaky Bucket Configuration. If an input is intermittently inactive then this time can be longer. The default setting of cnfg_upper_threshold_n is 6, therefore the default time is 0.75 s. The time taken (in seconds) to cancel the activity alarm on a previously completely inactive reference source is calculated, for a particular Leaky Bucket, as: (a) x (b - c)]/ 8 where: a = cnfg_decay_rate_n b = cnfg_bucket_size_n c = cnfg_lower_threshold_n (where n = the number (0 to 3) of the relevant Leaky Bucket Configuration in each case). Activity Monitoring The ACS8509 has a combined inactivity and irregularity monitor. The ACS8509 uses a “leaky bucket” accumulator, which is a digital circuit which mimics the operation of an analog integrator, in which input pulses increase the output amplitude but die away over time. Such integrators are used when alarms have to be triggered either by fairly regular defect events, which occur sufficiently close together, or by defect events which occur in bursts. Events which are sufficiently spread out should not trigger the alarm. By adjusting the alarm setting threshold, the point at which the alarm is triggered can be controlled. The point at which the alarm is cleared depends upon the decay rate and the alarm clearing threshold. On the alarm setting side, if several events occur close together, each event adds to the amplitude and the alarm will be triggered quickly; if events occur a little more spread out, but still sufficiently close together to overcome the decay, the alarm will be triggered eventually. If events occur at a rate which is not sufficient to overcome the decay, the alarm will not be triggered. On the alarm clearing side, if no defect events occur for a sufficient time, the amplitude will decay gradually and the alarm will be cleared when the amplitude falls below the alarm clearing threshold. The ability to decay the amplitude over time allows the importance of defect events to be reduced as time passes by. This means that, in the case of isolated events, the F8530D_026Inact_Irreg_Mon_02 Inactivities/Irregularities Programmable Fall Slopes Reference Source Leaky Bucket Response Alarm bucket_size upper_threshold lower_threshold (all programmable)

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 39 www.semtech.com ACS8509 SETS alarm will not be set, whereas, once the alarm becomes set, it will be held on until normal operation has persisted for a suitable time (but if the operation is still erratic, the alarm will remain set). See Figure 9. The “leaky bucket” accumulators are programmable for size, alarm set & reset thresholds and decay rate. Each source is monitored over a 128 ms period. If, within a 128 ms period, an irregularity occurs that is not deemed to be due to allowable jitter/wander, then the accumulator is incremented. The accumulator will continue to increment up to the point that it reaches the programmed bucket size. The “fill rate” of the leaky bucket is, therefore, 8 units/second. The “leak rate” of the leaky bucket is programmable to be in multiples of the fill rate (x1, x0.5, x0.25 and x0.125) to give a programmable leak rate from 8 units/sec down to 1 unit/sec. A conflict between trying to “leak” at the same time as a “fill” is avoided by preventing a “leak” when a “fill” event occurs. Disqualification of a non-selected reference source is based on inactivity, or on an out of band result from the frequency monitors. The currently selected reference source can be disqualified for phase, frequency, inactivity or if the source is outside the DPLL lock range. If the currently selected reference source is disqualified, the next highest priority, active reference source is selected. Frequency Monitoring The ACS8509 performs frequency monitoring to identify reference sources which have drifted outside the acceptable frequency range of ±16.6 ppm (measured with respect to the output clock). The sts_reference_sources out-of-band alarm for a particular reference source is raised when the reference source is outside the acceptable frequency range. The ACS8509 DPLL has a programmable frequency limit of ±80 ppm. If the range is programmed to be > 16.6 ppm, the frequency monitors should be disabled so the input reference source is not automatically rejected as out of frequency range. Modes of Operation The ACS8509 has three primary modes of operation (Free-run, Locked and Holdover) supported by three secondary, temporary modes (Pre-Locked, Lost_Phase and Pre-Locked2). These are shown in the State Transition Diagram, Figure 10. The ACS8509 can operate in Forced or Automatic control. On reset, the ACS8509 reverts to Automatic Control, where transitions between states are controlled completely automatically. Forced Control can be invoked by configuration, allowing transitions to be performed under external control. This is not the normal mode of operation, but is provided for special occasions such as testing, or where a high degree of hands-on control is required. Free-run mode The Free-run mode is typically used following a power-on- reset or a device reset before network synchronization has been achieved. In the Free-run mode, the timing and synchronization signals generated from the ACS8509 are based on the Master clock frequency provided from the external oscillator and are not synchronized to an input reference source. The frequency of the output clock is a fixed multiple of the frequency of the external oscillator, and the accuracy of the output clock is equal to the accuracy of the Master clock. The transition from Free-run to Pre-locked occurs when the ACS8509 selects a reference source. Pre-Locked mode The ACS8509 will enter the Locked state in a maximum of 100 seconds, as defined by GR-1244-CORE specification, if the selected reference source is of good quality. If the device cannot achieve lock within 100 seconds, it reverts to Free-run mode and another reference source is selected. Locked mode The Locked mode is used when an input reference source has been selected and the PLL has had time to lock. When the Locked mode is achieved, the output signal is in phase and locked to the selected input reference source. The selected input reference source is determined by the priority table. When the ACS8509 is in Locked mode, the output frequency and phase follows that of the selected input reference source. Variations of the external crystal frequency have a minimal effect on the output frequency. Only the minimum to maximum frequency range is affected. Note that the term, “in phase”, is not applied in the conventional sense when the ACS8509 is used as a frequency translator (e.g., when the input frequency is 2.048 MHz and the output frequency is 19.44 MHz) as

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 40 www.semtech.com ACS8509 SETS the input and output cycles will be constantly moving past each other; however, this variation will itself be cyclical over time unless the input and output are not locked. Lost_Phase mode Lost-phase mode is entered when the current phase error, as measured within the DPLL, is larger than a preset limit (see register 04, bits 5:3), as a result of a frequency or phase transient on the selected reference source. This mode is similar in behavior to the Pre-locked or Pre-locked(2) modes, although in this mode the DPLL is attempting to regain lock to the same reference rather than attempt lock to a new reference. If the DPLL cannot regain lock within 100 s, the source is disqualified, and one of the following transitions takes place: 1. Go to Pre-Locked(2); - If a known-good standby source is available. 2. Go to Holdover; - If no standby sources are available. Holdover mode The Holdover mode is used when the ACS8509 has been in Locked mode for long enough to acquire stable frequency data, but the final selected reference source has become unavailable and a replacement has not yet been qualified for selection. In Holdover mode, the ACS8509 provides the timing and synchronization signals to maintain the Network Element (NE), but they are not phase locked to any input reference source. The timing is based on a stored value of the frequency ratio obtained during the last Locked mode period. To allow for further development of the way the internal algorithm operates, and to allow for customized switching behavior, the switch to and from Holdover state may be controlled by external software. The device must be set in either “manual” mode or “automatic” mode: 1. Register cnfg_mode bit holdover offset enable set high (manual mode). The Holdover frequency is determined by the value in register cnfg_holdover_offset. This is a 19 bit signed number, with a LSB resolution of 0.0003 ppm, which gives an adjustment range of ±80 ppm. This value can be derived from a reading of the register sts_curr_inc_offset (addr 0D, 0C and 07) which gives, in the same format, an indication of the current output frequency deviation, which would be read when the device is locked. If required, this value could be read by an external microcontroller and averaged over the time required. The averaged value could then be fed to the cnfg_holdover_offset register ready for setting of the averaged frequency value when the device enters Holdover mode. The sts_curr_inc_offset value is internally derived from the Digital Phase Locked Loop (DPLL) integral path value, which already represents a well averaged measure of the current frequency, depending on the loop bandwidth selected. 2. Register cnfg_mode bit holdover offset enable set low (automatic mode). In automatic control, the device can be run in one of two ways:

2.1 Register cnfg_holdover_offset register 40 bit 7 auto

holdover averaging is set high. The value is averaged internally over 32 samples at 32 seconds apart, giving the average frequency over approximately the last 20 minutes. The proportional DPLL path is ignored so that recent signal disturbances do not affect the Holdover frequency value. If the device has been previously correctly locked, missing pulses in the input clock stream fed to the SETS IC are ignored, hence also avoiding any frequency disturbances to the output frequency value when an input clock source fails.

2.2 Register cnfg_holdover_offset register 40 bit 7 auto

holdover averaging is set low. This simply freezes the DPLL at the current frequency (as reported by the sts_curr_inc_offset register). The proportional DPLL path is ignored so that recent signal disturbances do not affect the Holdover frequency value. Automatic control with internal averaging (option 2.1) is the default condition. If the TCXO frequency is varying due to temperature fluctuations in the room, then the instantaneous value can be different from the average value, and then it may be possible to exceed the 0.05 ppm limit (depending on how extreme the temperature fluctuations are). It is advantageous to shield the TCXO to slow down frequency changes due to drift and external temperature fluctuations. The frequency accuracy of Holdover mode has to meet the ITU-T, ETSI and Telcordia performance requirements. The performance of the external oscillator clock is critical in this mode, although only the frequency stability is important - the stability of the output clock in Holdover is directly related to the stability of the external oscillator.

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 41 www.semtech.com ACS8509 SETS Pre-Locked(2) mode This state is very similar to the Pre-Locked state. It is entered from the Holdover state when a reference source has been selected and applied to the phase locked loop. It is also entered if the device is operating in Revertive mode and a higher-priority reference source is restored. Upon applying a reference source to the phase locked loop, the ACS8509 will enter the Locked state in a maximum of 100 seconds, as defined by GR-1244-CORE specification, if the selected reference source is of good quality. If the device cannot achieve lock within 100 seconds, it reverts to Holdover mode and another reference source is selected. Protection Facility The ACS8509 supports redundancy protection. The primary functions of this include: - Alignment of the priority tables of both Master and Slave ACS8509 devices so as to align the selection of reference sources of both Master and Slave ACS8509 devices. - Alignment of the phases of the 8 kHz and 2 kHz clocks in both Master and Slave ACS8509 devices to within one cycle of the 77.76 MHz internal clock. When two ACS8509 devices are to be used in a redundancy-protection scheme within an NE, one will be designated as the Master and the other as the Slave. It is expected that an NE will use the T OUT0 output for its internal operations because the TOUT4 output is intended to feed an SSU/BITS system. An SSU/BITS will not be bothered by phase differences between signals arriving from different sources because it typically incorporates line build-out functions to absorb phase differences on reference inputs. This means that the phasing of the composite clocks between two ACS8509 devices do not have to be mutually-aligned. The same is not true, however, of the T OUT0 output signals (O1 ,O2, O3, Frame clock and Multi-Frame clock). It is usually important to align the phases of all equivalent TOUT0 signals generated by different sources so that switch-over from one device to another does not affect the internal operations of the NE. Both ACS8509 devices will produce the same signals, which will be routed around the NE to the various consumers (clock sinks). With the possible exception of a through-timing mode, the signals from the Master device will be used by all consumers, unless the Master device fails, when each consumer will switch over to the signals generated by the Slave device. Switchover to a new T OUT0 clock should be as hitless as possible. This requires the signals of both ACS8509 devices to be phase aligned at each consumer. Phase alignment requires frequency alignment. To ensure that both devices can generate output clocks locked to the same source, both devices are supplied with the same reference sources on the same input ports and will have identical priority tables. Failures of selected reference sources will result in both ACS8509 devices making the same updates to their priority tables as availability information will be updated in both devices. Although, in principle, the priority tables will be the same if the same reference sources are used on the same input port on each device, in practice, this is only true if the reference sources actually arrive at each device - failures of a source seen only by one device and not by the other, such as could be caused, for example, by a backplane connector failure, would result in the priority tables becoming misaligned. It is thus necessary to force the priority tables to be aligned under normal operating conditions so that the devices can make the same decisions - this can be achieved by loading the availability seen by one device (via the sts_reference_sources register) into the cnfg_sts_remote_sources_valid register of the other device. Another factor which could affect hit-less switching is the frequency of the local oscillator clock used by each ACS8509 device: these clocks are not mutually aligned and, whilst this has no impact on the frequency of the output clocks during locked mode, it could cause the output frequencies to diverge during Holdover mode if no action were taken to avoid it. In order to maintain alignment of the output frequencies of each ACS8509 device even during Holdover, the Master device's 6.48 MHz output is fed into the Slave device on its SEC3 pin, whilst the Multi-Frame Sync (2 kHz) output is fed to the Sync2k input of the Slave. In this way, the Slave locks to the master's output and remains locked whilst the Master moves between operating states. Only when the Master fails does the Slave use its own reference inputs - should the Master have been in the Holdover state, the Slave device will see the same lack of reference sources and also enter the Holdover state. This scheme also provides a convenient way to phase-align all TOUT0 output clocks in Master and Slave devices, and also to detect the failure of the Master device.

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 42 www.semtech.com ACS8509 SETS If a Master device fails, the Slave has to take over responsibility for the generation of the output clocks, including the 8 kHz and 2 kHz Frame and Multi-Frame clocks. The Slave device is also given responsibility for building the priority table and performing the reference switching operations. The Slave device, therefore, adopts a more active role when the Master has failed. The cnfg_mode register 34 (Hex) Bit 1 contains the Master/Slave control bit to determine the designation of the device. To restore redundancy protection, the Master has to be repaired and replaced. When this occurs, the new Master cannot immediately adopt its normal role because it must not cause phase hits on the output clocks. It has, therefore, to adopt a subordinate role to the active Slave device, at least until such time as it has acquired alignment to the 8 kHz and 2 kHz frame and Multi-Frame clocks and the priority table of the Slave device; then, when a switch-back (restoration) is ordered, the Master can take over responsibility. These activities, in Master or Slave operation, are summarized in Table 15 and described in detail in Application Note AN-SETS-2. Alignment of Priority Tables in Master and Slave ACS8509 Correct protection will only be achieved by connecting individual reference sources to the same input ports on each device and priority tables in each device must be aligned to each other. The Master device must take account of the availability of each reference source seen by another device and a Slave device must adopt the same order of priority as the Master device (except that the Slave's highest-priority input is SEC3). Both devices monitor the reference sources and decide the availability of each source; if the failure of a reference source is seen by both devices, they will both update their priority tables - however, if the reference source failure is only seen by one device and not by both, the priority tables could get out of step: this could be catastrophic if it resulted in two devices choosing different reference sources since any slight differences in frequency variation over time (e.g. wander) would mis- align the phase of the 8 kHz Frame and 2 kHz Multi-Frame clocks produced by the individual devices, resulting in phase hits on switchover. It is therefore important that the same priority table be built by each device, using the reference source availability seen by each device. The monitoring of the reference sources performed by a Master ACS8509 results in a list of available sources being placed in a sts_valid_sources register. This information is used within the device as one of the masks used to build the device's priority table. The information is passed to the Slave device and used to configure the cnfg_sts_remote_sources_valid register so that it can use it as a mask in building its own priority tables. The information is passed between devices using the microprocessor port. Alignment of the Selection of Reference Sources for TOUT4 Generation in the Master and Slave ACS8509 As stated previously, there is no need to align the phases of the TOUT4 outputs in Master and Slave devices. There is a need, however, to ensure that all devices select the same reference source. But, since there is no Holdover mode required for the generation of the T OUT4 clock, and every reference source is continuously monitored within each device, it is permissible to rely on external intelligence to command a switchover to an alternative source should the selected one fail. The time delay involved in detecting the failure, indicating it to the outside and selecting a new source, will result only in the SSU/BITS entering its Holdover mode for a short time. Alignment of the Phases of the 8 kHz and 2 kHz Clocks in both Master and Slave ACS8509 In addition to aligning the edges of the TOUT0 outputs of Master and Slave devices, it is necessary to align the edges of the Frame and Multi-Frame clocks. If this is not performed, frame alignment may be lost in distant equipment on switch-over to an alternative device, resulting in anomalous network operation of a very serious nature. In accordance with the alignment mechanism used with the main T OUT0 clock (described in the opening paragraphs of this section), whereby the 6.48 MHz output of the Master device is supplied to the Slave device, the alignment of both the 8 kHz and 2 kHz clocks is accomplished (they are already synchronous to the TOUT0 clocks) by feeding the 2 kHz clock of the Master device into the Slave device. The Multi-Frame Sync clock output of the Slave device is also fed to the Sync2K input of the Master device. Alignment of the Multi-Frame Sync input occurs only when cnfg_mode register, bit 3, address 34Hex External 2 kHz Sync Enable is set to 1.

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 43 www.semtech.com ACS8509 SETS JTAG The JTAG connections on the ACS8509 allow a full boundary scan to be made. The JTAG implementation is fully compliant to IEEE 1149.1, with the following minor exceptions, and the user should refer to the standard for further information. 1. The output boundary scan cells do not capture data from the core, and so do not support INTEST. However this does not affect board testing. 2. In common with some other manufacturers, pin TRST is internally pulled low to disable JTAG by default. The standard is to pull high. The polarity of TRST is as the standard: TRST high to enable JTAG boundary scan mode, TRST low for normal operation. 3. The device does not support the optional tri-state capability (HIGHZ). This will be supported on the next revision of the device. The JTAG timing diagram is shown in Figure 13. PORB The Power On Reset (PORB) pin resets the device if forced Low for a power on reset to be initiated. The reset is asynchronous, the minimum Low pulse width is 5 ns. Reset is needed to initialize all of the register values to their defaults. Asserting Reset is required at power on, and may be re-asserted at any time to restore defaults. This is implemented most simplistically by an external capacitor to GND along with the internal pull-up resistor. The ACS8509 is held in a reset state for 250 ms after the PORB pin has been pulled High. In normal operation PORB should be held High. Notes: (i) Both ACS8509 must build a common priority table so that the Slave ACS8509 can select the same input reference source as the Master ACS8509 if the Master fails (when the Master is OK, the Slave locks to the Master's output). (ii) Slave ACS8509 uses common priority tabl e, built before Master ACS8509 failed - priority table can be modified asstatus of the input reference sources changes. (iii) Slave ACS8509 outputs must remain in phase with those of Master ACS8509. Table 15 Master-Slave Relationship Ref_sources to Master ACS8509 Ref_sources to Slave ACS8509 Master ACS8509 Status Slave ACS8509 Status Master ACS8509 Slave ACS8509 Output Comments All good All good Good Good Locked (ref_x) Locked to Master Note (i) Some Failed Some others failed Good Good Locked (ref_y) Locked to Master Note (i) Good Good Good Failed Locked (ref_x) Dead Good Good Failed Good Dead Locked (ref_x) Note (ii) Good Good Failed Failed Dead Dead Failed Failed Failed Good Holdover Locked to Master Note (iii) Failed Failed Good Failed Holdover Dead Failed Failed Failed Good Dead Holdover Failed Failed Failed Failed Dead Dead

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 44 www.semtech.com ACS8509 SETS Figure 10 Automatic Mode Control State Diagram Free-run select ref (state 001) (1) Reset (3) no valid standby ref (main ref invalid or out of lock > 100s (2) all refs evaluated at least one ref valid Pre-locked wait for up to 100s (state 110) (4) valid standby ref [main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock > 100s] (5) selected ref phase locked Locked keep ref (state 100) Lost-phase wait for up to 100s (state 111) (10) selected source phase locked (6) no valid standby ref main ref invalid (7) phase lost on main ref (8) phase regained within 100s(9) valid standby ref [main ref invalid or (higher priority ref valid & in revertive mode)] Pre-locked2 wait for up to 100s (state 101) Holdover select ref (state 010) (12) valid standby ref (main ref invalid or out of lock >100s) (11) no valid standby ref (main ref invalid or out of lock >100s) (15) valid standby ref [main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock >100s] (13) no valid standby ref (main ref invalid or out of lock >100s) (14) all refs evaluated at least one ref valid Reference sources are flagged as valid when active, in-band and have no phase alarm set. All sources are continuously checked for activity and frequency Only the main source is checked for phase. A phase lock alarm is only raised on a reference when that reference has lost phase whilst being used as the main reference. The micro-processor can reset the phase lock alarm. A source is considered to have phase locked when it has been continuously in phase lock for between 1 and 2 seconds. F8530D_018AutoModeContStateDia_02

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 45 www.semtech.com ACS8509 SETS Maximum Ratings Important Note: The “Absolute Maximum Ratings”are stress ratings only, and functional operation of the device at conditions other than those indicated in the “Operating Conditions” sections of this specification are not implied. Exposure to the absolute maximum ratings for an extended period may reduce the reliability or useful lifetime of the product. Operating Conditions DC Characteristics Electrical Specification Table 16 Absolute Maximum Ratings Parameter Symbol Minimum Maximum Units Power Supply (dc voltage) VDD, VD+, VA1+, VA2+, VDD_DIFF VDD -0.5 3.6 V Input Voltage (non-supply pins) V IN -5 . 5 V Output Voltage (non-supply pins) V OUT -5 . 5 V Ambient Operating Temperature Range T A -40 +85 oC Storage Temperature T STOR -50 +150 oC Table 17 Operating Conditions Parameter Symbol Minimum Typical Maximum Units Power Supply (dc voltage) VDD, VD+, VA1+, VA2+, VDD_DIFF V DD 3.0 3.3 3.6 V Power Supply (dc voltage) VDD5 V DD5 3.0 3.3/5.0 5.5 V Ambient Temperature Range T A -40 - +85 oC Supply Current (Typical - one 19 MHz output) I DD - 130 222 mA Total Power Dissipation P TOT - 430 800 mW Table 18 DC Characteristics: TTL Input Port Across all operating conditions, unless otherwise stated Parameter Symbol Minimum Typical Maximum Units VIN High VIH 2.0 - - V VIN Low VIL -- 0 . 8 V Input Current I IN -- 1 0 µA

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 46 www.semtech.com ACS8509 SETS Notes: (i) Assuming a differential input voltage of at least 100 mV. (ii) With 50 Ω load on each pin to VDD -2 V, i.e. 82 Ω to GND and 130 Ω to VDD. Table 19 DC Characteristics: TTL Input Port with Internal Pull-up Across all operating conditions, unless otherwise stated Parameter Symbol Minimum Typical Maximum Units VIN High VIH 2- -V VIN Low VIL -- 0 . 8 V Pull-up Resistor PU 30 - 80 k Ω Input Current I IN - - 120 µΑ Table 20 DC Characteristics: TTL Input Port with Internal Pull-down Across all operating conditions, unless otherwise stated Parameter Symbol Minimum Typical Maximum Units VIN High VIH 2.0 - - V VIN Low VIL -- 0 . 8 V Pull-down Resistor PD 30 - 80 k Ω Input Current I IN - - 120 µA Table 21 DC Characteristics: TTL Output Port Across all operating conditions, unless otherwise stated Parameter Symbol Minimum Typical Maximum Units VOUT Low (lOL = 4 mA) V OL 0- 0 . 4 V VOUT High (lOH = 4 mA) V OH 2.4 - - V Drive Current I D -- 4 m A Table 22 DC Characteristics: PECL Output Port Across all operating conditions, unless otherwise stated Parameter Symbol Minimum Typical Maximum Units PECL Output Low Voltage (Note (ii)) V OLPECL VDD-2.10 - V DD-1.62 V PECL Output High Voltage (Note (ii)) V OHPECL VDD-1.25 - V DD-0.88 V PECL Output Differential Voltage (Note (i)) V ODPECL 580 - 900 mV

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 47 www.semtech.com ACS8509 SETS Figure 11 Recommended Line Termination for PECL Output Port Figure 12 Recommended Line Termination for LVDS Output Port Table 23 DC Characteristics: LVDS Output Port Across all operating conditions, unless otherwise stated Parameter Symbol Minimum Typical Maximum Units LVDS Output High Voltage (Note (i)) VOHLVDS -- 1 . 5 8 5 V LVDS Output Low Voltage (Note (i)) VOLLVDS 0.885 - - V LVDS Differential Output Voltage V ODLVDS 250 - 450 mV LVDS Change in Magnitude of Differential Output Voltage for complementary States (Note (i)) VDOSLVDS -- 2 5 m V LVDS Output Offset Voltage Temperature = 25 oC (Note (i)) VOSLVDS 1.125 - 1.275 V Note: (i) With 100 Ω load between the differential outputs. O1POS O1NEG F8509D_024PECL_02 Frequencies:

155.52 MHz

ZO = Transmission line Impedance VDD = +3.3 V ZO = 50Ω ZO = 50Ω VDD GND 130Ω 82Ω 130Ω 82Ω 01POS 01NEG F8509D_025LVDS_01 Frequencies: ZO = Transmission line Impedance ZO = 50Ω ZO = 50Ω 100Ω

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 48 www.semtech.com ACS8509 SETS Jitter Performance Table 24 DC Characteristics: Output Ji tter Generation (Test Definition G.813) Across all operating conditions unless otherwise stated Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Test Definition Filter used UI Spec UI Measurement on ACS8509 G813[11] for 155 MHz option 1 500 Hz to 1.3 MHz UI p-p = 0.5 0.058 (Note (ii)) G813[11] for 155 MHz option 1 65 kHz to 1.3 MHz UI p-p = 0.1 0.048 (Note (iii) 0.048 (Note (ii)) G813[11] for 155 MHz option 2 12 kHz to 1.3 MHz UI p-p = 0.1 0.053 (Note (iv)) 0.053 (Note (v)) 0.058 (Note (vi)) 0.053 (Note (vii)) 0.053 (Note (ii)) 0.058 (Note (iii)) 0.057 (Note (viii)) 0.055 (Note (ix)) 0.057 (Note (x)) 0.057 (Note (xi)) 0.057 (Note (xii)) 0.053 (Note (xiii)) G813[11] and G812[10] for 2.048 MHz option 1 20 Hz to 100 kHz UI p-p = 0.05 0.046 (Note (xiv)) Table 25 DC Characteristics: Output Ji tter Generation (Test Definition G812) Across all operating conditions unless otherwise stated Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Test Definition Filter used UI Spec UI Measurement on ACS8509 G812[10] for 1.544 MHz 10 Hz to 40 kHz UI p-p = 0.05 0.036 (Note (xiv)) G812[10] for 155.52 MHz electrical 500 Hz to 1.3 MHz UI p-p = 0.5 0.058 (Note (xv)) G812[10] for 2.048 MHz 65 Hz to 1.3 MHz UI p-p = 0.075 0.048 (Note (xv))

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 49 www.semtech.com ACS8509 SETS Table 26 DC Characteristics: Output Jitter Generation (Test Definition ETS-300-462-3) Across all operating conditions unless otherwise stated Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Test Definition Filter used UI Spec UI Measurement on ACS8509 ETS-300-462-3[3] for 2.048 MHz SEC 20 Hz to 100 kHz UI p-p = 0.5 0.046 (Note (xiv)) ETS-300-462-3[3] for 2.048 MHz SEC (Filter spec 49 Hz to 100 kHz) 20 Hz to 100 kHz UI p-p = 0.2 0.046 (Note (xiv)) ETS-300-462-3[3] for 2.048 MHz SSU 20 Hz to 100 kHz UI p-p = 0.05 0.046 (Note (xiv)) ETS-300-462-3[3] for 155.52 MHz 500 Hz to 1.3 MHz UI p-p = 0.5 0.058 (Note (xv)) ETS-300-462-3[3] for 155.52 MHz 65 kHz to 1.3 MHz UI p-p = 0.1 0.048 (Note (xv)) Table 27 DC Characteristics: Output Jitter Generation (Test Definition GR-253-CORE) Across all operating conditions unless otherwise stated Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Test Definition Filter used UI Spec UI Measurement on ACS8509 GR-253-CORE[17] net i/f, 51.84 MHz 100 Hz to 0.4 MHz UI p-p = 1.5 0.022 (Note (xv)) GR-253-CORE[17] net i/f, 51.84 MHz (Filter spec 20 kHz to 400 Hz) 18 kHz to 0.4 MHz UI p-p = 0.15 0.019 (Note (xv)) GR-253-CORE[17] net i/f, 155.52 MHz 500 Hz to 1.3 MHz UI p-p = 1.5 0.058 (Note (xv)) GR-253-CORE[17] net i/f, 155.52 MHz 65 kHz to 1.3 MHz UI p-p = 0.15 0.048 (Note (xv)) GR-253-CORE[17] cat II elect i/f, 155.52 MHz 12 kHz to 400 kHz UI p-p = 0.1 0.057 (Note (xv)) UIrms= 0.1 0.006 (Note (xv)) GR-253-CORE[17] cat II elect i/f, 51.84 MHz 12 kHz to 1.3 MHz UI p-p = 0.1 0.017 (Note (xv)) UIrms= 0.01 0.003 (Note (xv)) GR-253-CORE[17] DS1 i/f, 1.544 MHz 10_Hz to 40 kHz UI p-p = 0.1 0.036 (Note (xiv)) UIrms= 0.01 0.0055 (Note (xiv))

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 50 www.semtech.com ACS8509 SETS Table 28 DC Characteristics: Output Jitte r Generation (Test Definition AT&T 62411) Across all operating conditions unless otherwise stated Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Test Definition Filter used UI Spec UI Measurement on ACS8509 AT&T 62411[2] for 1.544 MHz (Filter spec 10 Hz to 8 kHz) 10 Hz to 40 kHz UI rms = 0.02 0.0055 (Note (xiv)) AT&T 62411[2] for 1.544 MHz 10 Hz to 40 kHz UI rms = 0.025 0.0055 (Note (xiv)) AT&T 62411[2] for 1.544 MHz 10 Hz to 40 kHz UI rms = 0.025 0.0055 (Note (xiv)) AT&T 62411[2] for 1.544 MHz Broadband UI rms = 0.05 0.0055 (Note (xiv)) Table 29 DC Characteristics: Output Ji tter Generation (Test Definition G.742) Across all operating conditions unless otherwise stated Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Test Definition Filter used UI Spec UI Measurement on ACS8509 G-742[8] for 2.048 MHz DC to 100 kHz UI p-p = 0.25 0.047 (Note (xiv)) G-742[8] for 2.048 MHz (Filter spec 18 kHz to 100 kHz) 20 Hz to 100 kHz UI p-p = 0.05 0.046 (Note (xiv)) G-742[8] for 2.048 MHz 20 Hz to 100 kHz UI p-p = 0.05 0.046 (Note (xiv)) Table 30 DC Characteristics: Output Jitter Generation (Test Definition GR-499-CORE) Across all operating conditions unless otherwise stated Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Test Definition Filter used UI Spec UI Measurement on ACS8509 GR-499-CORE[18] & G824[14] for 1.544 MHz 10 Hz to 40 kHz UI p-p = 5.0 0.036 (Note (xiv)) GR-499-CORE[18] & G824[14] for 1.544 MHz (Filter spec 8 kHz to 40 kHz) 10 Hz to 40 kHz UI p-p = 0.1 0.036 (Note (xiv)) GR-499-CORE[18] for 1.544 MHz >10 Hz UI p-p = 0.05 0.036 (Note (xiv))

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 51 www.semtech.com ACS8509 SETS Notes for Tables 24 to 30 Notes: (i) Filter used is that defined by test definition unless otherwise stated (ii) 5 Hz bandwidth, 19.44 MHz direct lock. (iii) 5 Hz bandwidth, 8 kHz lock. (iv) 20 Hz bandwidth, 19.44 MHz direct lock. (v) 20 Hz bandwidth, 8 kHz lock. (vi) 10 Hz bandwidth, 19.44 MHz direct lock. (vii) 10 Hz bandwidth, 8 kHz lock. (viii) 2.5 Hz bandwidth, 19.44 MHz direct lock. (ix) 2.5 Hz bandwidth, 8 kHz lock. (x) 1.2 Hz bandwidth, 19.44 MHz direct lock. (xi) 1.2 Hz bandwidth, 8 kHz lock. (xii) 0.6 Hz bandwidth, 19.44 MHz direct lock. (xiii) 0.6 Hz bandwidth, 8 kHz lock. (xiv) 5 Hz bandwidth, 8 kHz lock, 2.048 MHz input. (xv) 5 Hz bandwidth, 8 kHz lock, 19.44 MHz input. Figure 13 JTAG Timing Table 31 JTAG Timing (for use with Figure 13) Parameter Symbol Minimum Typical Maximum Units Cycle Time t CYC 50 - - ns TMS/TDI to TCK rising edge time t SUR 3- - n s TCK rising to TMS/TDI hold time t HT 23 - - ns TCK falling to TDO valid t DOD -- 5 n s F8110D_022JTAGTiming_01 TCK TMS TDI tSUR tHT TDO tDOD tCYC

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 52 www.semtech.com ACS8509 SETS Input/Output Timing Figure 14 Input/Output Timing with Phase Build-out Off

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 53 www.semtech.com ACS8509 SETS Motorola Mode In MOTOROLA mode, the device is configured to interface with a microprocessor using a 680x0 type bus as parallel data + address. Figure 15 and Figure 16 show the timing diagrams of read and write accesses for this mode. Figure 15 Read Access Timing in MOTOROLA Mode Note: (i) Timing with RDY. If RDY not used, t pw1 becomes 178 ns. Table 32 Read Access Timing in MOTOROLA Mode (for use with Figure 15) Symbol Parameter MIN TYP MAX tsu1 Setup A valid to CSBfalling edge 0 ns - - tsu2 Setup WRB valid to CSBfalling edge 0 ns - - td1 Delay CSBfalling edge to AD valid - - 177 ns td2 Delay CSBfalling edge to DTACKrising edge - - 13 ns td3 Delay CSBrising edge to AD high-Z - - 0 ns td4 Delay CSBrising edge to RDY high-Z - - 7 ns tpw1 CSB Low time 485 ns (i) -- tpw2 RDY High time 310 ns - 472 ns th1 Hold A valid after CSBrising edge 0 ns - - th2 Hold WRB valid after CSBrising edge 0 ns - - th3 Hold CSB Low after RDYfalling edge 0 ns - - tp Time between consecutive accesses (CSBrising edge to CSBfalling edge)3 2 0 n s - - F8110D_007ReadAccMotor_01 CSB WRB A AD RDY (DTACK) X X address Z Z X X Z tpw1 tsu2 tsu1 td1 td2 th1 th2 tpw2 th3 td4 td3 data Z

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 54 www.semtech.com ACS8509 SETS Figure 16 Write Access Timing in MOTOROLA Mode Note: (i) Timing with RDY. If RDY not used, t pw1 becomes 178 ns. Table 33 Write Access Timing in MOTOROLA Mode (for use with Figure 16) Symbol Parameter MIN TYP MAX tsu1 Setup A valid to CSBfalling edge 0 ns - - tsu2 Setup WRB valid to CSBfalling edge 0 ns - - tsu3 Setup AD valid before CSBrising edge 3 ns - - td2 Delay CSBfalling edge to RDYrising edge - - 13 ns td4 Delay CSBrising edge to RDY High-Z - - 7 ns tpw1 CSB Low time 485 ns (i) -- tpw2 RDY High time 310 ns - 472 ns th1 Hold A valid after CSBrising edge 3 ns - - th2 Hold WRB Low after CSBrising edge 0 ns - - th3 Hold CSB Low after RDYfalling edge 0 ns - - th4 Hold AD valid after CSBrising edge 4 ns - - tp Time between consecutive accesses (CSBrising edge to CSBfalling edge) 320 ns - - F8110D_008WriteAccMotor_01 CSB WRB A AD RDY (DTACK) X X address Z X X Z tpw1 tsu2 tsu1 tsu3 td2 th1 th2 tpw2 th3 td4 th4 X data X

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 55 www.semtech.com ACS8509 SETS Intel Mode In Intel mode, the device is configured to interface with a microprocessor using a 80x86 type bus as parallel data + address. Figure 17 and Figure 18 show the timing diagrams of read and write accesses for this mode. Figure 17 Read Access Timing in INTEL Mode Note: (i) Timing with RDY. If RDY not used, t pw1 becomes 180 ns. Table 34 Read Access Timing in INTEL Mode (for use with Figure 17) Symbol Parameter MIN TYP MAX tsu1 Setup A valid to CSBfalling edge 0 ns - - tsu2 Setup CSBfalling edge to RDBfalling edge 0 ns - - td1 Delay RDBfalling edge to AD valid - - 177 ns td2 Delay CSBfalling edge to RDY active - - 13 ns td3 Delay RDBfalling edge to RDYfalling edge -- 1 4 n s td4 Delay RDBrising edge to AD high-Z - - 10 ns td5 Delay CSBrising edge to RDY high-Z - - 9 ns tpw1 RDB Low time 486 ns (i) -- tpw2 RDY Low time 310 ns - 472 ns th1 Hold A valid after RDBrising edge 0 ns - - th2 Hold CSB Low after RDBrising edge 0 ns - - th3 Hold RDB Low after RDYrising edge 0 ns - - tp Time between consecutive accesses (RDBrising edge to RDBfalling edge, or RDBrising edge to WRBfalling edge) 320 ns - - F8110D_009ReadAccIntel_01 CSB address Z Z data WRB RDB tpw1 th2 th1 tsu2 A tsu1 td3 tpw2 th3 AD td1 td4 RDY td2 td5

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 56 www.semtech.com ACS8509 SETS Figure 18 Write Access Timing in INTEL Mode Notes: (i) Timing with RDY. If RDY not used, t pw1 becomes 180 ns. (ii) Timing if t h2 is greater than 170 ns, otherwise 5 ns after CSB rising edge. Table 35 Write Access Timing in INTEL Mode (for use with Figure 18) Symbol Parameter MIN TYP MAX tsu1 Setup A valid to CSBfalling edge 0 ns - - tsu2 Setup CSBfalling edge to WRBfalling edge 0 ns - - tsu3 Setup AD valid before WRBrising edge 3 ns - - td2 Delay CSBfalling edge to RDY active - - 13 ns td3 Delay WRBfalling edge to RDYfalling edge - - 14 ns td5 Delay CSBrising edge to RDY high-Z - - 9 ns tpw1 WRB Low time 486 ns (i) -- tpw2 RDY Low time 310 ns - 472 ns th1 Hold A valid after WRBrising edge 170 ns(ii) -- th2 Hold CSB Low after WRBrising edge 0 ns - - th3 Hold WRB Low after RDYrising edge 0 ns - - th4 Hold AD valid after WRBrising edge 4 ns - - tp Time between consecutive accesses (WRBrising edge to WRBfalling edge, or WRBrising edge to RDBfalling edge) 320 ns - - F8110D_010WriteAccIntel_01 CSB address ZZ data WRB RDB tpw1 th2 th1 tsu2 A tsu1 td3 tpw2 th3 AD tsu3 th4 RDY td2 td5

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 57 www.semtech.com ACS8509 SETS Multiplexed Mode In MULTIPLEXED mode, the device is configured to interface with a microprocessor using a multiplexed address/data bus. Figures 19 and 20 show the timing diagrams of read and write accesses. Figure 19 Read Access Timing in MULTIPLEXED Mode Note: (i) Timing with RDY. If RDY not used, t pw1 becomes 180 ns. Table 36 Read Access Timing in MULTIPLEXED Mode (for use with Figure 19) Symbol Parameter MIN TYP MAX tsu1 Setup AD address valid to ALEfalling edge 2 ns - - tsu2 Setup CSBfalling edge to RDBfalling edge 0 ns - - td1 Delay RDBfalling edge to AD data valid - - 177 ns td2 Delay CSBfalling edge to RDY active - - 13 ns td3 Delay RDBfalling edge to RDYfalling edge - - 15 ns td4 Delay RDBrising edge to AD data high-Z - - 9 ns td5 Delay CSBrising edge to RDY high-Z - - 10 ns tpw1 RDB Low time 487 ns (i) -- tpw2 RDY Low time 310 ns - 472 ns tpw3 ALE High time 2 ns - - th1 Hold AD address valid after ALEfalling edge 3 ns - - th2 Hold CSB Low after RDBrising edge 0 ns - - th3 Hold RDB Low after RDYrising edge 0 ns - - tp1 Time between ALEfalling edge and RDBfalling edge 0 ns - - tp2 Time between consecutive accesses (RDBrising edge to ALErising edge)3 2 0 n s - - F8110D_011ReadAccMultiplex_01 CSB ALE ZZ dataaddress X X WRB RDB tpw1 th2 tpw3 tsu1 th1 tsu2 tp1 td3 td1 td4 tpw2 th3 AD RDY td2 td5

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 58 www.semtech.com ACS8509 SETS Figure 20 Write Access Timing in MULTIPLEXED Mode Note: (i) Timing with RDY. If RDY not used, t pw1 becomes 180 ns. Table 37 Write Access Timing in MULTIPLEXED Mode (For use with Figure 20) Symbol Parameter MIN TYP MAX tsu1 Set up AD address valid to ALEfalling edge 2 ns - - tsu2 Set up CSBfalling edge to WRBfalling edge 0 ns - - tsu3 Set up AD data valid to WRBrising edge 3 ns - - td2 Delay CSBfalling edge to RDY active - - 13 ns td3 Delay WRBfalling edge to RDYfalling edge - - 15 ns td5 Delay CSBrising edge to RDY high-Z - - 9 ns tpw1 WRB Low time 487 ns(i) -- tpw2 RDY Low time 310 ns - 472 ns tpw3 ALE High time 2 ns - - th1 Hold AD address valid after ALEfalling edge 3 ns - - th2 Hold CSB Low after WRBrising edge 0 ns - - th3 Hold WRB Low after RDYrising edge 0 ns - - th4 AD data hold valid after WRBrising edge 4 ns - - tp1 Time between ALEfalling edge and WRBfalling edge 0 ns - - tp2 Time between consecutive accesses (WRBrising edge to ALErising edge)3 2 0 n s - - F8110D_012WriteAccMultiplex_01 CSB ALE ZZ dataaddress X X WRB RDB tpw1 th2 tpw3 tsu1 th1 tsu2 tp1 td3 tsu3 th4 tpw2 th3 AD RDY td2 td5

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 59 www.semtech.com ACS8509 SETS Serial Mode In Serial mode, the device is configured to interface with a serial microprocessor bus. The combined minimum High and Low times for SCLK define the maximum clock rate. For Write access this is 2.77 MHz (360 ns). For Read access the maximum SCLK rate is slightly slower and is affected by the setting of CLKE, being either 2.0 MHz (500 ns) or 1 MHz (1 us). This mismatch in rates is caused by the sampling technique used to detect the end of the address field in Read mode. It takes up to 3 cycles of an internal 6.40 MHz clock to start the Read process following receipt of the final address bit. This is 468 ns. The Read data is then decoded and clocked out onto SDO directly using SCLK. With CLKE=1, the falling edge of SCLK is used to clock out the SDO. With CLKE=0, the rising edge of SCLK is used to clock out the SDO. A minimum period of 500 ns (468 capture plus 32 decode) is required between the final address bit and clocking it out onto SDO. This means that to guarantee the correct operation of the Serial interface, with CLKE=0, SCLK has a maximum clock rate of 2 MHz. With CLKE=1, SCLK has a maximum clock rate of 1 MHz. SCLK is not required to run between accesses (i.e., when CSB = 1). The following Figures show the timing diagrams for Write and Read access for this mode. Figure 21 Read Access Timing in SERIAL Mode F8530D_013ReadAccSerial_01 ALE=SCLK CSB CLKE = 0; SDO data is clocked out on the rising edge of SCLK CLKE = 1; SDO data is clocked out on the falling edge of SCLK R/W Output not driven, pulled low by internal resistor A(0) = SDI AD(0)=SDO tsu2 tsu1 th1 tpw1 tpw2 A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 th2 td2td1 ALE=SCLK CSB R/W Output not driven, pulled low by internal resistor A(0)=SDI AD(0)=SDO A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 th2 td2td1

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 60 www.semtech.com ACS8509 SETS Figure 22 Write Access Timing in SERIAL Mode Table 38 Read Access Timing in SERIAL Mode (For use with Figure 21) Symbol Parameter MIN TYP MAX tsu1 Setup SDI valid to SCLKrising edge 0 ns - - tsu2 Setup CSBfalling edge to SCLKrising edge 160 ns - - td1 Delay SCLKrising edge (SCLKfalling edge for CLKE = 1) to SDO valid - - 17 ns td2 Delay CSBrising edge to SDO high-Z - - 10 ns tpw1 SCLK Low time CLKE = 0 CLKE = 1 250 ns 500 ns t pw2 SCLK High time CLKE = 0 CLKE = 1 250 ns 500 ns t h1 Hold SDI valid after SCLKrising edge 170 ns - - th2 Hold CSB Low after SCLKrising edge, for CLKE = 0 Hold CSB Low after SCLKfalling edge, for CLKE = 1 5 ns - - tp Time between consecutive accesses (CSBrising edge to CSBfalling edge)1 6 0 n s - - Table 39 Write Access Timing in SERIAL Mode (For use with Figure 22) Symbol Parameter MIN TYP MAX tsu1 Setup SDI valid to SCLKrising edge 0 ns - - tsu2 Setup CSBfalling edge to SCLKrising edge 160 ns - - tpw1 SCLK Low time 180 ns - - tpw2 SCLK High time 180 ns - - th1 Hold SDI valid after SCLKrising edge 170 ns - - th2 Hold CSB Low after SCLKrising edge 5 ns - - tp Time between consecutive accesses (CSBrising edge to CSBfalling edge)1 6 0 n s - - ALE=SCLK CSB R/W Output not driven, pulled low by internal resistor A(0)=SDI AD(0)=SDO tsu2 tsu1 th1 tpw1 tpw2 A0 A1 A2 A3 A4 A5 A6 th2 D0 D1 D2 D3 D4 D5 D6 D7 F8110D 014W it A S i l 02

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 61 www.semtech.com ACS8509 SETS EPROM Mode This mode is suitable for use with an EPROM, in which configuration data is stored (one-way communication - status information will not be accessible). A state machine internal to the ACS8509 device will perform numerous EPROM read operations to read the data out of the EPROM. In EPROM Mode, the ACS8509 takes control of the bus as Master and reads the device set-up from an AMD AM27C64 type EPROM at lowest speed (250ns) after device set-up (system reset). The EPROM access state machine in the up interface sequences the accesses. Figure 23 shows the access timing of the device in EPROM mode. Further information can be found in the AMD AM27C64 datasheet. Figure 23 Access Timing in EPROM mode Table 40 Access Timing in EPROM mode (For use with Figure 23) Symbol Parameter MIN TYP MAX tacc Delay CSBfalling edge or A change to AD valid - - 920 ns F8110D_015ReadAccEEPROM_01 CSB (=OEB) A AD address ZZ tacc data

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 62 www.semtech.com ACS8509 SETS Figure 24 LQFP Package

Package Information

Table 41 100 Pin LQFP Package Dimension Data (for use with Figure 24)

100 LQFP

A A1 A2 e AN1 AN2 AN3 AN4 R1 R2 L L1 S b b1 c c1 (ref) - 0.22 0.20 - - E D A A2 A1 b e b c c1 L AN4 AN3 AN2 S AN1 Section A-A Section B-B AA Seating plane 7 8 Notes B B The top package body may be smaller than the bottom package body by as much as 0.15 mm. To be determined at seating plane. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. Details of pin 1 identifier are optional but will be located within the zone indicated. Exact shape of corners can vary. A1 is defined as the distance from the seating plane to the lowest point of the package body. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. Shows plating. 1 2 3

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 63 www.semtech.com ACS8509 SETS Thermal Conditions The device is rated for full temperature range when this package is used with a 4 layer or more PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum operating temperature must be reduced when the device is used with a PCB with less than these requirements. Figure 25 Typical 100 Pin LQFP Footprint Notes: (i) (1) Solderable to this limit. (ii) Square package - dimensions apply in both X and Y directions. (iii) Typical example. The user is re sponsible for ensuring compatibility with PCB manufacturing process, etc. Pitch = 0.5 mm 18.3 mm 17.0 mm (1) 14.6 mm Width = 0.3 mm 1.85 mm F8509D_004QFNFootprint100_01

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 64 www.semtech.com ACS8509 SETS Figure 26 Simplified Application Schematic

Application Information

10uF_TANT 100nF C14 100nF C15 100nF C32 100nF 100uF VIN GND VOUT EZ1086CT-3.3 IC2 term_connect BZV90C-5.6v ZD1 1nF SEC1 SEC2 SEC4SEC3 C21 100nF output vdd2 gnd13 optn4 gnd2 txco Vectron 12.8MHz 100nF AGND1 TRST2 IC3 NC4 AGND5 VA1+6 TMS7 INTREQ8 TCK9 REFCLK10 DGND11 VD+12 VD+13 DGND14 DGND15 VD+16 NC17 IC18 VA2+19 AGND20 TDO21 IC22 TDI23 DGND24 DGND25 NC26 IC27 IC28 DGND29 FrSync30 MFrSync31 GND_DIFF32 VDD_DIFF33 IC34 IC35 O1POS36 O1NEG37 GND_DIFF38 VDD_DIFF39 IC40 IC41 IC42 IC43 VDD544 SYNC2K45 IC46 IC47 SEC148 DGND49 VDD50 SEC2 51 IC 52 IC 53 SEC3 54 IC 55 SEC4 56 IC 57 UPSEL2 58 UPSEL1 59 UPSEL0 60 VDD 61 DGND 62 A6 63 A5 64 A4 65 A3 66 A2 67 A1 68 A0 69 CSB 70 WRB 71 RDB 72 ALE 73 PORB 74 RDY 75 AD7 76 AD6 77 AD5 78 AD4 79 AD3 80 AD2 81 AD1 82 AD0 83 DGND84 VDD 85 VDD 86 DGND87 O2 88 IC 89 O3 90 VDD 91 DGND92 IC 93 IC 94 O4 95 IC 96 IC 97 IC 98 MSTSLVB99 SONSDHB100 IC1 ACS8509 AGND DGND AGND AGND DGND VDDVDD3 VDDA DGND3 DGND VDD VDD VDDA VDD DGND3 DGND2 VDDA VDD3 VDD2 DGND DGND DGND2 FrSync MFrSync O1 SYNC2K DGND VDD F8509D_031EvalBdSchem_01 VDD2 DGND2DGND2 VDD5v DGND VDD2 DGND VDD DGND UPSEL1 UPSEL0 UPSEL2 Int RDY ALE RDB WRB CSB (+) (+) Power supply and ground connections to 'star' connect back to these decoupling capacitors at the regulator and only connect together at this point Optional Processor interface type selection Optional Processor/EPROM interface type selection Optional EPROM interface selection Decoupling capacitor, C21 should be placed close to the xtal pins that are being decoupled CC parts are easily cut links that can also take SM capacitors or Ohm resistor links. All tcxo options to be placed as close as possible to IC1, with short output track. All decoupling capacitors, C29, C9, C13, C14, C15, C6, C5, C12, C11, C10,C32 should be placed close to the IC1 pins that are being decoupled

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 65 www.semtech.com ACS8509 SETS APLL Analogue Phase Locked Loop BITS Building Integrated Timing Supply DFS Digital Frequency Synthesis DPLL Digital Phase Locked Loop DS1 1544 kb/s interface rate DTO Discrete Time Oscillator E1 2048 kb/s interface rate I/O Input - Output LOF Loss of Frame Alignment LOS Loss Of Signal LQFP Low profile Quad Flat Pack LVDS Low Voltage Differential Signal MTIE Maximum Time Interval Error NE Network Element OCXO Oven Controlled Crystal Oscillator PBO Phase Build-out PDH Plesiochronous Digital Hierarchy PECL Positive Emitter Coupled Logic PFD Phase and Frequency Detector PLL Phase Locked Loop POR Power-On Reset ppb parts per billion ppm parts per million p-p peak-to-peak R/W Read/Write rms root-mean-square RO Read Only RoHS Restrictive Use of Certain Hazardous Substances (directive) SDH Synchronous Digital Hierarchy SEC SDH/SONET Equipment Clock SETS Synchronous Equipment Timing source SONET Synchronous Optical Network SSF Synchronization Signal Failure SSU Synchronization Supply Unit STM Synchronous Transport Module TDEV Time Deviation TCXO Temperature Compensated Crystal Oscillator UI Unit Interval WEEE Waste Electrical and Electronic Equipment (directive) [1] ANSI T1.101-1999 (1999) Synchronization Interface Standard [2] AT & T 62411 (12/1990) ACCUNET ® T1.5 Service description and Interface Specification [3] ETSI ETS 300 462-3, (01/1997) Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 3: The control of jitter and wander within synchronization networks [4] ETSI ETS 300 462-5 (09/1996) Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 5: Timing characteristics of slave clocks suitable for operation in Synchronous Digital Hierarchy (SDH) equipment [5] IEEE 1149.1 (1990) Standard Test Access Port and Boundary-Scan Architecture Physical/electrical characteristics of hierarchical digital interfaces Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s Second order digital multiplex equipment operating at 8448 kbit/s, and using positive justification Characteristics of synchronous digital hierarchy (SDH) equipment functional blocks Timing requirements of slave clocks suitable for use as node clocks in synchronization networks Timing characteristics of SDH equipment slave clocks (SEC) Controlled slip rate objectives on an international digital connection The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy Abbreviations References

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 66 www.semtech.com ACS8509 SETS The control of jitter and wander within digital networks which are based on the 1544 kbit/s hierarchy The control of jitter and wander within digital networks which are based on the Synchronous Digital Hierarchy (SDH) Resistibility of internal interfaces of telecommunication centres to surge overvoltages [17] Telcordia GR-253-CORE, Issue 3 (09/ 2000) Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria [18] Telcordia GR-499-CORE, Issue 2 (12/1998) Transport Systems Generic Requirements (TSGR) Common requirements [19] Telcordia GR-1244-CORE, Issue 2 (12/2000) Clocks for the Synchronized Network: Common Generic Criteria Semtech and the Semtech S logo are registered trademarks of Semtech Corporation. ACCUNET ® is a registered trademark of AT & T. AMD is a registered trademark of Advanced Micro Devices, Inc. Vectron is a registered trademark of Vectron International. ICT Flexacom is a registered trademark of ICT Electronics. Intel is a registered trademark of the Intel Corporation. Motorola is a registered trademark of Motorola, Inc. Telcordia is a registered trademark of Telcordia Technologies. Trademark Acknowledgements

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 67 www.semtech.com ACS8509 SETS The Revision Status of the datasheet, as shown in the center of the datasheet header bar, may be DRAFT, PRELIMINARY, or FINAL, and refers to the status of the Device (not the datasheet) within the design cycle. DRAFT status is used when the design is being realized but is not yet physically available, and the datasheet content reflects the intention of the design. The datasheet is raised to PRELIMINARY status when initial prototype devices are physically available, and the datasheet content more accurately represents the realization of the design. The datasheet is only raised to FINAL status after the device has been fully characterized, and the datasheet content updated with measured, rather than simulated parameter values. This is a FINAL release (Revision 2.00) of the ACS8509 datasheet. Changes made for this document revision are given in Table 42, together with a brief summary of previous revisions. For specific changes between earlier revisions, refer (where available) to those earlier revisions. Always use the current version of the datasheet. Revision Status/History Table 42 Revision History Revision Reference Description of Changes 1.00 September 2004 All pages New draft.

2.00 January 2006 All pages Updated to FINAL and up dated to reflect availability of lead(Pb)-free

packaged part.

ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 68 www.semtech.com ACS8509 SETS Disclaimers Life support- This product is not designed or intended for use in life support equipment, devices or systems, or other critical applications. This product is not authorized or warranted by Semtech for such use. Right to change- Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised to obtain the latest version of the relevant information before placing orders. Compliance to relevant standards- Operation of this device is subject to the User’s implementation and design practices. It is the responsibility of the User to ensure equipment using this device is compliant to any relevant standards. Contacts For Additional Information, contact the following: Semtech Corporation Advanced Communications Products E-mail: sales@semtech.com acsupport@semtech.com Internet: http://www.semtech.com USA: 200 Flynn Road, Camarillo, CA 93012-8790 Tel: +1 805 498 2111, Fax: +1 805 498 3804 FAR EAST: 11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, R.O.C. Tel: +886 2 2748 3380 Fax: +886 2 2748 3390 EUROPE: Semtech Ltd., Units 2 and 3, Park Court, Premier Way, Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN Tel: +44 (0)1794 527 600 Fax: +44 (0)1794 527 601

Ordering Information

ACS8509 SETS Synchronous Equipment Timing Source for SONET or SDH Network Elements. ACS8509T Lead (Pb) -free packaged vers ion of ACS8509; RoHS and WEEE compliant. ISO9001 CERTIFIED