ACS70310

ACS70310 ALLEGRO | Alldatasheet

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The Allegro ACS70310 IC incorporates a Hall element with BiCMOS integrated circuitry to provide a fully monolithic linear current sensor IC. The IC is sensitive to magnetic flux density orthogonal to the IC package surface and the output is an analog voltage proportional to the applied flux density. The ACS70310 is designed to be used in conjunction with a ferromagnetic core to provide highly accurate current sensing. The gain and offset drift over temperature is factory programmed at Allegro and delivers a solution with 1% sensitivity and 5 mV offset error from 25°C to 150°C. The ACS70310 is customer programmable. The absolute value of gain and offset can be programmed after manufacturing to provide customers industry-leading current sensor accuracy. The sensor has a high operating bandwidth from DC to 240 kHz and a fast 2 µs response time. It is ideal for use in high frequency automotive inverters and DC/DC converters where fast switching is required. Broken ground wire detection, clamps, power-on reset, and overvoltage detection provide the required diagnostics for safety-critical automotive applications. The on-board supply regulator enables the supply pin to survive voltages of ±18 V and the output pin to survive voltages of +16 to –6 V for added robustness in the harsh automotive ACS70310-DS, Rev. 1 MCO-0000617

• Factory-programmed segmented linear temperature compensation (TC) provides ultralow thermal drift □ Sensitivity ±1% □ Offset ±5 mV
• On-board supply regulator with reverse-battery protection provides high immunity to Electrical Overstress (EOS)
• Very fast response time (2 µs)
• High operating bandwidth: DC to 240 kHz
• AEC-Q100 Grade 0, automotive qualified
• Customer-programmable, high-resolution offset, and sensitivity trim Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing Figure 1: Functional Block Diagram ACS70310 FEATURES AND BENEFITS DESCRIPTION Regulator Programming Control Charge Pump Pulse Generator Broken Ground Detection Output Clamps Offset Control Signal Recovery Sensitivity Control EEPROM and Control Logic Temperature Sensor Active Temp. Compensation Dynamic Offset Cancellation GND CBYPASS VCC (Programming) To all subcircuits Push/Pull Output Driver VOUT (Programming) CL Undervoltage Detection April 10, 2019 PACKAGE: 4-pin SIP (suffix KT) Not to scale TN Leadform TF Leadform TG Leadform Continued on next page... Continued on next page...

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A. www.allegromicro.com SELECTION GUIDE Part Number [1] Factory-Programmed Sensitivity (mV/G) Programmable Sens Range (mV/G) TA (°C) Package [2] Packing [3] ACS70310LKTATN-001B5-C 1 0.5 to 1.2 –40 to 150 4-pin SIP, TN leadform 4000 pieces per 13-inch reel ACS70310LKTATN-2P5B5-C 2.5 1.2 to 2.5 ACS70310LKTATN-005B5-C 5 2.5 to 5.5 ACS70310LKTATN-010B5-C 10 5.5 to 11.5 [1] Characteristics are guaranteed within the sense programmable range of the corresponding part number. [2] TN, TG and TF package leadform options available. [3] Contact Allegro for additional packing options. Programmability F = Factory only C = Customer programmable Forward Supply Voltage Level 5 = 5 V Directionality B = Bidirectional U = Unidirectional Factory-Trimmed Sensitivity 001 = 1 mv/G Package Leadform Option TN TF TG Package Designator KTA = 4-pin mini SIP Temperature Range L = –40°C to 150°C Allegro Part Number ACS70310LKATN-001B5-C environment. Device parameters are specified across an extended ambient automotive temperature range: –40°C to 150°C. The ACS70310 sensor IC is provided in an extremely thin case (1 mm thick), 4-pin SIP (single in-line package, suffix KT) that is lead (Pb) free, with 100% matte-tin leadframe plating.

• Extremely low noise and high resolution achieved via proprietary Hall element and low-noise amplifier circuits
• Patented circuits suppress IC output spiking during fast current step inputs
• Wide selectable sensitivity range between 0.5 and 11.5 mV/G
• User-selectable ratiometric behavior of sensitivity, quiescent voltage, and clamps (ratiometry can be disabled), for simple interface with application A-to-D converter (ADC)
• Precise recoverability after temperature cycling
• Open circuit detection on ground pin (broken wire)
• Customer programmable Output V oltage Clamps provide short- circuit diagnostic capabilities
• Wide ambient temperature range: –40°C to 150°C
• Immune to mechanical stress
• Extremely thin package: 1 mm case thickness FEATURES AND BENEFITS (continued) DESCRIPTION (continued)

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Notes Rating Unit Forward Supply Voltage VCC 18 V Reverse Supply Voltage VRCC TJ(max) should not be exceeded –18 V Forward Output Voltage VOUT VOUT < VCC + 2 V 16 V Reverse Output Voltage VROUT Difference between VCC and output should not exceed 20 V –6 V Output Current IOUT Maximum survivable sink or source current on the output 10 mA Operating Ambient Temperature TA L temperature range –40 to 150 °C Storage Temperature Tstg –65 to 165 °C Maximum Junction Temperature TJ(max) 165 °C THERMAL CHARACTERISTICS Characteristic Symbol Test Conditions [2] Value Unit Package Thermal Resistance RθJA On 1-layer PCB with exposed copper limited to solder pads 174 °C/W [2] Additional thermal information available on the Allegro website Allowable PowerD issipation versusA mbient Temperature 20 40 60 80 100 120 140 160 180 Temperature, TA (°C) Allowable Power Dissipation, P D (mW) 300 400 200 100 600 500 800 700 900 (R = 174 ºC/W θJA LOAD BYPASS GND VOUT ACS70310 VCC VCC C C (Recommended) LOADR Figure 2: Typical Application Drawing

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com PINOUT DIAGRAM AND TERMINAL LIST TABLE Figure 3: KT Package Pinout Diagram (Ejector pin mark on opposite side) 2 3 4 1 Terminal List Table Number Name Function

1 VCC Input Power Supply; also used for programming

2 VOUT Output Signal, also used for programming

3 NC/GND Connect to GND for optimal ESD performance

4 GND Ground

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Characteristic Symbol Test Conditions Min. Typ. Max. Unit

ELECTRICAL CHARACTERISTICS

Supply Voltage VCC 4.5 5 5.5 V Supply Current ICC No load on VOUT; VCC @ 4.5, 5, and 5.5 V – 13 15 mA Power-On Reset Voltage VPOR(H) TA = 25°C, VCC rising 3.7 3.9 4.3 V VPOR(L) TA = 25°C, VCC falling 3.2 3.4 3.75 V Power-On Reset Hysteresis VPOR(HYS) TA = 25°C 440 500 560 mV Power-On Reset Release Time tPOR(R) TA = 25°C, VCC rising – 32 – µs Power-On Delay Time tPO TA = 25°C, CBYPASS = open, CL = 1 nF – 80 – µs Temperature Compensation Power-On Time tTC TA = 150°C, CBYPASS = open, CL = 1 nF, Sens = 1 and 10 mV/G – 146 – µs Supply Zener Clamp Voltage Vz TA = 25°C, ICC = 30 mA 18 20 – V OUTPUT CHARACTERISTICS DC Output Resistance ROUT TA = 25°C 2 4 8 Ω Output Load Resistance [1] RL VOUT to GND or VCC 4.7 10 – kΩ Output Load Capacitance CL VOUT to GND – – 5 nF Output Voltage Saturation VOUT(SATH) TA = 25°C, RL = 10 kΩ to GND, Bias = 400 G 4.75 4.8 – V VOUT(SATL) TA = 25°C, RL = 10 kΩ to VCC, Bias = 400 G – 0.2 0.25 V Output Voltage Clamp VCLP(HIGH) TA = 25°C, RL = 10 kΩ to GND, Bias = 400 G 4.65 4.7 4.75 V VCLP(LOW) TA = 25°C, RL = 10 kΩ to VCC, Bias = 400 G 0.25 0.3 0.36 V Output Voltage with Broken GND VBRK_DN TA = 25°C, RL = 10 kΩ to GND, Pin 3 = NC 0 100 200 mV VBRK_UP TA = 25°C, RL = 10 kΩ to VCC (5 V), Pin 3 = NC 4.8 4.9 5 V Overvoltage Detection [2] VOVD(EN) TA = 25°C – 6.5 – V VOVD(DIS) TA = 25°C – 6 – V Noise VIN TA = 25°C, CL = 1 nF, Sens = 5 mV/G – 1.4 – mG/√(Hz) VON TA = 25°C, Sens = 5 mV/G – 3.5 – mVRMS Propagation Delay Time tpd TA = 25°C, 0.5 Fullscale = 1 V/(t < 750 ns), CL = 0 nF, no RL – 1.2 1.65 µs Response Time tRESPONSE TA = 25°C, 0.5 Fullscale = 1 V/(t < 750 ns), CL = 0 nF, no RL – 2.1 3 µs Rise Time tr TA = 25°C, 0.5 Fullscale = 1 V/(t < 750 ns), CL = 0 nF, no RL – 1.9 – µs Output Slew Rate SR TA = 25°C, 0.5 Fullscale = 1 V/(t < 750 ns), CL = 0 nF, no RL 410 480 550 V/ms Internal Bandwidth BWi Small signal –3 dB, CL = 1 nF, TA = 25°C; Sens = 10 mV/G – 240 – kHz Continued on the next page… OPERATING CHARACTERISTICS: Valid over full operating temperature range of TA, CBYPASS = 0.1 µF, and VCC = 5 V, unless otherwise specified

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Characteristic Symbol Test Conditions Min. Typ. Max. Unit QUIESCENT OUTPUT VOLTAGE (V OUT(Q)) Number of Fine QVO Programming Bits QVO_FINE – 9 – bit Quiescent Output Voltage [3] VOUT(QU) Unidirectional, TA = 25°C 0.495 0.5 0.505 V VOUT(QBI) Bidirectional, TA = 25°C 2.495 2.5 2.505 V Average Quiescent Voltage Output Programming Step Size [4] VOUT(Q)Step TA = 25°C – 1.18 – mV Average Quiescent Voltage Output Temperature Compensation Step Size VOUT(Q)TCStep – VOUT(Q)Step – mV SENSITIVITY (Sens) Coarse Sensitivity Programming Bits [5] SENS_COARSE Readable by customer – 2 – bit Fine Sensitivity Programming Bits SENS_FINE – 9 – bit Sensitivity Programming Range [6] SensPR SENS_COARSE = 0 0.5 – 1.2 mV/G SENS_COARSE = 1 1.2 – 2.5 mV/G SENS_COARSE = 2 2.5 – 5.5 mV/G SENS_COARSE = 3 5.5 – 11.5 mV/G Average Sensitivity Programming Step Size StepSENS SENS_COARSE = 0 – 2.87 – µV/G SENS_COARSE = 1 – 6.06 – µV/G SENS_COARSE = 2 – 13.06 – µV/G SENS_COARSE = 3 – 27.1 – µV/G Average Sensitivity Temperature Compensation Step Size StepSENSTC TA = –40°C to 150°C – StepSENS – μV/G SENSITIVITY ERROR Factory Sensitivity Error SensERR TA = 25°C –1 – 1 % Sensitivity Drift Over Temperature ΔSensTC TA = 25°C to 150°C –1 – 1 % Sensitvity Non-Linearity Error [7] LinERR Measured at 400 G (1, 2.5, and 5 mV/G) or Sensitivity Ratiometry Error RatERRSENS VCC = 4.85 to 5.15 V –0.55 – 0.55 % QUIESCENT VOLTAGE OUTPUT ERROR Factory Quiescent Voltage Output Error VQVOERR TA = 25°C –5 – 5 mV Quiescent Voltage Output Temperature Error VOUT(Q)TC TA = 25°C to 150°C –5 – 5 mV TA = –40°C to 25°C –5 – 5 mV Quiescent Voltage Output Ratiometry ErrorVRatERRVOUT(Q) VCC = 4.85 to 5.15 V –5 – 5 mV LIFETIME QVO Lifetime Drift VQVOLife TA = 25°C – 0.8 – mV Sens Lifetime Drift SensERR_Life TA = 25°C – 0.5 – % [1] Using small RL will increase output error; this error scales with output causing offset and symmetry error, i.e. using a RL = 4.7 kΩ will cause a 4 mV error due to the resis- tor divider between the RL(pulldown) and the internal resistance of 4 Ω at 5 V output. Keep this in mind when sizing RL. [2] Overvoltage Detection was characterized on the bench. [3] Devices programed to the typical values are guaranteed to meet the VOUT(Q)TC spec. [4] This is an average and actual step can vary. For best results, check QVO after every retrim. Refer to the Quiescent Voltage Output Programming Resolution in the defini- tion section. [5] Allegro guarantees limits of devices that remains within their factory programed SEN_COARSE and the corresponding SENSPR during customer programing. [6] Device performance is guaranteed within these ranges. [7] LinErr valid from 0 to ±2000 G, validated by characterization and design. OPERATING CHARACTERISTICS (continued): Valid over full operating temperature range of TA, CBYPASS = 0.1 µF, and VCC = 5 V, unless otherwise specified

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com CHARACTERISTIC DEFINITIONS Power-On Time (tPO) When the supply is ramped to its operating voltage, the device requires a finite time to power its internal components before responding to an input magnetic field. Power-On Time (t PO ) is defined as: the time it takes for the out- put voltage to settle within ±10% of its steady-state value under an applied magnetic field, after the power supply has reached its minimum specified operating voltage (V CC(min)) as shown in Figure 4. Temperature Compensation Power-On Time (tTC ) After Power-On Time (tPO ) elapses, tTC is also required before a valid temperature compensated output. Propagation Delay (tpd) The time interval between a) when the applied magnetic field reaches 20% of its final value, and b) when the output reaches 20% of its final value (see Figure 5). Rise Time (tr) The time interval between a) when the sensor IC reaches 10% of its final value, and b) when it reaches 90% of its final value (see Figure 2). Response Time (tRESPONSE) The time interval between a) when the applied magnetic field reaches 90% of its final value, and b) when the sensor reaches 90% of its output corresponding to the applied magnetic field (see Figure 6). The 90%-90% is also shown in the Electrical Characteristics table and in the performance data. Figure 4: Power-On Time Definition Figure 5: Propagation Delay and Rise Time Definitions Figure 6: Response Time Definition V VCC VCC(min) VOUT 90% VOUT t1= time at which power supply reaches minimum specified operating voltage t2= time at which output voltage settles within ±10% of its steady-state value under an applied magnetic field t1 t2 tPO VCC(typ) Applied Magnetic Field Transducer Output (%) Propagation Delay, tpd Rise Time, tr t Applied Magnetic Field Transducer Output(90%-90%) (%) Response Time, tRESPONSE t

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Quiescent Voltage Output (VOUT(QU/BI)) In the quiescent state (no significant magnetic field: B = 0 G), the output (VOUT(QU/BI) ) has a constant ratio to the supply voltage (VCC ) throughout the entire operating ranges of VCC and ambi- ent temperature (TA) . U and BI correspond to unidirectional or bidirectional mode. Before any programming, the Quiescent V oltage Output (VOUT(Q)) has a nominal value of VCC / 2 for a bidirectional device and 0.5 V for unidirectional parts with a VCC of 5 V . Quiescent Voltage Output Programming Range The Quiescent V oltage Output (VOUT(Q) ) can be programmed within the Quiescent V oltage Output limits. Exceeding the speci- fied Quiescent V oltage Output limits will cause Quiescent V olt- age Output Drift Through Temperature Range (ΔV OUT(Q)TC) to deteriorate beyond the specified values. Average Quiescent Voltage Output Program- ming Step Size (StepVOUT(Q)) The Average Quiescent V oltage Output Progamming Step Size (Step VOUT(Q) ) is determined using the following calculation: VOUT(Q)maxcode – VOUT(Q)mincode 2n – 1VOUT(Q)Step = , (1) where n is the number of available programming bits in the trim range, 9 bits, V OUT(Q)maxcode is at decimal code 255, and VOUT(Q)mincode is at decimal code 256. Quiescent Voltage Output Programming Resolution The programming resolution for any device is half of its pro- gramming step size. The step size of each bit can vary. For best accuracy, check VOUT after every trim. The devices DAC performance is screened and accounted in the factory-standard trim, but becomes a possible source of error if the devices is reprogramed beyond the Qui- escent V oltage Output; programming beyond this range causes V OUT(Q)TC to be invalid. Quiescent Voltage Output Drift Through Temperature Range (VOUT(Q)TC) Due to internal component tolerances and thermal consider- ations, the Quiescent V oltage Output (VOUT(Q)) may drift from its nominal value through the operating ambient temperature (TA ). The Quiescent V oltage Output Drift Through Temperature Range VOUT(Q)TC) is defined as: DVOUT(Q)TC = VOUT(Q)(TA) – VOUT(Q)EXPECTED(TA) (2) ∆VOUT(Q)TC should be calculated using the actual measured values of ∆VOUT(Q)(TA) and ∆VOUT(Q)EXPECTED(TA) rather than programming target values. Sensitivity (Sens) The presence of a south polarity magnetic field, perpendicular to the branded surface of the package face, increases the output voltage from its quiescent value toward the supply voltage rail. The amount of the output voltage increase is proportional to the magnitude of the magnetic field applied. Conversely, the application of a north polarity field decreases the output voltage from its quiescent value. This proportionality is specified as the magnetic sensitivity, Sens (mv/G), of the device, and it is defined as: Sens = ,V– VOUT(BPOS) OUT(BNEG) BPOS – BNEG (3) where BPOS and BNEG are two magnetic fields with opposite polarities. Initial Factory-Programmed Sensitivity Before any programming, Sensitivity has a nominal value that depends on the SENS_COARSE bits setting. Each ACS70310 variant has a different SENS_COARSE setting. The parts TC per- formance is guaranteed if the SENS_COARSE bit is in its default factory value and within the Sensitivity Programing Range cor- responding to the SENS_COARSE bit. Sensitivity Programming Range (SensPR) The magnetic sensitivity (Sens) can be programmed around its initial value within the sensitivity range limits: Sens PR(min) and SensPR(max). Exceeding the specified Sensitivity Range will cause Sensitivity Drift Through Temperature Range (ΔSensTC) to deteriorate beyond the specified values.

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Average Fine Sensitivity Programming Step Size (StepSENS) This the change is the fine sensitivity parameter per code of sensf DAC. This value changes depending on SENS_COARSE. Keep in mind that the over temperature performance of the device is guaranteed only for the factory programed SENS_COARSE and its associated SENSPR. Sensitivity Programming Resolution This resolution is equal to or less than 1/2 × StepSENS. If the device is more than 1/2 × StepSENS but less than one StepSENS away from a desired trim, then an additional step in the correct direction will yield a resolution less than 1/2 × Step SENS. Sensitivity Drift Through Temperature Range (ΔSens TC ) Second-order sensitivity temperature coefficient effects cause the magnetic sensitivity, Sens, to drift from its expected value over the operating ambient temperature range (T A). The Sensitivity Drift Through Temperature Range (∆SensTC ) is defined as: SensTA – SensEXPECTED(TA) SensEXPECTED(TA) ∆SensTC = × 100% . (4) Output Voltage Operating Range The functional range for optimal performance of the device is between 4.5 to 0.5 V output voltage while VCC = 5 V . The device can respond to magnetic fields that cause the output to go beyond these voltages, but parameters may not meet datasheet limits. Sensitivity Non-Linearity Error (LinERR ) The ACS70310 is designed to provide a linear output in response to a ramping applied magnetic field. LinERR is valid from 0 G to ±2000 G input field while within the Output V oltage Operat- ing Range. Consider two magnetic fields, B1 and B2. Ideally, the sensitivity of a device is the same for both fields, for a given sup- ply voltage and temperature. Linearity error is present when there is a difference between the sensitivities measured at B1 and B2. Linearity error is calculated separately for the positive SensB POS2 (LinERRPOS ) and negative (LinERRNEG ) applied magnetic fields. Linearity Error (%) is measured and defined as: SensB(POS,NEG)2 SensB(POS,NEG)1 1–LinERR(POS,NEG) = × 100% (5) where: |VOUT(Bx) – VOUT(Q)| Bx SensBx = , (6) and BPOSx and BNEGx are positive and negative magnetic fields, with respect to the quiescent voltage output such that Then: LinERR max( LinERRPOS , LinERRNEG )= . (7) Ratiometry Error (RatERR ) The ACS70310 device features a ratiometric output. This means that the Quiescent V oltage Output (VOUT(Q) ), magnetic sensitiv- ity, Sens, and Output V oltage Clamp (VCLP(HIGH) and VCLP(LOW) ) are proportional to the Supply V oltage (VCC). In other words, when the supply voltage increases or decreases by a certain percentage, each characteristic also increases or decreases by the same percentage. Ratiometry Error is the difference between the measured change in the supply voltage relative to 5 V , and the measured change in each characteristic. The ratiometric error in Quiescent V oltage Output, RatERRVOUT(Q) (%), for a given supply voltage (VCC) is defined as: VOUT(QBI)(VCC) VCC 1 –RatERRVOUT(QBI) = × 100% . VOUT(QBI)(5V) 5 V (8) RatERRVOUT(QU) is defined in the same way as RatERRVOUT(QBI) with a factor of 1/5 multiplied. This is to scale the ratiometry error of the unidirectional device so that it can be compared with the bidirectional device. The ratiometric error in magnetic sensitivity, RatERRSens (%), for a given Supply V oltage (VCC ) is defined as: Sens(VCC) / Sens(5V) VCC / 5 V1–RatERRSens = × 100% . (9)

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Power-On Reset Voltage (VPOR ) On power-up, to initialize to a known state and avoid current spikes, the ACS70310 is held in a reset state. The reset signal is disabled when V CC reaches VPORH and time tPORR has elapsed, allowing the output voltage to go from a high-impedance state into normal operation. During power-down, the reset signal is enabled when V CC reaches VPORL , causing the output voltage to go into a high-impedance state. (Note that a detailed description of POR can be found in the Functional Description section). Power-On Reset Release Time (tPORR) When VCC rises to VPORH , the Power -On Reset counter starts. The ACS70310 output voltage will transition from a high-imped- ance state to normal operation only when the Power-On Reset Counter has reached t PORR and VCC has been maintained above VPORH . Output Saturation Voltage (VSAT ) When output voltage clamps are disabled, the output voltage can swing to a maximum of V SAT(HIGH) and to a minimum of VSAT(LOW) . Broken Wire Voltage (VBRK ) If the GND pin is disconnected (broken wire event), the output voltage will go to V BRK(HIGH) (if a load resistor is connected to VCC) or to VBRK(LOW) (if a load resistor is connected to GND). Mold Ejector Pin Indent Branded Face Magnetic Flux Direction Causing the Output to Increase Figure 7: Magnetic Flux Polarity

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com FUNCTIONAL DESCRIPTIONS Power-On Reset (POR) The descriptions in this section assume: Temperature = 25°C, no output load (RL, CL), and no significant magnetic field is present. When the device is off, the output will be in a high-impedance state. Power-On As VCC ramps up, the device output is in high impedance until VCC reaches VPOR(H). As VCC rises above VPOR(H), the device’s output leaves the high impedance state and enters normal operat- ing mode. Overvoltage Detection (VOVD) When VCC is raised above the Overvoltage Detection enable volt- age (VOVD(EN)), the ACS70310 output stage enters high imped- ance. VOUT will float: to VCC with a pull-up RL, or to GND with a pull-down RL, when VOVD(EN) is reached. When programing the ACS70310, Overvoltage Detection must be active for com- munication. The ACS70310 output will resume normal operation after V CC is below the Overvoltage Detection disable voltage VOVD(DIS). Note that Supply V oltage limits still apply for operat- ing characteristic. Power-Down As VCC ramps down, the device output is active until VCC falls below VPOR(L). As VCC falls below VPOR(L), the device’s output will enter a high impedance state. Power On/Off Profile Figure 8 shows the analog output of a device at power on and power off. Figure 8: Power On/Off and Overvoltage Detection (OVD), no R L VCC = C1 (yellow), VOUT = C2 (red), ICC = C4/10 (green)

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Figure 9: Rise Time: 110 G excitation signal with 10%-90% rise time = 700 ns, Input = C4 × 5 G/A (green), VOUT = C2 (red), no CL or RL, CBY = 0.1 µF Figure 10: Response Time plot of 90%-90% (input to output):

110 G excitation signal with rise time 10%-90% = 700 ns,

Input = C4 × 5 G/A (green), VOUT = C2 (red), no CL or RL, CBY = 0.1 µF

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Figure 11: Propagation Delay from 20%-20% (input to output): Input = C4 × 5 G/A (green), VOUT = C2 (red), no CL or RL, CBY = 0.1 µF

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com PROGRAMMING GUIDELINES The serial interface uses a bidirectional communication on VOUT. When the voltage on the VCC pin is increased beyond the pro- gramming threshold, the device will enter programming mode. The device has an internal charge pump to generate the EEPROM pulses. Recommended programing kits/subkits and software can be found under the Technical Docs on the ACS70310 product page at the www.allegromicro.com website. sdata_out_en out_dis VOUT 0 0 Analog output 0 1 High-Z

1 X sdata_out

– Manchester Code Read Acknowledge – Manchester Code VCC (package pin) VOUT (package pin) Analog Output sdata_out_en sdata_out dis_out Serial Interface Digital OVD Timer OVD Detect

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Memory-Locking Mechanisms The ACS70310 is equipped with two distinct memory-locking mechanisms:

• Default Lock: At power-up, all registers of the ACS70310 are locked by default. EEPROM and volatile memory cannot be read or written. To disable Default Lock, a specific 32-bit customer access code has to be written to address 0x36 within Access Code Timeout (t ACC = 10 ms) from power-up. After doing so, registers can be accessed. If VCC is power-cycled, the Default Lock will automatically be re-enabled. This ensures that during normal operation, memory content will not be altered due to unwanted glitches on VCC or the output pin.
• Lock Bit: After EEPROM has been programmed by the user, the EELOCK bit can be set high and VCC power-cycled to permanently disable the ability to read or write any register. This will prevent the ability to disable Default Lock using the method described above. Note that after the EELOCK bit is set high and the VCC pin has been power-cycled, the EELOCK bit can no longer be cleared and registers can no longer be written to. Serial Communication The serial interface allows an external controller to read and write registers, including EEPROM, in the ACS70310 using a point-to-point command/acknowledge protocol. The ACS70310 does not initiate communication; it only responds to commands from the external controller. Each transaction consists of a com- mand from the controller. If the command is a write, there is no acknowledging from the ACS70310. If the command is a read, the ACS70310 responds by transmitting the requested data. Serial interface timing parameters can be found in the Program- ming Levels table (Table 1). Note that the external controller must avoid sending a Command frame that overlaps a Read Acknowledge frame. The serial interface uses a Manchester-encoding-based protocol per G.E. Thomas (0 = rising edge, 1 = falling edge), with address and data transmitted MSB first. Four commands are recognized by the ACS70310: Write Access Code, Write to V olatile Memory, Write to Non-V olatile Memory (EEPROM) and Read. One frame type, Read Acknowledge, is sent by the ACS70310 in response to a Read command. Synchronize Bit boundaries VMAN(L) VMAN(H) 0 V Memory Address Data CRC Read/Write 0 0 0/1 0 0 01 Figure 12: General Format for Serial Interface Commands

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com The ACS70310 device uses a three-wire programming interface, where VCC is used to control the program enable signal, data is transmitted on VOUT, and all signals are referenced to GND. This three-wire interface makes it possible to communicate with multiple devices with shared VCC and GND lines. The four transactions (Write Access, Write to EEPROM, Write to V olatile Memory, and Read) are show in the figures on the following pages. To initialize any communication, V CC should be increased to a level above VprgH(min) without exceeding VprgH(max). At this time, VOUT is disabled and acts as an input. After program enable is asserted, the external controller must drive the output low in a time less than t d . This prevents the device interpreting any false transients on VOUT as data pulses. After the command is completed, V CC is reduced below VprgL, back to normal operating level. Also, the output is enabled and responds to magnetic input. When performing a Write to EEPROM transaction, the ACS70310 requires a delay of t w to store the data into the EEPROM. The device will respond with a high-to-low transition on VOUT to indicate the Write to EEPROM sequence is com- plete. When sending multiple command frames, it is not necessary to toggle the program enable signal on VCC. After the first com- mand frame is completed, and V CC remains at VprgH , the device will ignore any subsequent pulses on the output. When the pro- gram enable signal is brought below VprgL(max) , the output will respond to the magnetic input. Synchronize MSB MSB Memory Address Data CRC Read/Write Figure 13: Command Frame General Format Quantity of Bits Name Values Description

2 Synchronization 00 Used to identify the beginning of a serial interface command

1 Read / Write

0 [As required] Write operation 1 [As required] Read operation

6 Address 0/1 [Read/Write] Register address (volatile memory or EEPROM)

32 Data 0/1

26 data bits and 6 ECC bits. For a read command frame the data consists of 32 bits: [31:28] Don’t Care, [27:26] ECC Pass/Fail, and [25:0] Data. Where bit 0 is the LSB. For a write command frame the data consists of 32 bits: [31:26] Don’t Care and [25:0] Data. Where bit 0 is the LSB. 3 CRC 0/1 Bits to check the validity of frame.

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Table 1: Programming Parameters, CBYPASS = 0.1 µF, VCC = 5 V Characteristics Symbol Note Min. Typ. Max. Unit Program Enable Voltage (High) VprgH Program enable signal high level on VCC – 9.2 – V Program Enable Voltage (Low) VprgL Program enable signal low level on VCC – 6.5 – V Output Enable Delay te External capacitance (CLX) on VOUT may increase the Output Enable Delay – 125 – µs Program Time Delay td – 74 – µs Program Write Delay tw – 20 – ms Manchester High Voltage VMAN(H) Data pulses on VOUT 4 5 VCC V Manchester Low Voltage VMAN(L) Data pulses on VOUT 0 – 1 V Bit Rate tBITR Communication rate 1 30 100 kbps Bit Time tBIT Data bit pulse width at 30 kbps – (33) – µs Access Code Timeout tACC 10 ms VOUT (Output) VOUT (Input) External Control VCC VprgH High Z Access Code High ZHigh Z Normal Output Normal Output VprgL 5 V 5 V 0 V 0 V td te Figure 14: Write Access Code Figure 15: Write Volatile Memory VOUT (Output) VOUT (Input) External Control VCC VprgH High Z High ZHigh Z Normal Output Normal Output VprgL 5 V 5 V 0 V 0 V t d te DataWrite Command Figure 16: Write Non-Volatile Memory VOUT (Output) VOUT (Input) External Control VCC VprgH High Z High ZHigh Z Normal Output Normal Output VprgL 5 V 5 V 0 V 0 V t d te DataWrite Command twtd VCC Figure 17: Read VOUT (Output) VOUT (Input) External Control VCC VprgH High Z High ZHigh Z Normal Output Normal Output VprgL 5 V 5 V 0 V 0 V t d te Data Read Command td VCC

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com MANCHESTER COMMUNICATION tbit Sync Write MSB Manchester Stream Addr Data CRC Manchester Write Command 0 0 0 Addr CRCManchester Stream tbit Sync Read MSB Manchester Read Command 0 0 1 Command Format Write Command Sync R/W Address (6 bits) Data (32 bits) CRC Bit Boundaries 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 1 1 1 0 0 1 0 1 Read Command Read Acknowledge Sync R/W Address (6 bits) CRC Sync CRC Data (32 bits) 0 0 1 0 1 1 0 0 0 0 1 0 0 0 0 1 0 1 0 1 1 1 1 0 0 1 0 1

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Parameter Description Min. Max. tsclk System clock period after trimming. 133 ns (7.5 MHz) 167 ns (6 MHz) tbit Bit time. 1 µs (1 MBd) 1 ms (1 kBd) tDIS_TOP OUT pin is disabled after raising VCC. 56 µs (512 × tsclk) 73.5 µs (514 × tsclk) tOUTH_1ST_TOP The OUT pin is either pulled high or low. No low-to-high transitions are allowed after this MAX time except to start the Manchester command. This is for the 1st Manchester command after raising VCC. 73.5 µs 123 µs t CMD_1ST_TOP Time required before the 1st Manchester command can be sent after raising VCC. 144 µs n/a tLOW Time required to hold output low before the 1st Manchester edge. 1 µs n/a M Data tLOW tCMD_1ST_TOP tOUTH_1ST_TOP tDIS_TOP switch point VCC Nominal OUT OUT is active Device stops driving OUT by here OUT can be pulled high or low Past this MAX time OUT cannot transition Low to High except to start Manchester OUT is required to be low before a Manchester command Earliest time for Manchester command Generic Timing For initial portion of Manchester command

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Parameter Description Min. Max. tsclk System clock period after trimming. 133 ns (7.5 MHz) 167 ns (6 MHz) tbit Bit time. 1 µs (1 MBd) 1 ms (1 kBd) tACK_EN Time for the device to drive OUT after Manchester command. Host must stop driving OUT within this time. 2 × tbit 2 × tbit tEE_WR During this time the device is writing the EEPROM – – tEE_ACK Device will drive OUT low during this time 1 × tbit 1 × tbit tOUTH The OUT pin is either pulled high or low. No low-to-high transitions are allowed after this MAX time except to start the next Manchester command. 0 1.8 × t bit tCMD_EE Time before the next Manchester command may be given following a write to EEPROM. 2.2 × tbit n/a tLOW Time required to hold output low before the 1st Manchester edge. 1 µs n/a M Data tLOW VCC or comm_en OUT OUT can be pulled high or low Past this MAX time OUT cannot transition Low to High except to start Manchester OUT is required to be low before a Manchester command Earliest time for Manchester command Write to EEPROM If VCC is held up at the programming voltage, multiple Manchester commands can be executed. M Data Device drives low for ACK EEPROM write complete Host stops driving OUT by here Manchester command to write EEPROM tEE_WR tACK_EN tEE_ACK tOUTH tCMD_EE

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Parameter Description Min. Max. tsclk System clock period after trimming. 133 ns (7.5 MHz) 167 ns (6 MHz) tbit Bit time. 1 µs (1 MBd) 1 ms (1 kBd) tCMD_R Time before the next Manchester command may be given following a write to a Register. 2 µs n/a M Data M Data tCMD_R VCC or comm_en OUT Manchester command to write EEPROM Host holds OUT low Earliest time for next Manchester command Write to Register (Not EEPROM)

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Read (Controller to ACS70310) The fields for the Read command are:

• Sync (2 zero bits)
• Read/Write (1 bit, must be 1 for read)
• CRC (3 bits) Figure 18 shows the sequence for a Read command. Synchronize MSB Memory Address CRC Read/Write 0 0 1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Figure 18: Read Sequence Read Acknowledge (ACS70310 to Controller) The fields for the data return frame are:
• Sync (2 zero bits)
• Data (32 bits): □ [31:28] Don’t Care □ [27:26] ECC Pass/Fail □ [25:0] Data Figure 19 shows the sequence for a Read Acknowledge. Refer to the Detecting ECC Error section for instructions on how to detect Read/Write Synchronize Memory Address Data (32 bits) and ECC failure. Synchronize MSB Data (32 bits) CRC Figure 19: Read Acknowledgement Sequence Write (Controller to ACS70310) The fields for the Write command are:
• Sync (2 zero bits)
• Read/Write (1 bit, must be 0 for write)
• Address (6 bits)
• Data (32 bits): □ [31:26] Don’t Care □ [25:0] Data
• CRC (3 bits) Figure 20 shows the sequence for a Write command. Bits [31:26] are Don’t Care because the ACS70310 automatically generates 6 ECC bits based on the content of bits [25:0]. These ECC bits will be stored in EEPROM at locations [31:26]. Synchronize MSB MSB Memory Address Data (32 bits) CRC Read/Write Figure 20: Write Sequence Write Access Code (Controller to ACS70310) The fields for the Access Code command are:
• Sync (2 zero bits)
• Read/Write (1 bit, must be 0 for write)
• Address (6 bits, address 0x36 for Customer Access)
• Data (32 bits, 0xC4136737 for Customer Access)
• CRC (3 bits) Figure 21 shows the sequence for an Access Code command. Synchronize MSB MSB Memory Address Data (32 bits) CRC Read/Write 0 0 0 1 0 0 1 0 0 0/1 0/1 0/1 0/10/1. . . 0/1 0/1 Figure 21: Write Access Code The controller must open the serial communication with the ACS70310 device by sending an Access Code. It must be sent within Access Code Timeout, t ACC, from power-up, or the device will be disabled for read and write access. Access Codes Information Name Serial Interface Format Register Address (Hex) Data (Hex) Customer 0x36 0xC4136737

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com EEPROM Error Checking and Correction (ECC) Hamming code methodology is implemented for EEPROM checking and correction. The device has ECC enabled after power-up. The device always returns 32 bits. The message received from controller is analyzed by the device EEPROM driver and ECC bits are added. The first 6 received bits from device to controller are dedicated to ECC. Detecting ECC Error If an uncorrectable error has occurred, bits 27:26 are set to 10, the VOUT pin will go to a high-impedance state, and the device will not respond to the applied magnetic field. EEPROM ECC Errors Bits Name Description 31:28 – No meaning 27:26 ECC 00 = No Error 01 = Error detected and message corrected 10 = Uncorrectable error 11 = No meaning 25:0 D[25:0] EEPROM data Table 2: Customer Memory Map Address Register Name Parameter Name Description r/w Bits Location 0x4 scratch_c customer_scratch Unused area RW 26 25:0 0x5 cust0_c sensf Sensitivity, fine adjustment RW 9 8:0 qvof Quiescent Output Voltage (QVO), fine adjustment RW 9 17:9 sensc Coarse Sensitivity RW [1] 2 19:18 0x6 cust1_c rat_dis Ratiometry disable. Sens and VOUT(Q) are not guaranteed if ratiometry is disabled. RW 1 2 uni_en Enables Unidirectional Output RW 1 4 clamp_en Clamp enable RW 1 5 pol Reverses output polarity RW 1 6 dev_lock Bit to lock the serial interface from receiving data RW 1 7 0x29 status_c customer_access Customer write access enabled RO 1 0 [1] Overtemperature performance is no longer valid if this register is changed from factory default.

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com For Reference Only - Not for Tooling Use (Reference DWG-9202) Dimensions in millimeters - NOT TO SCALE Dimensions exclusive of mold flash, gate burs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown

0.54 REF

12.14 ±0.05

1.27 NOM

0.89 MAX

10° A B C D E Dambar removal protrusion (16X) Gate and tie burr area Molded Lead Bar for preventing damage to leads during shipment Active Area Depth, 0.37 mm REF Branding scale and appearance at supplier discretion C = Device part number = Last two digits of year of manufacture = Week of manufacture N Y W Standard Branding Reference View F Hall element, not to scale 24 31 A D F F F 2.60 1.41 E 5.21+0.08 –0.05 5.21+0.08 –0.05 3.43+0.08 –0.05 0.41 +0.08 –0.05 1.50 +0.08 –0.05 0.20+0.08 –0.05 1.00 +0.08 –0.05 1.00 +0.08 –0.05 Mold Ejector Pin Indent Branded Face B NNNN YYWW PACKAGE OUTLINE DRAWING Figure 22: Package KT, 4-Pin SIP, TN Leadform

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Figure 23: Package KT, 4-Pin SIP, TF Leadform NOTES: 1) LEAD TRIM AND FORMING OPERATIONS PERFORMED ON ALLEGRO SUPPLIED MATERIAL. 2) FOR DIMENSIONS AND TOLERANCING ON SUPPLIED DEVICES, REFER TO ALLEGRO DWG-9202. 3) TRUE POSITION AND PROFILE TOLERANCE APPLIES ALONG EACH LEAD IN A ZONE STARTING FROM THE LEAD TIP AND ENDING NO MORE THAN 10 mm IN FROM THE TIP. R.20 (4×) A (3.43) (5.21) (9.33)(9.54) LEADS PRIOR TO BENDING PIN 1 ACTIVE SURFACE 4.5 2.4 C B C B A A B A 0.6 2.35 2.35 A A B B 0.4 C (4×) SEE NOTE 3 1.97 3.24 0.70 4.51 0.41 PIN 1PIN 2 PIN 4 PIN 3 SECTION A-A (PINS 1 AND 4) SCALE 5:1 5.49 4.30 91.3° ± 1.0°A B (REF)

0.20 A B

0.2 D (PIN 1) SEE NOTE 3 (PIN 4) SEE NOTE 3 D SECTION B-B (PINS 2 AND 3) SCALE 5:1 5.49 A 91.3° ± 1.0° 4.30 B 0.15 E (PIN 3) SEE NOTE 3 E (PIN 2) SEE NOTE 3 (REF) METRIC TOLERANCES X ± 10% X.X ± 0.25 X.XX ± 0.10 X.XXX ± 0.025 ANGULAR ± 0.5° ALL SURFACES TO BE 32 µin (0.80 µm) OR BETTER BREAK ALL SHARP EDGES 0.015" HOLD ALL DIMS AFTER PLATING REFERENCE DWG-0000425 0.762 5.20.508 4.7 PCB LAYOUT REFERENCE VIEW

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Figure 24: Package KT, 4-Pin SIP, TG Leadform NOTES: 1) LEAD TRIM AND FORMING OPERATIONS PERFORMED ON ALLEGRO SUPPLIED MATERIAL. 2) FOR DIMENSIONS AND TOLERANCING ON SUPPLIED DEVICES, REFER TO ALLEGRO DWG-9202. 3) TRUE POSITION AND PROFILE TOLERANCE APPLIES ALONG EACH LEAD IN A ZONE STARTING FROM THE LEAD TIP AND ENDING NO MORE THAN 10 mm IN FROM THE TIP. METRIC TOLERANCES X ± 10% X.X ± 0.25 X.XX ± 0.10 X.XXX ± 0.025 ANGULAR ± 0.5° ALL SURFACES TO BE 32 µin (0.80 µm) OR BETTER BREAK ALL SHARP EDGES 0.015" HOLD ALL DIMS AFTER PLATING REFERENCE DWG-0000622 PIN 1 ACTIVE SURFACE 2.30 2.30 0.4 B // 0.2 CZ B PINS 1,4 0.4 B // 0.15 CZ B PINS 2,3 4.34.1 3.81 1.27 2.54 ZERO POINT FOR LEAD TIP POSITION MEASUREMENT PIN 1 PIN 2 PIN 4PIN 3

0.4 A B

4 LEAD TIPS

A DATUM TARGETS SCALE 10 : 1 (5.2) C 0.6 0.6 PIN 1 2.54 1.7 2.3 C1C2 B 0.762 5.20.508 4.7 PCB LAYOUT REFERENCE VIEW

Very High Precision, Programmable Linear Hall-Effect Sensor IC with Reverse Battery Protection and High-Bandwidth (240 kHz) Analog Output for Core-Based Current Sensing ACS70310 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com For the latest version of this document, visit: www.allegromicro.com

Revision History

– February 27, 2019 Initial release 1 April 10, 2019 Removed Internal Bandwidth min/max values (page 5) and added TF/TG leadform footprints (pages 25-26) Copyright 2019, Allegro MicroSystems. Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents.