ACS630MS RENESAS | Alldatasheet
Document overview
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Technical content
Features
- Devices QML Qualified in Accordance with MIL-PRF-38535
- Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96711 and Intersil’ QM Plan
- 1.25 Micron Radiation Hardened SOS CMOS
- Total Dose >300K RAD (Si)
- Single Event Upset (SEU) Immunity: <1 x 10 -10 Errors/ Bit/Day (Typ)
- SEU LET Threshold>100 MEV-cm2/mg
- Dose Rate Upset>1011 RAD (Si)/s, 20ns Pulse
- Dose Rate Survivability>1012 RAD (Si)/s, 20ns Pulse
- Latch-Up Free Under Any Conditions
- Military Temperature Range-55oC to +125oC
- Significant Power Reduction Compared to ALSTTL Logic
- DC Operating Voltage Range 4.5V to 5.5V
- Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min
- Input Current 1A at VOL, VOH
- Fast Propagation Delay37ns (Max), 24ns (Typ)
Description
The Intersil ACS630MS is a Radiation Hardened 16-bit parallel error detection and correction circuit. It uses a modified Ham- ming code to generate a 6-bit check word from each 16-bit data word. The check word is stored with the data word during a memory write cycle; during a memory read cycle a 22-bit word is taken form memory and checked for errors. Single bit errors in the data words are flagged and corrected. Single bit errors in check words are flagged but not corrected. The position of the incorrect bit is pinpointed, in both cases, by the 6-bit error syndrome code which is output during the error correction cycle. The ACS630MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic Family. The ACS630MS is supplied in a 28 lead Ceramic Flatpack (K suffix) or a 28 Lead Ceramic Dual-In-Line Package (D suffix). Pinouts
28 PIN CERAMIC DUAL-IN-LINE, MIL-STD-1835 DESIGNATOR
CDIP2-T28, LEAD FINISH C TOP VIEW
28 PIN CERAMIC FLATPACK, MIL-STD-1835 DESIGNATOR
CDFP3-F28, LEAD FINISH C TOP VIEW DEF DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 GND VCC CB0 CB1 CB3 CB5 DB15 DB14 DB13 DB12 SEF CB2 CB4 DEF DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 GND VCC SEF CB0 CB1 CB2 CB3 CB4 CB5 DB15 DB14 DB13 DB12
Ordering Information
PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE 5962F9671101VXC -55 oC to +125oC MIL-PRF-38535 Class V 28 Lead SBDIP 5962F9671101VYC -55 oC to +125oC MIL-PRF-38535 Class V 28 Lead Ceramic Flatpack ACS630D/Sample 25 oC Sample 28 Lead SBDIP ACS630K/Sample 25 oC Sample 28 Lead Ceramic Flatpack ACS630HMSR 25 oCD i e D i e
FN3199 Rev 1.00 Page 2 of 3 January 1996 Function Tables Control Functions MEMORY CYCLE CONTROL EDAC FUNCTION DATA I/O CHECKWORD ERROR FLAGS S1 S0 SEF DEF WRITE Low Low Generates Checkword Input Data Output Checkword Low Low READ Low High Read Data and Check- word Input Data Input Checkword Low Low READ High High Latch and Flag Error Latch Data Latch Checkword Enable d Enabled READ High Low Correct Data Word and Generate Syndrome Bits Output Corrected Data Output Syndrome Bits Enabled Enabled Check Word Generation CHECKWORD BIT 16-BIT DATA WORD 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 C B 0 XX XX XXX X C B 1 X XX XX X X X C B 2 X XX XXX X X C B 3 XXX XX XXX C B 4 XXXXX XXX C B 5 XXXXXXXX NOTE: The six check bits are parity bits derived from the matrix of data bits as indicated by “x” for each bit Error Syndrome Codes SYNDROME ERROR CODE ERROR LOCATIONS DB CB NO ERROR0123456789 1 0 1 1 1 2 1 3 1 4 1 5 012345 C B 0 L LHL LHHHL L LHHLHHLHHHHH H C B 1 LHL LHL LHLHHLHHLHHLHHHH H C B 2 HLLHLLHLHLHHLHHLHHLHHH H C B 3 L L LHHHL LHHL L LHHHHHHLHH H C B 4 H H HLLLLL HHHHHL L LHHHHLH H C B 5 HHHHHHHH LLLLLLLL HHHHHL H Error Functions TOTAL NUMBER OF ERRORS ERROR FLAGS DATA CORRECTION16-BIT DATA 6-BIT CHECKWORD SEF DEF 0 0 Low Low Not Applicable 1 0 High Low Correction 0 1 High Low Correction 1 1 High High Interrupt 2 0 High High Interrupt 0 2 High High Interrupt
FN3199 Rev 1.00 Page 3 of 3 January 1996 ACS630MS Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 1999. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Die Characteristics DIE DIMENSIONS: 171 mils x 159 mils 4340mm x 4040mm METALLIZATION: Type: AlSi Metal 1 Thickness: 7.125k Å 1.125kÅ Metal 2 Thickness: 9kÅ 1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ 1kÅ WORST CASE CURRENT DENSITY: <2.0 x 105A/cm2 BOND PAD SIZE: 110m x 110m 4.4 mils x 4.4 mils Metallization Mask Layout ACS630MS DEFDB0DB1DB2 VCC SEF S1 DB3 (5) DB4 (6) DB5 (7) DB6 (8) DB7 (9) DB8 (10) DB9 (11) (25) S0 (24) CB0 (23) CB1 (22) CB2 (21) CB3 (20) CB4 (19) CB5 DB10 DB11 GND DB12 DB13 DB14 DB15