ACS541MS RENESAS | Alldatasheet
Document overview
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- PDF pages: 3
Technical content
Features
- Devices QML Qualified in Accordance with MIL-PRF- 38535
- Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96710 and Intersil’s QM Plan
- 1.25 Micron Radiation Hardened SOS CMOS
- Total Dose >300K RAD (Si)
- Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/ Bit/Day (Typ)
- SEU LET Threshold>100 MEV-cm2/mg
- Dose Rate Upset>1011 RAD (Si)/s, 20ns Pulse
- Dose Rate Survivability>1012 RAD (Si)/s, 20ns Pulse
- Latch-Up Free Under Any Conditions
- Military Temperature Range-55oC to +125oC
- Significant Power Reduction Compared to ALSTTL Logic
- DC Operating Voltage Range 4.5V to 5.5V
- Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min
- Input Current 1A at VOL, VOH
- Fast Propagation Delay17ns (Max), 12ns (Typ)
Description
The Intersil ACS541MS is a Radiation Hardened Octal Buf- fer/Line Driver, with three-state outputs. The output enable pins OE1 , OE2 control the Three-State outputs. If either enable is high the output will be in a high impedance state. For data output both enables must be low. The ACS541MS utilizes adv anced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic family. The ACS541MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or a Ceramic Dual-In-Line package (D suffix). Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C TOP VIEW
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C TOP VIEW 1OE1 GND VCC OE2 12 0 OE1 GND VCC OE2
Ordering Information
PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE 5962F9671001VRC -55 oC to +125oC MIL-PRF-38535 Class V 20 Lead SBDIP 5962F9671001VXC -55 oC to +125oC MIL-PRF-38535 Class V 20 Lead Ceramic Flatpack ACS541D/Sample 25 oC Sample 20 Lead SBDIP ACS541K/Sample 25 oC Sample 20 Lead Ceramic Flatpack ACS541HMSR 25 oCD i e D i e
FN4085 Rev.0.00 Page 2 of 3 January 1996 ACS541MS Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 1999. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Functional Diagram TRUTH TABLE INPUTS OUTPUTS OE1 OE2 An Yn LLH H LLLL HXXZ XHXZ NOTE: L = Low Logic Level, H = High Logic Level, Z = High Impedance VCC GND VCC GND VCC GND VCC GND VCC GND VCC GND VCC GND VCC GND OE1 OE2 VCC GND
FN4085 Rev.0.00 Page 3 of 3 January 1996 Die Characteristics DIE DIMENSIONS: 102 mils x 102 mils 2,600mm x 2,600mm METALLIZATION: Type: AlSi Metal 1 Thickness: 7.125kÅ 1.125kÅ Metal 2 Thickness: 9kÅ 1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ 1kÅ WORST CASE CURRENT DENSITY: <2.0 x 105 A/cm2 BOND PAD SIZE: > 4.3 mils x 4.3 mils > 110m x 110m Metallization Mask Layout ACS541MS (1) OE1 (2) A0 (20) VCC (16) Y2 GND (10) Y7 (11) Y6 (12) NC A2 (4) A6 (8) (14) Y4 (15) Y3 A3 (5) NC A4 (6) NC A5 (7) A7 (9) Y5 (13) (17) Y1 NC (3) A1 (18) YO (19) OE2