ACS422MX68

ACS422MX68 IDT | Alldatasheet

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LOW-POWER, HIGH-FIDELITY INTEGRATED CODEC ACS422Mx68 1 V1.2 1/12 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS422MX68 The ACS422Mx68 is a low-power, high-fidelity integrated CODEC targeted at portable applications such as tablet computers, personal navigation devices, portable projectors and speaker docks. In addition to a high-fidelity low-power CODEC, the device integrates a MONO DDX TM Class D speaker amplifier and a true cap-less headphone amplifier. Beyond high-fidelity for portable systems, the device offers an enriched “audio presence” through built-in audio processing capability. TARGET APPLICATIONS

• Tablet Computers
• Portable Navigation Devices
• Personal Media Players
• Portable Projectors
• Speaker Docks

FEATURES

• High fidelity 24-bit stereo CODEC
• DAC 102dB SNR; THD+N better than -82dB
• ADC 90dB SNR, THD + N better than -80dB
• Built in audio controls and processing
• 3D stereo enhancement
• Dual (cascaded) stereo 6-ba nd parametric equalizers
• Programmable Compressor/Limiter/Expander
• Psychoacoustic Bass and Treble enhancement processing
• Filterless Mono DDX TM Class D Speaker Driver
• 1W/channel (8 ) or 2W/channel (4), 0.05% THD+N typical
• Tri-state DDX TM Class D achieves low EMI and high efficiency
• >80% efficiency at 1W
• Spread spectrum support for reduced EMI output power mode
• Anti-Pop circuitry
• On-chip true cap-less headphone driver
• 35 mW output power (16 )
• Charge-pump allows true ground centered outputs
• SNR of 102dB
• I 2 S d a t a i n t e r f a c e
• Microphone/line-in interface
• Analog microphone or line-in inputs
• Digital microphone (ACS422MD68)
• Automatic level control
• On-chip low-jitter PLL for audio timing
• Low power with built in power management
• 1.7 V CODEC supports 1Vrms
• Very low standby and no-signal power consumption
• 1.8V digital / 1.7V analog supply for low power
• 2-wire (I 2C compatible) control interface
• 68-pin dual row 6x6 mm TLA package DDXTM and the DDX logo are trademarks of Apogee Technology.

1 V1.2 1/12 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS422MX68 ACS422Mx68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC TABLE OF CONTENTS

2 V1.2 1/12 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS422MX68 ACS422Mx68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC

3 V1.2 1/12 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS422MX68 ACS422Mx68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC

2W/channel (4) filterless DDXTM mono class D amplifier, and microphone interface with programmable gain. Figure 1. Block Diagram

• A 1W/channel (8 ) or 2W/channel (4) filterless MONO DDXTM Class D amplifier. This amplifier is capable of driving a MONO speaker typically found in portable equipment, providing high fidelity, high efficiency, and excellent sound quality.
• A line-out/capless stereo headphone port with ground referenced outputs, capable of driving headphones without requiring an external DC blocking capacitor. Each endpoint features independent volume controls, including a soft-mute capa bility which can slowly ramp up or down the volume changes to avoid unwanted audio artifacts. The ACS422Mx68 output signal paths consist of digital filters, DACs and output drivers. The digital filters and DACs are enabled when the ACS422Mx68 is in ‘playback only’ or ‘record and playback’ mode. The output drivers can be sepa- rately enabled by individual control bits. PLL Audio Processing Bass/Treble Enhancement SYSTEM EQ SPEAKER EQ 3-D effect Compressor-limiter Dynamic Range Expander Source Select Switch Audio Processing DAC Left HP Out LeftHP SPKR + BTL Digital PWM controller LIN3/DMIC_CLK* RIN1 DACIN VOLmute ADCOUT Anti- popDAC Left HP Out RightHPAnti- pop DAC Right Audio Processing VOLmute MIC Bias LIN1 LIN2 D2S RIN2 RIN3/DMIC_DAT* MUX LIN1 LIN2 MUX RIN1 RIN2 1 bit1 bit RIN1 RIN2 MUX RIN3 D2S LIN1 LIN2 MUX LIN3 D2S D2S MUXMUX S Clocking Control I2C_SCL I2C_SDA DACLRCLK ADCLRCLK DACBCLK ADCBCLK MCLK Internal Audio Clock(s) PVDD DVDD_CORE CPVDD Vref AGND DVDD_IO Charge-Pump AVDDCAP+ CAP- V- DAC Right DAC DAC ADCL ADCR -97 to +30 dB In 0.5 dB steps -97 to +30 dB In 0.5 dB steps vol Digital Volume Digital Volume Automatic Level Control DVSS AVSS CPGND PVSS3 4 Vref AFILT1 AFILT2 HP_DET TEST VDD_XTAL VDD_PLL2 VDD_PLL1 VDD_PLSS VSS_PLSS VSS_XTAL +0/+10/+20/+30 dB BoostAGC -17 to +30dB in 0.75dB steps +0/+10/+20/+30 dB Boost -17 to +30dB in 0.75dB steps AGC SPKR - VDD_PLL3 *Digital Microphone Products

4 V1.2 1/12 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS422MX68 ACS422Mx68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC The digital filter and audio processing block processe s the data to provide volume control and numerous sound enhancement algorithms. Two high performance sigma-delta audio DACs convert the digital data into analog. The digital audio data is converted to oversampled bit streams using 24-bit digital interpolation filters, which then enters sigma-delta DACs, and become converted to high quality analog audio signals. To enhance the sound available from the small, low-power speakers typically found in a portable device, the ACS422Mx68 provides numerous audio enhancement capabilities. The ACS422Mx68 features dual, independent, pro- grammable left/right 6-band equalization, allowing the system designer to provide an advanced system equalizer to accommodate the specific speakers and enclosure design. A compressor/limiter features programmable attack and release thresholds, enabling the system designer to attenuat e loud noise excursions to avoid speaker artifacts, thus allowing the underlying content to be pl ayed at a louder volume without dist ortion. For compressed audio, a program- mable expander is available to help restore the dynamic range of the original content. A stereo depth enhancement algorithm allows common left/right content (e.g. dialog) to be attenuated separately from other content, providing a per- ceived depth separation between background and foregr ound audio. Psychoacoustic bass and treble enhancement algorithms achieve a rich, full tone even from originally compressed content, and even with speakers generally unable to play low-frequency sounds. 1.3. Audio Inputs On the analog input side, the device features multiple line-in/microphone inputs, which can be used for analog micro- phone, or line-in inputs. In addition, digital microphones are also supported. The device provides input gain control, separate volume controls, automatic leveling capability, and programmable microphone boost to smooth input record- ing. A programmable silence “floor” or “threshold” can be set to minimize background noise.

functions in the correct order.

6 BSTR RW 0 Analog in Boost Right

3 ADCL RW 0 ADC Left

2 ADCR RW 0 ADC Right

Table 1. Power Management Register 1

4 SPKL RW 0 LSPK Output Buffer

3 SPKR RW 0 RSPK Output Buffer

1 INSELR RW 0 Analog in Select Mux Right

Table 2. Power Management Register 2

setting the DIGENB bit (R25, bit 0). prevent the DACs and ADCs from re-starting correctly. Table 3. Power Management Register1 -- Master Clock Disable

Figure 2. Output Audio Processing 7:3 – R 0 Reserved for future use. Table 4. DC_COEF_SEL Register 3:2 RSVD R 0h Reserved for future use.

0 RSVD R 0 Reserved

Table 5. CONFIG0 Register

The signal volume can be controlled digitally, across a gain and attenuation range of -95.25dB to 0dB (0.375dB steps). cates mute; other values select the number of 0.375dB steps above -95.625dB for the volume level. grammable and a detection flag indicates when a stream of zero data has been detected.

7 ADCFade RW 1 1 = volume fades between old/new value

6 DACFade RW 1 1 = volume fades between old/new value

5 RSVD R 0 Reserved for future use.

3 ADCVOLU RW 0

2 DACVOLU RW 0

1 SPKVOLU RW 0

0 HPVOLU RW 0

headphone volume register written. Table 6. Volume Update Control Register 7 zerodet_flag R 0 1 = zero detect length exceeded. 6 RSVD R 0 Reserved for future use. 3 RSVD R 0 Reserved for future use. 1 RSVD R 0 Reserved for future use. 0 RSVD R 0 Reserved for future use. 7 zerodet_flag R 0 1 = zero detect length exceeded. Table 7. Gain Control Register

The signal volume can be controlled digitally, across a gain and attenuation range of -95.25dB to 0dB (0.375dB steps). cates mute; other values select the number of 0.375dB steps above -95.625dB for the volume level. the I2C address space of the device, access to the EQ ram occurs through the Control/Status registers. quency bands, gain, and filter characteristics (high, low, or bandpass). Figure 3. Prescaler & EQ Filters after the next write to the Right Input Volume register. Table 8. DAC Volume Control Registers

cients. (-2 coefficient  +2). Figure 4. 6-Tap IIR Equalizer Filter

• EQ Filter Enable Register
• DACCRAM Read Data (0x3D–LO, 0x3E –MID, 0x3F–HI), DACCRAM Write Data (0x3A–LO, 0x3B–MID, 0x3C–HI) Registers These two 24-bit registers provide the 24-bit data holding registers used when doing indire ct writes/reads to the DAC Register Address Bit Label Type Default Description R32 (20h) CONFIG1

7 EQ2_EN R/W 0 EQ bank 2 enable

following EQ stages are executed.

3 EQ1_EN R/W 0 EQ bank 1 enable

following EQ stages are executed. Table 9. CONFIG1 Register

• DACCRAM Address Register This 7-bit register provides the address to the internal RA M when doing indirect writes/r eads to the DAC Coefficient RAM.
• DACCRAM STATUS Register This control register provides the write/read enable when doing indirect writes/reads to the DAC Coefficient RAM. 3.4.3. Equalizer, Bass, Treble Coefficient & Equalizer Prescaler RAM The DAC Coefficient RAM is a single port 161x24 synchronous RAM. It is programmed indirectly through the Control Bus in the following manner: Register Address Bit Label Type Default Description R58 (3Ah) DACCRAM_WRITE_LO 7:0 DACCRWD[7:0] R/W 0 Low byte of a 24-bit data register, contains the values to be written to the DACCRAM. The address written will have been specified by the DACCRAM Address fields. R59 (3Bh) DACCRAM_WRITE_MID 7:0 DACCRWD[15:8] R/W 0 Middle byte of a 24-bit data register, contains the values to be written to the DACCRAM. The address written will have been specified by the DACCRAM Address fields. R60 (3Ch) DACCRAM_WRITE_HI 7:0 DACCRWD[23:16] R/W 0 High byte of a 24-bit data register, contains the values to be written to the DACCRAM. The address written will have been specified by the DACCRAM Address fields. R61 (3Dh) DACCRAM_READ_LO 7:0 DACCRRD[7:0] R 0 Low byte of a 24-bit data register, contains the contents of the most recent DACCRAM address read from the RAM. The address read will have been specified by the DACCRAM Address fields. R62 (3Eh) DACCRAM_READ_MID 7:0 DACCRRD[15:8] R 0 Middle byte of a 24-bit data register, contains the contents of the most recent DACCRAM address read from the RAM. The address read will have been specified by the DACCRAM Address fields. R63 (3Fh) DACCRAM_READ_HI 7:0 DACCRRD[23:16] R 0 High byte of a 24-bit data register, contains the contents of the most recent DACCRAM address read from the RAM. The address read will have been specified by the DACCRAM Address fields.

Table 10. DACCRAM Read/Write Registers Table 11. DACCRAM Address Register

7 DACCRAM_Busy R 0 1 = read/write to DACCRAM in progress, cleared by

Table 12. DACCRAM Status Register

1. Write target address to DACCRAM_ADDR register.
2. Write D7:0 to the DACCRAM_WRITE_LO register
3. Write D15:8 to the DA CCRAM_WRITE_MID register
4. Write D23:16 to the DACCRAM_WRITE_HI register
5. On successful receipt of the DACCRAM_WRITE_HI data, the part will automatically start a write

cycle. The DACCRAM_Busy bit will be set high to indicate that a write is in progress.

1. On completion of the internal write cycle, the DACCRAM_Busy bit will be 0 (when operating the
2. The bus cycle may be terminated by the host or steps 2-6 may be repeated for writes to consec-

Figure 5. DAC Coefficient RAM Write Sequence

1. Write target address to DACCRAM_ADDR register.( EQ data is pre-fetched for read even if we
2. Start (or repeat start) a write cycle to DACCRAM _READ_LO and after the second byte (register
3. Signal a repeat start and indicate a read operation
4. Read D7:0 (register address incremented after ack by host)
5. Read D15:8 (register address incremented after ack by host)
6. Read D23:16 (register address incremented and ne xt EQ location pre-fetched after ack by host)
7. The host stops the bus cycle
8. Start (or repeat start instead of stopping the bus cycle in step 7) a write cycle indicating

DACCRAM_RD_LO as the target address.

1. After the second byte is acknowledged, signal a repeated start.
2. Indicate a read operation
3. Read the DACCRAM_READ_LO regist er as described in step 4
4. Read the DACCRAM_READ_MID regi ster as described in step 5
5. Read the DACCRAM_READ_HI register as described in step 6

28 SCL cycles

1. Repeat steps 8-13 as desired

Figure 6. DAC Coefficient RAM Read Sequence

• DACCRAM EQ Addresess EQ 0 EQ1 Addr Channel 0 Coefficients Addr Channel 1 Coefficients Addr Channel 0 Coefficients Addr Channel 1 Coefficients 0x00 EQ_COEF_0F0_B0 0x20 EQ_COEF_1F0_B0 0x40 EQ_COEF_2F0_B0 0x60 EQ_COEF_3F0_B0 0x01 EQ_COEF_0F0_B1 0x21 EQ_COEF_1F0_B1 0x41 EQ_COEF_2F0_B1 0x61 EQ_COEF_3F0_B1 0x02 EQ_COEF_0F0_B2 0x22 EQ_COEF_1F0_B2 0x42 EQ_COEF_2F0_B2 0x62 EQ_COEF_3F0_B2 0x03 EQ_COEF_0F0_A1 0x23 EQ_COEF_1F0_A1 0x43 EQ_COEF_2F0_A1 0x63 EQ_COEF_3F0_A1 0x04 EQ_COEF_0F0_A2 0x24 EQ_COEF_1F0_A2 0x44 EQ_COEF_2F0_A2 0x64 EQ_COEF_3F0_A2 0x05 EQ_COEF_0F1_B0 0x25 EQ_COEF_1F1_B0 0x45 EQ_COEF_2F1_B0 0x65 EQ_COEF_3F1_B0 0x06 EQ_COEF_0F1_B1 0x26 EQ_COEF_1F1_B1 0x46 EQ_COEF_2F1_B1 0x66 EQ_COEF_3F1_B1 0x07 EQ_COEF_0F1_B2 0x27 EQ_COEF_1F1_B2 0x47 EQ_COEF_2F1_B2 0x67 EQ_COEF_3F1_B2 0x08 EQ_COEF_0F1_A1 0x28 EQ_COEF_1F1_A1 0x48 EQ_COEF_2F1_A1 0x68 EQ_COEF_3F1_A1 0x09 EQ_COEF_0F1_A2 0x29 EQ_COEF_1F1_A2 0x49 EQ_COEF_2F1_A2 0x69 EQ_COEF_3F1_A2 0x0A EQ_COEF_0F2_B0 0x2A EQ_COEF_1F2_B0 0x4A EQ_COEF_2F2_B0 0x6A EQ_COEF_3F2_B0 0x0B EQ_COEF_0F2_B1 0x2B EQ_COEF_1F2_B1 0x4B EQ_COEF_2F2_B1 0x6B EQ_COEF_3F2_B1 0x0C EQ_COEF_0F2_B2 0x2C EQ_COEF_1F2_B2 0x4C EQ_COEF_2F2_B2 0x6C EQ_COEF_3F2_B2 0x0D EQ_COEF_0F2_A1 0x2D EQ_COEF_1F2_A1 0x4D EQ_COEF_2F2_A1 0x6D EQ_COEF_3F2_A1 0x0E EQ_COEF_0F2_A2 0x2E EQ_COEF_1F2_A2 0x4E EQ_COEF_2F2_A2 0x6E EQ_COEF_3F2_A2 0x0F EQ_COEF_0F3_B0 0x2F EQ_COEF_1F3_B0 0x4F EQ_COEF_2F3_B0 0x6F EQ_COEF_3F3_B0 0x10 EQ_COEF_0F3_B1 0x30 EQ_COEF_1F3_B1 0x50 EQ_COEF_2F3_B1 0x70 EQ_COEF_3F3_B1 0x11 EQ_COEF_0F3_B2 0x31 EQ_COEF_1F3_B2 0x51 EQ_COEF_2F3_B2 0x71 EQ_COEF_3F3_B2 0x12 EQ_COEF_0F3_A1 0x32 EQ_COEF_1F3_A1 0x52 EQ_COEF_2F3_A1 0x72 EQ_COEF_3F3_A1 RA1 DA6AS DA0 RD7 Sr R AS RD0 AMRA7 1. DA: Device Address 6. A M: Acknowledge from master 2. RA: Register Address 7. N M: Not Acknowledge from master 3. EQ_A: EQ RAM Address 8. S: Start 4. RD: Register Data 9. S r: Repeated Start 5. AS: Acknowledge from slave 10. P: Stop SCL SDA DA[6:0], WS RA[7:0] RD[7:0] write EQ RAM Address RD[7:0] read EQ RAM Data Lo read EQ RAM Data Mid read EQ RAM Data Hi EQ_A ++; prefetch data DA[6:0], R Sr RD[7:0]RA[7:0] write EQ RAM Read Lo, truncate SP DA[6:0], W EQ RAM Data must be valid here Generic read operation EQ RAM read operation EQ_A updated; EQ RAM read req = 1

30 SCL cycles

Table 13. DACCRAM EQ Addresess

• DACCRAM Bass/Treble Addresses 0x13 EQ_COEF_0F3_A2 0x33 EQ_COEF_1F3_A2 0x53 EQ_COEF_2F3_A2 0x73 EQ_COEF_3F3_A2 0x14 EQ_COEF_0F4_B0 0x34 EQ_COEF_1F4_B0 0x54 EQ_COEF_2F4_B0 0x74 EQ_COEF_3F4_B0 0x15 EQ_COEF_0F4_B1 0x35 EQ_COEF_1F4_B1 0x55 EQ_COEF_2F4_B1 0x75 EQ_COEF_3F4_B1 0x16 EQ_COEF_0F4_B2 0x36 EQ_COEF_1F4_B2 0x56 EQ_COEF_2F4_B2 0x76 EQ_COEF_3F4_B2 0x17 EQ_COEF_0F4_A1 0x37 EQ_COEF_1F4_A1 0x57 EQ_COEF_2F4_A1 0x77 EQ_COEF_3F4_A1 0x18 EQ_COEF_0F4_A2 0x38 EQ_COEF_1F4_A2 0x58 EQ_COEF_2F4_A2 0x78 EQ_COEF_3F4_A2 0x19 EQ_COEF_0F5_B0 0x39 EQ_COEF_1F5_B0 0x59 EQ_COEF_2F5_B0 0x79 EQ_COEF_3F5_B0 0x1A EQ_COEF_0F5_B1 0x3A EQ_COEF_1F5_B1 0x5A EQ_COEF_2F5_B1 0x7A EQ_COEF_3F5_B1 0x1B EQ_COEF_0F5_B2 0x3B EQ_COEF_1F5_B2 0x5B EQ_COEF_2F5_B2 0x7B EQ_COEF_3F5_B2 0x1C EQ_COEF_0F5_A1 0x3C EQ_COEF_1F5_A1 0x5C EQ_COEF_2F5_A1 0x7C EQ_COEF_3F5_A1 0x1D EQ_COEF_0F5_A2 0x3D EQ_COEF_1F5_A2 0x5D EQ_COEF_2F5_A2 0x7D EQ_COEF_3F5_A2 0x1E - 0x3E - 0x5E - 0x7E - 0x1F EQ_PRESCALE0 0x3F EQ_PRESCALE1 0x5F EQ_PRESCALE2 0x7F EQ_PRESCALE3 Addr Bass Coefficients1 Addr Treble Coefficients Addr 3D Coefficients 0x80 BASS_COEF_EXT1_B0 0x97 TR EB_COEF_EXT1_B0 0xAE 3D_COEF 0x81 BASS_COEF_EXT1_B1 0x98 TR EB_COEF_EXT1_B1 0xAF 3D_MIX 0x82 BASS_COEF_EXT1_B2 0x 99 TREB_COEF_EXT1_B2 0x83 BASS_COEF_EXT1_A1 0x9A TREB_COEF_EXT1_A1 0x84 BASS_COEF_EXT1_A2 0x9B TREB_COEF_EXT1_A2 0x85 BASS_COEF_EXT2_B0 0x9C TREB_COEF_EXT2_B0 0x86 BASS_COEF_EXT2_B1 0x9D TREB_COEF_EXT2_B1 0x87 BASS_COEF_EXT2_B2 0x9E TREB_COEF_EXT2_B2 0x88 BASS_COEF_EXT2_A1 0x9F TREB_COEF_EXT2_A1 0x89 BASS_COEF_EXT2_A2 0xA0 TREB_COEF_EXT2_A2 0x8A BASS_COEF_NLF_M1 2 0xA1 TREB_COEF_NLF_M1 0x8B BASS_COEF_NLF_M2 0xA2 TREB_COEF_NLF_M2 0x8C BASS_COEF_LMT_B0 0xA3 TREB_COEF_LMT_B0 0x8D BASS_COEF_LMT_B1 0xA4 TREB_COEF_LMT_B1

Table 14. DACCRAM Bass/Treble Addresses

the max positive or negative value. than 0dB it will saturate at 0dB as the final processing step within the DSP module. speaker output which from the user listening perception it would “sound louder”. 1.All B0 coefficients are set to unity (400000h) by default. All others, including M1 and M2, are 0 by default. 1 integer bit, and 22 fraction bits.

1 Addr Treble

Figure 7. Gain Compressor, Output vs Input expansion function for either increasing dynamic range or noise gating. nal level is increased, the gain is decreased to maintain a specific output level. lar threshold, the expander will reduce the gain even further to extend the dynamic range of the material.

17 V1.2 1/12 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS422MX68 ACS422Mx68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.7.1. Configuration This compressor limiter provides the following configurable parameters.

• Compressor
• Threshold – The threshold ab ove which the compressor will reduce the dynamic range of the audio in the compression region.
• Ratio – The ratio between the input dynamic range and the output dynamic range. For example, a ratio of 3 will reduce an input dynamic range of 9db to 3db.
• Attack Time – The amount of time that changes in gain are smoothed over during the attack phase of the compressor.
• Release Time – The amount of time that changes in gain are smoothed over during the release phase of the compressor.
• Makeup gain – Used to increase the overall level of the compressed audio.
• Limiter
• Threshold – The threshold ab ove which the limiter will reduce the dynamic range of the audio in the compression region.
• Target – The limit of the output level (t ypically set to the same as threshold).
• Attack Time – The amount of time that changes in gain are smoothed over during the attack phase of the limiter.
• Release Time – The amount of time that changes in gain are smoothed over during the release phase of the limiter.
• Expander
• Threshold – The threshold below which the ex pander will increase the dynamic range of the audio.
• Ratio – The ratio between the input dynamic range and the output dynamic range of the audio in the expansion range. For example a ratio of 3 will take an input dynamic range of 9db and expand it to 27db.
• Attack Time – The amount of time that changes in gain are smoothed over during the attack phase of the expander
• Release Time - The amount of time that changes in gain are smoothed over during the release phase of the expander.
• Two level detection algorithms
• RMS – Use an RMS measurement for the level.
• Peak – Use a peak measurement for the level. 3.7.2. Controlling parameters In order to control this processing, there are a number of configurable parameters. The parameters and their ranges are:
• Compressor/limiter
• Threshold – -40db to 0db relative to full scale.
• Ratio – 1 to 20
• Attack Time – typically 0 to 500ms
• Release Time – typically 25ms to 2 seconds
• Makeup gain – 0 to 40db

• Expander
• Threshold – -30 to -60 dB
• Ratio – 1 to 6
• Attack Time – same as above
• Release Time – same as above.
• Two level detection algorithms
• R M S
• P e a k 3.7.3. Overview A basic block diagram of the compressor is shown below:

Figure 8. Compressor block diagram As this diagram shows, there are 3 primary components of the compressor.

1. Level Detector: The level detector, oddly enough, detects the level of the incoming signal.
2. Gain Calculation: The gain calculation block is responsible for taking the output of the level

• The gain calculation operates in 3 regions:
• Linear region – If the level is higher th an the expander threshold and lower than the compression threshold, then the gain is 1.0
• Compression region – When the level is higher than the compressor threshold, then the comp/limiter is in the compression region. The gain is a function of the compressor ratio and the signal level.
• Expansion region – When the signal is lower than the expansion threshold, the comp/limiter is in the expansion region. In this region, the gain is a function of the signal level and the expansion ratio.
• Compression region gain calculation: In the compression region, the gain calculation is: Atten(in db) = (1-1/ratio)(threshold(in db) – level(in db);
• For example,
• Ratio = 4:1 compression
• Threshold = -16db
• Level = -4 db Level Detector Gain Calc Attack/ release filter Peak or RMS Compare to Thresholds Calc Gain Lowpass filter Gains based on Attack and release Audio In Audio Out

19 V1.2 1/12 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS422MX68 ACS422Mx68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC The required attenuation is: 9db or a gain coefficient of 0.1259. Translating this calculation from log space to linear yields the formula: Gain =(level/threshold)1/ratio*(threshold/level)

• Expansion region gain calculation: In the ex pansion region, the attenuation calculation is: Atten(in db) = (1 - ratio)(threshold-level);
• For example,
• Ratio = 3:1
• Threshold = -40db
• Level = -44 db The resulting attenuation required is 8db or a gain value of 0.1585. The linear equation for calculating the gain is: Gain =(level/threshold) ratio*(threshold/level)
• State Transitions: In addition to calculati ng the new gain for the compressor, the gain calcu- lation block will also select the filter coefficient for the attack/release filter. The rules for selecting the coefficient are as follows: In the compression region:
• If the gain calculated is less than the last gain calculated (more compression is being applied), then the filter coefficient is the compressor attack.
• If the gain calculated is more than the last ga in calculated (less compression), the filter coef- ficient is the compressor release.
• In the expansion region:
• If the calculated gain is less than the last gain calculated (closing expander, the filter coeffi- cient is the expander attack.
• If the calculated gain is more than the last gain calculated, the filter coefficient is the expander release. In the linear region:
• Modify gain until a gain of 1.0 is obtained.
• If the last non-linear state was compression, use the compressor release.
• If the last non-linear state was ex pansion, use the expander attack. 3. Attack/Release filter: In order to prevent objectionable artifacts, the gain is smoothly ramped from the current value to the new value calculated by the gain calculation block. In the PC-based comp/limiter, this is achieved using a simple tracking lowpass filter to smooth out the abrupt tran- sitions. The calculation (using the coefficient (coeff) selected by the gain block) is: Filtered_gain = coeff*last_filtered_gain + (1.0 - coeff)*target_gain; This creates a exponential ramp from the current gain value to the new value.

• General compressor/limiter/expander control
• Compressor/Limiter/Expander make-up gain
• Compressor Threshold
• Compressor ratio register
• Compressor Attack Time Constant Register (Low) Register Address Bit Label Type Default Description R37 (25h) CLECTL 7:5 RSVD R 0h Reserved

4 Lvl_Mode RW 0

3 WindowSel RW 0

2 Exp_en RW 0 1 = enable expander

1 Limit_en RW 0 1 = enable limiter

0 Comp_en RW 0 1 = enable compressor

Table 15. CLECTL Register Table 16. MUGAIN Register Table 17. COMPTH Register Table 18. CMPRAT Register gain value during a compressor attack phase. Table 19. CATKTCL Register

• Compressor Attack Time Constant Register (High)
• Compressor Release Time Constant Register (Low)
• Compressor Release Time Constant Register (High)
• Limiter Threshold Register
• Limiter Target Register
• Limiter Attack Time Constant Register (Low )
• Limiter Attack Time Constant Register (High )
• Limiter Release Time Constant Register (Low ) Register Address Bit Label Type Default Description R42 (2Ah) CATKTCH 7:0 CATKTC[15:8] RW 00h High byte of the time constant used to ramp to a new gain value during a compressor attack phase.

Table 20. CATKTCH Register gain value during a compressor release phase. Table 21. CRELTCL Register gain value during a compressor release phase. Table 22. CRELTCH Register Table 23. LIMTH Register Table 24. LIMTGT Register gain value during a limiter attack phase. Table 25. LATKTCL Register gain value during a limiter attack phase. Table 26. LATKTCH Register gain value during a limiter release phase. Table 27. LRELTCL Register

• Limiter Release Time Co nstant Register (High) 3.7.5. Expander Registers
• Expander Threshold Register
• Expander Ratio Register
• Expander Attack Time Constant Register (Low)
• Expander Attack Time Constant Register (High)
• Expander Release Time Constant Register (Low)
• Expander Release Time Constant Register (High) Register Address Bit Label Type Default Description R50 (32h) LRELTCH 7:0 LRELTC[15:8] RW 00h High byte of the time constant used to ramp to a new gain value during a limiter release phase.

Table 28. LRELTCH Register Table 29. EXPTH Register Table 30. EXPRAT Register gain value during a expander attack phase. Table 31. XATKTCL Register gain value during a expander attack phase. Table 32. XATKTCH Register gain value during a expander release phase. Table 33. XRELTCL Register gain value during a expander release phase. Table 34. XRELTCH Register

grammable within a range. The input is prescaled (fixed) before summation to prevent saturation. The 3-D enhancement algorithm is a tried and true algorithm that uses two principles.

1. If the material common to the two channels is removed, then the speakers will sound more 3-D.
2. If the material for the opposite ch annel is presented to the current channel inverted, it will tend to

right ear that is leaking into the right ear. Figure 9. 3-D Channel Inversion

43 D E N R W 0 3D Enhancement Enable

3 TEEN RW 0 Treble Enhancement Enable

2 TNLFBYP RW 0 Treble Non-linear Function Bypass:

1 BEEN RW 0 Bass Enhancement Enable

0 BNLFBYP RW 0 Bass Non-linear Function Bypass:

Table 35. FX Control Register

tem below what it is actually capable of. Below is a diagram of the implementation of this algorithm. Figure 10. Bass Enhancement

1. Extract filter – This filter extracts the bass information that the speaker system can't reproduce.

This is a 4th order band pass filter with a typical bandwidth of 1.5 to 2 octaves.

1. NLF – This is a Nonlinear function that is used to generate the harmonics of the fundamentals in

the extracted audio. More on this function later.

1. Limit Filter – This filter will limit the amplitude of the harmonics generated to prevent the har-
2. Mixing – This structure allows mixing of the generated harmonics and the original material.
3. Cutoff Filter – This filter is used to remove all material below the cutoff frequency of the speaker

can't be reproduced. This is a 2nd order high pass filter. enhancement replaces these lost high frequencies. good predictor of audio between 10K-20K.

Figure 11. Treble Enhancement frequencies. These harmonics are then summed back into the original signal, providing a brighter sound. This algorithm has 4 components.

• Extract Filter– This filter is used to extract the treble between 4-8K. This is 2 2nd order high pass filters.
• Enhanced Treble Non-Linear Function– Generates high frequency components
• Limit Filter– This filter limits the harmonics generated by the NLF to prevent any significant aliasing. A second order filter is sufficient.
• Mixing Network – This simply sums the generated harmonic signals into the original signal. 3.12. Mute and De-Emphasis The ACS422Mx68 has a Soft Mute function, which is used to gradually attenuate the digital signal volume to zero. The gain returns to its previous setting if the soft mute is removed. At startup, the codec is muted by default; to enable audio play, the mute bit must be cleared to 0. After the equalization filters, de-emphasis may be performe d on the audio data to compensate for pre-emphasis that may be included in the audio stream. De-emphasis filteri ng is only available for 48kHz, 44.1kHz, and 32kHz sample rates. 3.13. Mono Operation and Phase Inversion Normal stereo operation converts left and right channel digi tal audio data to analog in separate DACs. However, it is also possible to have the same signal (left or right) appe ar on both analog output channels by disabling one channel; alternately, there is a mono-mix mode that mixes the two c hannels digitally before converting to analog using only one DAC. In this mode, the other DAC is switched off, and the resulting mixed stream signal can appear on both analog output channels. The DAC ou tput defaults to non-inverted. Setting DACPOLL and DACPOL R bits will invert the DAC output phase on the left and right channels. NLF Extract Filter Limit Filter

7 DACPOLR RW 0 Invert DAC Right signal

6 DACPOLL RW 0 Invert DAC Left signal

2 DEEMP RW 0

Table 36. CNVRTR1 Register

Figure 12. Interpolation and Filtering

remains at ground, so that no click noise is produced when muting or un-muting. Gains above 0dB run the risk of clipping large signals. ume fade function that smoothly changes volume from the current value to the target value. pins. They are intended to drive an 8 ohm or 4 ohm speaker pair.

7 RSVD R 0 Reserved

the next write to the Right Input Volume register. Table 37. HPVOL L/R Registers

• Feedback filters are applied to shape any noise. The filters move noise from audible frequencies to frequencies above the audio range.
• The PWM block converts the data streams to tri-state PWM signals and sends them to the power stages.
• Finally, the DDX TM Class D controller block adjusts the output volume to provide constant output power across supply voltage. The power stages boost the signals to higher levels, sufficient to drive speakers at a comfortable lis- tening level. 3.14.3.1. Constant Output Power Mode In normal operation the BTL amplifier is rated at 0. 5W (full scale digital with 6dB BTL gain) into an 8 However, when constant output power mode is enab led, the full scale output is held constant from 3.1V to 5.5V. The BTL amplifier in ACS422Mx68 will continuously adjust to power supply changes to ensure that the full scale output power remains constant. This is not an automatic level control. Rather, this func- tion prevents sudden volume changes when switching between battery and line power. Please note, when in this mode the amplifier efficiency may be reduced and decreases with higher supply volt- ages and lower target values. A simple 5-bit ADC is used to monitor PVDD. As PVDD raises or lowers, the analog circuit will send a 5-bit code to the digital section that will aver age and then calculate a gain adjustment. The BTL audio signal will be multiplied by this gain value (in addition to the user volume controls). Register Address Bit Label Type Default Description R2 (2h) SPKVOLL

after the next write to the Right Input Volume register. Table 38. SPKVOL L/R Registers

30 V1.2 1/12 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS422MX68 ACS422Mx68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC The user will select a target val ue for the circuit. The constant ou tput function will calculate a gain adjustment that will provide approximately the same full sc ale output voltage as provided when PVDD causes the same code value. So, if the tar get is 9 then a PVDD voltage of about 3.7V would generate a code value of 9 and a full scale output power of about 630mW into 8 ohms. If PVDD should rise to 4V, generating a code of 13, then th e constant output power circuit would reduce the gain by 0.75dB (4 codes * 0.1875dB) to keep the full scale output at the target level. The circuit may be configured to add gain, attenuation, or both to maintain the full-scale output level. If the needed adjustment falls outside of the range of the circuit (only attenuation is enabled and gain is needed, for example) then the circuit will apply as much correction as it is able. Through the use of gain, attenuation, and target values, different behaviors may be implemented:

• Attenuation only, target set to mimic a low supply voltage - Constant output level across bat- tery state with constant quality (THD/SNR)
• Attenuation only, target set to mimic a moderate supply voltage - Output limiting to an approximate power level. Level will decrease at lower supply voltages but won’t increase beyond a specific point.
• Gain only, target at or near max - Output will remain relatively constant but distortion will increase as PVDD is lowered. This mimics the behavior of common class-AB amplifiers.
• Gain and attenuation - Output remains at a le vel below the maximum possible at the highest supply voltage and above the theoretical full scale at minimum supply. Full scale PCM input clips when the supply voltage is low but won’t become too loud when the supply voltage is high. In addition to maintaining a constant output level, PVDD may be monitored for a large, sudden, change. If the High Delta function is enabled a nd PVDD changes more than 4 code steps since the last cycle, the output will be rapidly reduced then gradually increased to the target level. When using this circuit, please take note of the following:
• The full scale output power may be limited by the supply voltage.
• Full scale output power is affected by other gain controls in the output path including the EQ and compressor/limiter.
• The Constant Output Power function is intended to help maintain a constant output level, not an exact output level. The output level for a specific target may vary part to part. If limiting is required for safety or other reasons, be conservative and set the target well below the maxi- mum allowable level.
• Noise on the PVDD supply may cause erratic behavior. Use the recommended supply decoupling caps and verify that the power supply can support the peak currents demanded by a class-D amplifier.

sense circuit will be averaged for at least 200ms.

• Constant Output Power 1
• Constant Output Power 2 Register Address Bit Label Type Default Description R34 (22h) Constant Output Power 1

7 COPAtten RW 0

higher than the target value. higher than the target value.

5 HDeltaEn RW 0

reduced rapidly then slowly returned to the target level. 4:0 COPTarget[4:0] RW 8h 5-bit target fo r the Constant Output Power function. Table 39. Constant Output Power 1 Register

6 RSVD R 0 Reserved

Table 40. Constant Output Power 2 Register

• Constant Output Power 3
• Configuration Register
• PWM Control 0 Register Register Address Bit Label Type Default Description R137 (89h) Constant Output Power 3

7 HighDelta R 0

6 RSVD R 0

higher than the target value. Table 41. Constant Output Power 3 Register 3:2 RSVD R 0h Reserved for future use. Table 42. CONFIG0 Register Table 43. PWM0 Register

• PWM Control 1 Register
• PWM Control 2 Register
• PWM Control 3 Register Register Address Bit Label Type Default Description R67 (43h) PWM1

Dither position, where dither inserted after NS. Table 44. PWM1 Register inverting the output signal. Table 45. PWM2 Register Table 46. PWM3 Register

the default state of the device. outputs will be turned off when disabled. puts. Control bits determine the meaning and polarity of the input. In addition to enabling and disabling outputs, the EQ may also be controlled using the HP_DET pin. and the other EQ is active when the Speaker ou tput is active (independent HP and Speaker EQ). of the outputs are active (Speaker compensation and USER EQ) or other combinations are possible. registers. The HP_DET logic can only disable the EQ filters.

7 D2S RW 0 Analog in D2S AMP Enable

6 HPOutL RW 0 Left Headphone Output Enable

5 HPOutR RW 0 Right Headphone Output Enable

4 SPKOut RW 0 Speaker Output Enable

3 RSVD RW 0

2 RSVD RW 0

1 RSVD RW 0

0 VREF RW 1 Voltage reference

Note: A value of “1” indicates the output is enabled; a value of ‘0’ disables the output. Table 47. Power Management 2 Register

6 HPSWPOL RW 0

1 TSDEN RW 0

Table 48. Additional Control Register Table 49. Headphone Operation Table 50. EQ Operation

37 V1.2 1/12 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS422MX68 ACS422Mx68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.16. Thermal Shutdown To avoid overpowering and overheating the codec when the amplifier outputs are driving large currents, the ACS422Mx68 incorporates a thermal protection circuit. If enabled, and the device temp erature reaches approximately 150°C, the speaker and headphone amplifier outputs will be disabled. Once the device cools, the outputs will be auto- matically re-enabled. 3.16.1. Algorithm description: There are 2 trip points, “high” and “low”. High indicates a critical overheat requiring a reduction in vol- ume to avoid damage to the part. Low is set for a slightly lower temperature point, indicating that the current level is safe but that increased volume would result in a critical overheat condition. Normally, the overheat bits are polled every 8ms but may be polled at 4ms, 8ms, 16ms, or 32ms by adjusting the Poll value. Reductions in volume will be allowed to happen at the Poll rate. Increases in volume are programmable to happen every 1, 2, 4, or 8 Poll cycles and in steps of 0.75dB to 6dB. This allows a full scale volume increase in a range of 10s of milliseconds to 10s of seconds. When both overheat bits are 0, the volume is allo wed to increment by the IncStep size, unless the volume has already reached the maximum value allowed. Any subsequent increment will be held off until the programmed number of polling cycles have occurred. When the low overheat bit is 1 and the high overheat bit is 0, this indicates that the volume is cur- rently at a safe point but the temperature is higher than desired and incrementing the volume may cause severe overheating. The volume is held at the current value. When the high overheat bit is 1, damage could occur, so the volume se tting will be immediately reduced by the Decrement Step value. As the ov erheat bits are re-polled, this volume reduction will continue until the high overheat bit drops to 0 or the volume value reaches the minimum setting. If the high overheat bit remains 1 even at the minimum setting, th en the mute control bit will be asserted. If the high overheat bit persists even after mute, then the BTL amp will be powered down. 3.16.2. Thermal Trip Points. The high and low trip points can be adjusted to suit the needs of a particular system implementation. There is a “shift” value (TripShift) which sets the low trip point, and there is a “split” value (TripSplit) that sets how many degrees above the low trip point the high trip point is. By default: TripShift = 2 (140 degrees C) TripSplit = 0 (15 degrees C) Therefore: High Trip Point = 155°C. Low Trip Point = 140°C.

Figure 15. Temp sense volume adjustment algorithm

• Only the high overheat is used, the low overheat is ignored.
• Whenever polled, if the high over heat is 1, then the volume setting will immediately be set to 0h.
• Conversely, if the high overheat is 0, the volume setting will immediately be set to the MaxVol value.
• Both volume clear and volume set events occur at the polling rate. During this mode, the algorithm still possesses the ability to mute and then power down the BTL amp if the high overheat continues to be 1. This mode is disabled by default. Increment Ratio Count OverheatHL ==? IDLE TS Disabled Every “Poll” time (8ms default) 01 00 Increment Volume by IncStep Ratio met & Vol /= Max? No Yes Vol @ Min? Yes No Vol = Mute? Yes Decrement Volume by DecStep Volume = Mute BTL PWD No

the amplifier will disable itself again. The thermal shutdown circuit is enabled using the Additional Control Register, see Table 51. Table 51. Additional Control Register

7 TripHighStat R 0

6 TripLowStat R 0

Table 52. THERMTS Register

6 InstCutMode RW 0

Table 53. THERMTSPKR1 Register

7 ForcePwdStatus R 0

Table 54. THERMTSPKR2 Register

Figure 16. Input Audio Processing path to the stereo ADCs. Prior to the AD C, there is a multiplexor that allows th e system to select which input is in use. operate with the two channels mixed to mono either in the analog or digital domains. muted or the device is placed into standby mode.

powered off to conserve power. A differential input amplifie r may be selected as a mono source to either ADC input. This D2S amplifier can select either Input 1 or Input 2 using the DS bit. the left and right ADC independently. Table 55. Input Software Control Register

Table 56. INMODE Register

7 ADCPOLR RW 0

3 ADCMU RW 1 1 = Mute ADC

1 ADCHPDR RW 0 ADC High Pass Filter Disable (Right)

0 ADCHPDL RW 0 ADC High Pass Filter Disable (Right)

Table 57. CNVRTR0 Register Table 58. AIC2 Register

external resistor biasing network. The MICB control bit is used to enable the output. Figure 17. Mic Bias Control registers has no effect. Software can also mute the inputs in the analog domain. Table 59. Power Management 1 Register - Mic Bias Enable

4.4.1. Input PGA Software Control Register. and convert the raw multi-bit oversampled data from the ADC using the digital filter path illustrated below. Figure 18. ADC Filter Data path after the next write to the Right Input Volume register. after the next write to the Right Input Volume register. Table 60. INVOL L&R Registers

Figure 19. ADC Input processing inputs. Software can change the polarity of the output signal.

“00000000” indicates mute; other values describe the number of 0.375dB steps above -71.25dB. tal volume is immediately updated with the ADCVOL_L data when the Left ADC Digital Vo lume register is written.

7 ADCPOLR RW 0 0 = Right polarity not inverted

Table 61. CNVRTR0 Register Table 62. ADC HPF Enable

The ACS422Mx68 has an automatic level control to achieve recording volume across a range of input signal levels. The device uses a digital peak detector to monitor and adjusts the PGA gain to provide a signal level at the ADC input. Figure 20. ALC Operation target level. An upper limit for the PGA gain can also be imposed, using the MAXGAIN control bits. after the next write to the Right Input Volume register. Table 63. L/R ADC Digital Volume Registers

50 V1.2 1/12 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS422MX68 ACS422Mx68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Hold time specifies the delay between detecting a peak level being below target, and the PGA gain beginning to ramp up. It is specified as 2 n*2.67mS, enabling a range between 0mS and over 40s.; ramp-down begins immediately if the signal level is above the target. Decay (Gain Ramp-Up) Time is the time that it takes for the PGA to ramp up across 90% of its range. The time is 2 n*24mS. The time required for the recording level to return to its target value therefore depends on the decay time and on the gain adjustment required. Attack (Gain Ramp-Down) Time is the time that it takes for the PGA to ramp down across 90% of its range. Time is specified as 2n*24mS. The time required for the recording level to return to its target value depends on both the attack time and on the gain adjustment required. When operating in stereo, the peak detector takes the maximum of left and right channel peak val- ues, and both PGAs use the same gain setting, to preserve the stereo image. If the ALC function is only enabled on one channel, only one PGA is controlled by the ALC mechanism, and the other channel runs independently using the PGA gain set through the control registers. If one ADC channel is unused, the peak detector will ignore that channel. The ALC function can operate when the two ADC outputs are mixed to mono in the digital domain or in the analog domain.

2 ALC MODE RW 0 0: ALC Mode 1: Limiter mode

Note: ensure that LINVOL and RINVOL settings (reg. 0 and 1) are the same before entering this mode. where each value represents a 6dB step. ALC hold time before gain is increased. Table 64. ALC Control Registers

The ADC output can be muted. Alternatively, the PGA gain can be held . always operates on the same channel(s) as the ALC. Line Input 3 may be an analog line (mic) or digital microphone input depending on the part option. using a control bit and the left time slot is copied to the ADC left and right inputs. the ADC base rate for 32KHz, and 80 times the base rate for 44.1KHz and 48KHz base rates. Table 65. NGATE Register

The two DMIC data inputs are shown connected to the A DCs through the same multiplexors as the analog ports. an audio driver will be able to configure and use the digital microphones exactly like an analog microphone. Table 66. DMIC Clock

Figure 21. Single Digital Microphone (data is ported to both left and right channels)

0 N/A No Digital Microphones

1 Single Edge

“Left” D-mic data is used for ADC left and right channels.

2 Double Edge

alternative clock edge (multiplexed output) capability. Table 67. Valid Digital Mic Configurations Single “Left” Microphone, DMIC input set to mono input mode. Single Microphone not supporting multiplexed output.

Figure 22. Stereo Digital Microphone Configuration

7 DMicEn RW 0

Table 68. DMICCTL Register

the LSB are then transmitted in order. Figure 27. I2S Justified Audio Interface (assuming n-bit word length)

6 BCLKINV RW 0

Table 69. AIC1 Register

1 BCLK1 BCLK

low with an internal pull-down resistor unless that resistor is disabled.

1. Both the DAC and ADC must be pr ogrammed for the same sample rate
2. Both the DAC and ADC must be programmed for the same number of clocks per frame
3. When in slave mode, the DAC and ADC data must be aligned relative to the provided BCLK and
4. The DAC and ADC must be powered down when changing the BLRCM mode
5. If sharing the BCLK from one path (DAC or ADC) and the LRCLK from the other path (ADC or

Table 70. AIC2 Register

all converters before changing modes. 2.DAC (playback path) is off when HPL, HPR, SPKL, and SPKR power states are off. Table 71. Bit Clock and LR Clock Mode Selection

Table 72. ADC Data Output pin state

5 ADOPDD RW 0 ADCDOUT Pull-Down Disable

3 ABCPDD RW 0

2 DDIPDD RW 0

Table 73. AIC3 Register

The BCM mode bit clock generator produces 16, 20, or 32 bit cycles per sample. Figure 28. Bit Clock mode ates using a standard 2-wire interface, as a slave device only. ACS422Mx68 acknowledges again by pulling SDA low. or stop condition is detected out of sequence, the device returns to the idle condition. Table 74. Master Mode BCLK Frequency Control Register

• Device Identification Registers
• Device Revision Register Note: Contact IDT for device and revision information. 5.9.5.2. Register Reset The ACS422Mx68 registers may be reset to their de fault values using the reset register. Writing a special, non-zero va lue to this register causes all other registers to assume their default states. Device status bits will not necessarily change their values depending on the state of the device. Register Address Bit Label Type Default Description R126 (7Eh) DEVIDH 7:0 DID[15:8] R xxh 16-bit device identification number. The ACS422Mx68 has programmable clocking that will drive different device IDs for each configuration. Contact IDT. R125 (7Dh) DEVIDL 7:0 DID[7:0] R xxh

Table 76. DEVID H&L Registers 7:4 MAJ[3:0] R xh 4-bit major revision number. Contact IDT. 3:0 MNR[3:0] R xh 4-bit minor revision number. Contact IDT. Table 77. REVID Register Table 78. RESET Register

• 122.880 MHz (2560 x 48 KHz)
• 112.896 (2560 x 44.1 KHz) It is important that the crystal oscillator and needed PLLs remain on until all audio functions, includ- ing jack detection, are disabled. 6.2. ACLK Clocking and Sample Rates The ACS422Mx68 utilizes internal PLLs to generate the audio master clock (ACLK) at 56.448MHz (22.5792MHz *2.5) do not need to run at the same sample rate unless they are sharing BCLK and LRCLK pins. Disable the appropriate converters before programming the mode or rate, especially if the DAC and ADC are programmed to share the same BCLK and LRCLK. After changing rate, a delay of up to 5mS may be needed for the part to properly lock PLLs, flush fil- ters, etc. Register Address Bit Label Type Default Description R23 (17h) ADC Sample Rate Control (ADCSR) 7:6 ABCM[1:0] RW 00 ADC Bit Clock Mode (for data interface ADCBCLK generation in master mode) 00 = Auto 01 = 32x fs 10 = 40x fs 11 = 64x fs 5R S V D R 0 R e s e r v e d 4:3 ABR[1:0] RW 10 ADC Base Rate 00 = 32KHz 01 = 44.1KHz 10 = 48KHz 11 = Reserved 2:0 ABM[2:0] RW 010 ADC Base Rate Multiplier 000 = 0.25x 001 = 0.50x 010 = 1x 011 = 2x 100-111 = Reserved

Table 79. ADCSR Register

Table 80. DACSR Register

40.96 MHz

011 Reserved

61.44 MHz

Table 81. ACLK and Sample Rates

3:2 RSVD R 0h Reserved for future use. when needed (COP, UVLO enabled). Table 82. CONFIG0 Register

00 NA Reserved

Table 83. SDM Rates

recommended operating temperature range. Table 84. Electrical Specification: Maximum Ratings Table 85. Recommended Operating Conditions

Table 86. Device Characteristics

2.1 Vrms

0.5 W(ave)

1 W(ave)

1.Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 kHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio). 2.THD+N ratio as defined in AES17 and outlined in AES6id,non-weighted, swept over 20 Hz to 20 kHz bandwidth.

Table 88. Low power mode power consumption include PLL/clock buffer section. not include PLL/clock buffer section. load but not PLL/clock buffer section. include PLL/clock buffer section. Table 87. Typical Power Consumption include PLL/clock buffer section. include PLL/clock buffer section. include PLL/clock buffer section.

Table 89. Register Map

• Registers not described in this map should be considered “reserved”.
• Numerous portions of the register map are compat ible with popular codecs from other vendors. R52 (34h) EXPRAT Expander Ratio EXPRAT2 EXPRAT1 EXPRAT0 00h R53 (35h) XATKTCL Expander Attack time constant Low XATKTC7 XATKTC6 XATKTC5 XATKTC4 XATKTC3 XATKTC2 XATKTC1 XATKTC0 00h R54 (36h) XATKTCH Expander Attack time constant High XATKTC15 XATKTC14 XATKTC13 XATKTC12 XA TKTC11 XATKTC10 XATKTC9 XATKTC8 00h R55 (37h) XRELTCL Expander Release time constant Low XRELTC7 XRELTC6 XRELTC5 XRELTC4 XRELTC3 XRELTC2 XRELTC1 XRELTC0 00h R56 (38h) XRELTCH Expander Release time constant High XRELTC15 XRELTC14 XRELTC13 XRELTC12 XRELTC11 XRELTC10 XRELTC9 XRELTC8 00h R57 (39h) FXCTL Effects Control 3DEN TEEN TNLFBYP BEEN BNLFBYP 00h R58 (3Ah) DACCRWRL DACCRAM_WRITE_LO DACCRWD[7:0] 00h R59 (3Bh) DACCRWRM DACCRAM_WRITE_MID DACCRWD[15:8] 00h R60 (3Ch) DACCRWRH DACCRAM_WRITE_HI DACCRWD[23:16] 00h R61 (3Dh) DACCRRDL DACCRAM_READ_LO DACCRRD[7:0] 00h R62 (3Eh) DACCRRDM DACCRRAM_READ_MID DACCRRD[15:8] 00h R63 (3Fh) DACCRRDH DACCRRAM_READ_HI DACCRRD[23:16] 00h R64 (40h) DACCRADDR DACCRAM_ADDR DACCRADD[7:0] 00h R65 (41h) DCOFSEL DC_COEF_SEL dc_coef_sel[2:0] 05h R66-123 RSVD RSVD NA R124(7Ch) DEVADR I2C Device Address ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 D2h R125(7Dh) DEVIDL Device IDLow DID7 DI D6 DID5 DID4 DID3 DID2 DID1 DID0 xxh R126(7Eh) DEVIDH Device ID High DID15 DID14 DID13 DID12 DID11 DID10 DID9 DID8 xxh 1 R127(7Fh) REVID Device Revision MAJ3 MAJ2 MAJ1 MAJ0 MNR3 MNR2 MNR1 MNR0 xxh 2 R128(80h) RESET Reset Writing 0x85 to this register resets all registers to their default state 00h R129-R135 (81h - 87h) Reserved RSVD NA R136(88h) THERMSPKR2 Speaker Thermal Algorithm Status ForcePwd Status VolStatus[6:0] 08h R137-R255 (88h-FFh) Reserved RSVD NA 1. Device ID is dependent upon clock programming. 2. For device revision information, please contact IDT. Register (D15:9) Name Remarks Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0] Default

Figure 33. ACS422MA68 Pinout

Figure 34. ACS422MD68 Pinout

Table 90. Power Pins Table 91. Reference Pins

Table 92. Analog Input Pins Table 93. Analog Output Pins Table 94. Data and Control Pins

Table 95. PLL and NC Pins

Figure 35. Package Outline Note: IDT’s package thicknesses are <2.5mm and <350 mm3, so 260 applies in every case. temperature (this means Peak reflow temperature +0 oC. For example 260 oC+0 oC) at the rated MSL level. Table 96. Reflow Temperatures

81 V1.2 1/12 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS422MX68 ACS422Mx68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 11. APPLICATION INFORMATION For application information, please see refere nce designs and applicat ion notes available on www.idt.com. 12.ORDERING INFORMATION yy = silicon revision, contact IDT for current part number. 13.DISCLAIMER While the information presented herein has been checked for both accuracy and reliability, manufac- turer assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal co mmercial applications. Any other applications, such as those requiring extended temper ature range, high relia bility, or other extr aordinary environmental requirements, are not recommended without additional processing by manufacturer. Manufacturer reserves the right to change any circuitry or spec ifications without notice. Manufacturer does not authorize or warrant any product for use in life support devices or critical medical instruments. ACS422MA68TAGyyX TLA package, Analog Microphone ACS422MD68TAGyyX TLA package, Digital Microphone

LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC

6024 Silver Creek Valley Road

San Jose, California 95138 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications de- scribed herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and perfor- mance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT p roduct can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, in- cluding protected names, logos and designs, are the property of IDT or their respective third party owners. 14.DOCUMENT REVISION HISTORY Revision Date Description of Change

0.5 June 2011 initial release

1.0 July 2011

Removed Preliminary and Confidential status from datasheet. Updated TAG/TLA package diagram. Removed applications section, see reference design and application notes on www.idt.com, updates to the electrical characteristics. Compressor/limiter configuration section separated. Updated audio output references to include 2W at 4ohms. Added DDX(TM) name and logo.

1.1 November 2011 Changed 40mW to 35mW on headphone output and changed Power Supply Rejection Ration

maximum from 5.5 V to 5.25 V. 1.2 January 2012 Corrected the I/O type for the Analog output pins. Corrected the pin location in Analog output pin table for the BTL outputs.