ACS374MS RENESAS | Alldatasheet
Document overview
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- PDF pages: 8
Technical content
Features
- 1.25 Micron Radiation Hardened SOS CMOS
- Total Dose 300K RAD (Si)
- Single Event Upset (SEU) Immunity <1 x 10-10 Errors/Bit-Day (Typ)
- SEU LET Threshold >80 MEV-cm2/mg
- Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse
- Latch-Up Free Under Any Conditions
- Military Temperature Range: -55 oC to +125oC
- Significant Power Reduction Compared to ALSTTL Logic
- DC Operating Voltage Range: 4.5V to 5.5V
- Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min
- Input Current 1A at VOL, VOH
Description
The Intersil ACS374MS is a radiation hardened octal D-type flip-flop with three-state output s. The eight edge-triggered fl ip- flops enter data into their registers on the low to high transi tion of clock (CP). The Output Enable (OEN) controls the three-state outputs and is independent of the register operation. When the OEN is high, the outputs will be in the high impedance state. The ACS374MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the radiation hardened, high-speed, CMOS/SOS Logic Family. Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T20, LEAD FINISH C TOP VIEW
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR CDFP4-F20, LEAD FINISH C TOP VIEW
Ordering Information
Truth Table Functional Diagram 1OE GND VCC CP 12 0 OE GND VCC CP PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE ACS374DMSR -55 oC to +125oC Intersil Class S Equivalent 20 Lead SBDIP ACS374KMSR -55 oC to +125oC Intersil Class S Equivalent 20 Lead Ceramic Flatpack ACS374D/Sample +25 oC Sample 20 Lead SBDIP ACS374K/Sample +25 oC Sample 20 Lead Ceramic Flatpack ACS374HMSR +25 oCD i e D i e INPUTS OUTPUTS OE CP Dn Qn LH H LL L LX X Q 0 HX X Z H = High Level L = Low Level X = Immaterial Z = High Imped- ance = Transition from Low to High Level Q0 = the level of Q before the indicated input conditions were established DQ CP D CP Q OE FF COMMON CONTROLS OE
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under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
- All voltages referenced to device GND.
- Force/measure functions may be interchanged.
- For functional tests, VO 4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
- All voltages referenced to device GND.
- AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
- The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
- All voltages referenced to device GND.
- For functional tests, VO 4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”.
TABLE 5. DELTA PARAMETERS (+25oC)
- All delta calculations are referenced to 0 hour readings or pre-life readings.
TABLE 6. APPLICABLE SUBGROUPS
- Alternate Group A testing may be exercised in accordance with MIL-STD-883, Method 5005.
TABLE 7. TOTAL DOSE IRRADIATION
- Except FN test which will be performed 100% Go/No-Go.
TABLE 8. BURN-IN TEST CONNECTIONS (+125
- Each pin except VCC and GND will have a series resistor of 500 5%.
TABLE 9. IRRADIATION TEST CONNECTIONS (TA = +25oC, 5oC)
- Each pin except VCC and GND will have a series resistor of 47k 5%. Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures.
FN3997 Rev 0.00 Page 6 of 8 April 1995 Propagation Delay Timing Diagram and Load Circuit Intersil - Space Products MS Screening Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Nondestructive Bond Pull Method 2023 100% Internal Visual Inspection Method 2010 100% Temperature Cycling Method 1010 Condition C (-65o to +150oC) 100% Constant Acceleration 100% PIND Testing 100% External Visual Inspection 100% Serialization 100% Initial Electrical Test 100% Static Burn-In 1 Method 1015, 24 Hours at +125 oC Min 100% Interim Electrical Test 1 (Note 1) 100% Static Burn-In 2 Method 1015, 24 Hours at +125oC Min 100% Interim Electrical Test 2 (Note 1) 100% Dynamic Burn-In Method 1015, 240 Hours at +125oC or 180 Hours at +135oC 100% Interim Electrical Test 3 (Note 1) 100% Final Electrical Test 100% Fine and Gross Seal Method 1014 100% Radiographics Method 2012 (2 Views) 100% External Visual Method 2009 Group A (All Tests) Method 5005 (Class S) Group B (Optional) Method 5005 (Class S) (Note 2) Group D (Optional) Method 5005 (Class S) (Note 2) CSI and/or GSI (Optional) (Note 2) Data Package Generation (Note 3) NOTES: 1. Failures from interim electrical tests 1 and 2 are combined for determining PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures com- bined, PDA = 3% for subgroup 7 failures). Interim electrical te sts 3 PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures co mbined, PDA = 3% for subgroup 7 failures). 2. These steps are optional, and should be listed on the purchase order if required. 3. Data Package Contents: Cover Sheet (P .O. Number, Customer Number, Lot Date Code, Intersil Number, Lot Number, Quantity). Certificate of Conformance (as found on shipper). Lot Serial Number Sheet (Good Unit(s) Serial Number and Lot Number). Variables Data (All Read, Record, and delta operations). Group A Attributes Data Summary. Wafer Lot Acceptance Report (Method 5007) to include reproductions of SEM photos. NOTE: SEM photos to include percent of step coverage. X-Ray Report and Film, including penetrometer measurements. GAMMA Radiation Report with initial shipment of devices from the same wafer lot; containing a Cover Page, Disposition, RAD Dose, Lot Number, Test Package, Spec Number(s), Test Equipment, etc. Irradiation Read and Record data will be on file at Intersil. VS INPUT OUTPUT VIH VSS VOH VOL TPLH TPHL VS AC VOLTAGE LEVELS PARAMETER ACS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VIL 0 V GND 0 V DUT TEST CL RL POINT 50pF 500
FN3997 Rev 0.00 Page 7 of 8 April 1995 Pulse Width, Setup, Hold Timing Diagram Positive Edge Trigger and AC Load Circuit Three-State High Timing Diagram and Load Circuit Three-State Low Timing Diagram and Load Circuit INPUT VIL VIL VS VIH INPUT CP VIH TH = HOLD TIME TSU = SETUP TIME TW = PULSE WIDTH TW TSU TH TW VS DUT TEST CL RL POINT 50pF 500 PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS PARAMETER ACS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VIL 0 V GND 0 V TPHZ INPUTVS TPZH VT VIH VSS VOH VOZ OUTPUT VW DUT TEST CL RL POINT 50pF 500 PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS PARAMETER ACS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VT 2.25 V VW 3.60 V GND 0 V TPLZ INPUTVS TPZL VT VIH VSS VOZ VOL OUTPUT VW CL RL DUT TEST POINT VCC 500 50pF PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS PARAMETER ACS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VT 2.25 V VW 0.90 V GND 0 V
FN3997 Rev 0.00 Page 8 of 8 April 1995 ACS374MS Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 1999. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Die Characteristics DIE DIMENSIONS: 102 mils x 102 mils 2,600mm x 2,600mm METALLIZATION: Type: AlSiCu Metal 1 Thickness: 6.75k Å (Min), 8.25kÅ (Max) Metal 2 Thickness: 9kÅ (Min), 11kÅ (Max) GLASSIVATION: Type: SiO2 Thickness: 8kÅ 1kÅ DIE ATTACH: Material: Silver Glass or JM 7000 after 7/1/95 WORST CASE CURRENT DENSITY: < 2.0 x 105A/cm2 BOND PAD SIZE: > 4.3 mils x 4.3 mils > 110m x 110m Metallization Mask Layout ACS374MS D1 (4) Q1 (5) Q2 (6) D2 (7) (8) (9) (10) GND (11) CP (12) (13) (18) (17) D6 (16) Q6 (15) Q5 (14) D5 (2) (3) OE (1) VCC (20) (19) NC NCNC NC