ACS373MS INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • 1.25 Micron Radiation Hardened SOS CMOS
  • Total Dose 300K RAD (Si)
  • Single Event Upset (SEU) Immunity <1 x 10 -10 Errors/Bit-Day (Typ)
  • SEU LET Threshold >80 MEV-cm2/mg
  • Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse
  • Latch-Up Free Under Any Conditions
  • Military Temperature Range: -55 oC to +125oC
  • Significant Power Reduction Compared to ALSTTL Logic
  • DC Operating Voltage Range: 4.5V to 5.5V
  • Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min
  • Input Current≤1µA at VOL, VOH

Description

The Intersil ACS373MS is a radiation hardened octal transparent latch with three-state outputs. The outputs are transparent to the inputs when the latch enable ( LE) is high. When theLE goes low, the data is latched. When the Output Enable (OE) is high, the outputs are in the high impedance state. The latch operation is independent of the state of the output enable. The ACS373MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the radiation hardened, high-speed, CMOS/SOS Logic Family.

under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. All voltages referenced to device GND.
  2. Force/measure functions may be interchanged.
  3. For functional tests, VO≥4.0V is recognized as a logic “1”, and VO≤0.5V is recognized as a logic “0”.

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. All voltages referenced to device GND.
  2. AC measurements assume RL = 500Ω , CL = 50pF, Input TR = TF = 3ns.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly

tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. All voltages referenced to device GND.
  2. For functional tests, VO≥4.0V is recognized as a logic “1”, and VO≤0.5V is recognized as a logic “0”.

TABLE 5. DELTA PARAMETERS (+25

  1. All delta calculations are referenced to 0 hour readings or pre-life readings.

TABLE 6. APPLICABLE SUBGROUPS

  1. Alternate Group A testing may be exercised in accordance with MIL-STD-883, Method 5005.

TABLE 7. TOTAL DOSE IRRADIATION

  1. Except FN test which will be performed 100% Go/No-Go.

TABLE 8. BURN-IN TEST CONNECTIONS (+125

  1. Each pin except VCC and GND will have a series resistor of 500Ω± 5% for static burn-in.

TABLE 9. IRRADIATION TEST CONNECTIONS (TA = +25 oC, ±5oC)

  1. Each pin except VCC and GND will have a series resistor of 47kΩ± 5%. Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures.

Specifications ACS373MS Spec Number 518799 Propagation Delay Timing Diagram and Load Circuit Intersil - Space Products MS Screening Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) Radiation Verification (Each Wafer) Method 1019,

4 Samples/Wafer, 0 Rejects

100% Nondestructive Bond Pull Method 2023 100% Internal Visual Inspection Method 2010 100% Temperature Cycling Method 1010 Condition C (-65 o to +150oC) 100% Constant Acceleration 100% PIND Testing 100% External Visual Inspection 100% Serialization 100% Initial Electrical Test 100% Static Burn-In 1 Method 1015, 24 Hours at +125 oC Min 100% Interim Electrical Test 1 (Note 1) 100% Static Burn-In 2 Method 1015, 24 Hours at +125oC Min 100% Interim Electrical Test 2 (Note 1) 100% Dynamic Burn-In Method 1015, 240 Hours at +125 oC or 180 Hours at +135oC 100% Interim Electrical Test 3 (Note 1) 100% Final Electrical Test 100% Fine and Gross Seal Method 1014 100% Radiographics Method 2012 (2 Views) 100% External Visual Method 2009 Group A (All Tests) Method 5005 (Class S) Group B (Optional) Method 5005 (Class S) (Note 2) Group D (Optional) Method 5005 (Class S) (Note 2) CSI and/or GSI (Optional) (Note 2) Data Package Generation (Note 3) NOTES: 1. Failures from interim electrical tests 1 and 2 are combined for determining PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures com- bined, PDA = 3% for subgroup 7 failures). Interim electrical tests 3 PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures combined, PDA = 3% for subgroup 7 failures). 2. These steps are optional, and should be listed on the purchase order if required. 3. Data Package Contents: Cover Sheet (P.O. Number, Customer Number, Lot Date Code, Intersil Number, Lot Number, Quantity). Certificate of Conformance (as found on shipper). Lot Serial Number Sheet (Good Unit(s) Serial Number and Lot Number). Variables Data (All Read, Record, and delta operations). Group A Attributes Data Summary. Wafer Lot Acceptance Report (Method 5007) to include reproductions of SEM photos. NOTE: SEM photos to include percent of step coverage. X-Ray Report and Film, including penetrometer measurements. GAMMA Radiation Report with initial shipment of devices from the same wafer lot; containing a Cover Page, Disposition, RAD Dose, Lot Number, Test Package, Spec Number(s), Test Equipment, etc. Irradiation Read and Record data will be on file at Intersil. VS INPUT OUTPUT VIH VSS VOH VOL TPLH TPHL VS AC VOLTAGE LEVELS PARAMETER ACS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VIL 0 V GND 0 V DUT TEST CL RL POINT 50pF 500Ω

Specifications ACS373MS Spec Number 518799 Pulse Width, Setup, Hold Timing Diagram Positive Edge Trigger and AC Load Circuit Three-State High Timing Diagram and Load Circuit Three-State Low Timing Diagram and Load Circuit INPUT VIL VIL VS VIH INPUT CP VIH TH = HOLD TIME TSU = SETUP TIME TW = PULSE WIDTH TW TSU TH TW VS DUT TEST CL RL POINT 50pF 500Ω PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS PARAMETER ACS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VIL 0 V GND 0 V TPHZ INPUTVS TPZH VT VIH VSS VOH VOZ OUTPUT VW DUT TEST CL RL POINT 50pF 500Ω PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS PARAMETER ACS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VT 2.25 V VW 3.60 V GND 0 V TPLZ INPUTVS TPZL VT VIH VSS VOZ VOL OUTPUT VW CL RL DUT TEST POINT VCC 500Ω 50pF PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS PARAMETER ACS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VT 2.25 V VW 0.90 V GND 0 V

D1 (4) Q1 (5) Q2 (6) D2 (7) (8) (9) (10) GND (11) CP (12) (13) (18) (17) D6 (16) Q6 (15) Q5 (14) D5 (2) (3) OE (1) VCC (20) (19) NC NCNC NC Die Characteristics DIE DIMENSIONS: 102 mils x 102 mils 2,600mm x 2,600mm METALLIZATION: Type: AlSiCu Metal 1 Thickness: 6.75k Å (Min), 8.25kÅ (Max) Metal 2 Thickness: 9kÅ (Min), 11kÅ (Max) GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ DIE ATTACH: Material: Silver Glass or JM 7000 after 7/1/95 WORST CASE CURRENT DENSITY: < 2.0 x 105A/cm2 BOND PAD SIZE: > 4.3 mils x 4.3 mils > 110µm x 110µm

D20.3MIL-STD-1835 CDIP2-T20 (D-8, CONFIGURATION C)

20 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 E 0.220 0.310 5.59 7.87 - e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.070 0.38 1.78 5 S1 0.005 - 0.13 - 6 S2 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2 N2 0 2 0 8 Rev. 0 4/94 NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE S S -D--A- -C- eA -B- aaa C A - BM DS Sccc C A - BM DS S D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 M A Ceramic Dual-In-Line Metal Seal Packages (SBDIP)

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 ACS373MS Spec Number 518799 -D- -C-

0.004 H A - BM DS S

-A- -B-

0.036 H A - BM DS S

e E A Q L D A SEATING AND LE2 E3 E3 BASE PLANE -H- b C M (c) (b) SECTION A-A BASE LEAD FINISH METAL PIN NO. 1 ID AREA A M K20.A MIL-STD-1835 CDFP4-F20 (F-9A, CONFIGURATION B)

20 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

A 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - D - 0.540 - 13.72 3 E 0.245 0.300 6.22 7.62 - E1 - 0.330 - 8.38 3 E3 0.030 - 0.76 - 7 e 0.050 BSC 1.27 BSC - k 0.008 0.015 0.20 0.38 2 L 0.250 0.370 6.35 9.40 - Q 0.026 0.045 0.66 1.14 8 S1 0.00 - 0.00 - 6 N2 0 2 0- Rev. 0 5/18/94 Ceramic Metal Seal Flatpack Packages (Flatpack) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the lim- its of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum lim- its of lead dimensions b and c or M shall be measured at the cen- troid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric mate- rials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.