ACS32201

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LOW-POWER, HIGH-FIDELITY CLASS-D AMPLIFIER ACS32201 IDT CONFIDENTIAL 1 V0.6 07/11 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS32201 The ACS32201 is a low-power, high-fidelity Class-D ampli- fier targeted at portable applications such as tablet com- puters, personal navigation devices, portable projectors and speaker docks. Built-in audio processing and a DDX TM Class-D digital speaker amplifier provide high fidel- ity audio for portable systems with enriched “audio pres- ence”. TARGET APPLICATIONS

Tablet Computers
Portable Navigation Devices
Personal Media Players
Portable Projectors
Speaker Docks

FEATURES

Filterless Stereo DDX TM Class D Speaker Driver
1W/channel (8 Ω) or 2W/channel (4Ω), 0.05% THD+N typical
Tri-state DDX TM Class D achieves low EMI and high efficiency
>80% efficiency at 1W
Spread spectrum support for reduced EMI output power mode
Anti-Pop circuitry
Built in audio controls and processing
3D stereo enhancement
Dual (cascaded) stereo 6-ba nd parametric equalizers
Programmable Compressor/Limiter/Expander
Psychoacoustic Bass and Treble enhancement processing
I 2 S d a t a i n t e r f a c e
Low power with built in power management
Very low standby and no-signal power consumption
1.8V digital / 1.7V analog supply for low power
2-wire (I 2C compatible) control interface
Package Options
68-pin dual row 6x6 mm TLA package
36-pin single row 5x5 mm HLA package PRELIMINARY DDXTM and the DDX logo are trademarks of Apogee Technology.

nel filterless stereo class D amplifier. Figure 1. ACS32201 Block Diagram

functions in the correct order. setting the DIGENB bit (R25, bit 0). Table 1. Power Management Register 1

4 SPKL RW 0 LSPK Output Buffer

3 SPKR RW 0 RSPK Output Buffer

Table 2. Power Management Register 2 Table 3. Power Management Register1 -- Master Clock Disable

Figure 2. Output Audio Processing 7:3 – R 0 Reserved for future use. Table 4. DC_COEF_SEL Register

0 RSVD R 0 Reserved

Table 5. CONFIG0 Register

2 GAIN

The signal volume can be controlled digitally, across a gain and attenuation range of -95.25dB to 0dB (0.375dB steps). cates mute; other values select the number of 0.375dB steps above -95.625dB for the volume level. grammable and a detection flag indicates when a stream of zero data has been detected.

7 RSVD RW 1 Reserved

6 DACFade RW 1 1 = volume fades between old/new value

5:3 RSVD R 0 Reserved for future use.

2 DACVOLU RW 0

1 SPKVOLU RW 0

0 RSVD RW 0 Reserved

Table 6. Volume Update Control Register 7 zerodet_flag R 0 1 = zero detect length exceeded. 6 RSVD R 0 Reserved for future use. 3 RSVD R 0 Reserved for future use. 1 RSVD R 0 Reserved for future use. 0 RSVD R 0 Reserved for future use. 7 zerodet_flag R 0 1 = zero detect length exceeded. Table 7. Gain Control Register

The signal volume can be controlled digitally, across a gain and attenuation range of -95.25dB to 0dB (0.375dB steps). cates mute; other values select the number of 0.375dB steps above -95.625dB for the volume level. the I2C address space of the device, access to the EQ ram occurs through the Control/Status registers. after the next write to the Right Input Volume register. Table 8. DAC Volume Control Registers

cients. (-2 ≤ coefficient < +2). Figure 4. 6-Tap IIR Equalizer Filter

EQ Filter Enable Register Register Address Bit Label Type Default Description R32 (20h) CONFIG1

7 EQ2_EN R/W 0 EQ bank 2 enable

following EQ stages are executed.

3 EQ1_EN R/W 0 EQ bank 1 enable

following EQ stages are executed. Table 9. CONFIG1 Register

DACCRAM Read Data (0x3D–LO, 0x3E –MID, 0x3F–HI), DACCRAM Write Data (0x3A–LO, 0x3B–MID, 0x3C–HI) Registers These two 24-bit registers provide the 24-bit data holding registers used when doing indire ct writes/reads to the DAC Coefficient RAM.
DACCRAM Address Register This 7-bit register provides the address to the internal RA M when doing indirect writes/r eads to the DAC Coefficient RAM.
DACCRAM STATUS Register This control register provides the write/read enable when doing indirect writes/reads to the DAC Coefficient RAM. Register Address Bit Label Type Default Description R58 (3Ah) DACCRAM_WRITE_LO 7:0 DACCRWD[7:0] R/W 0 Low byte of a 24-bit data register, contains the values to be written to the DACCRAM. The address written will have been specified by the DACCRAM Address fields. R59 (3Bh) DACCRAM_WRITE_MID 7:0 DACCRWD[15:8] R/W 0 Middle byte of a 24-bit data register, contains the values to be written to the DACCRAM. The address written will have been specified by the DACCRAM Address fields. R60 (3Ch) DACCRAM_WRITE_HI 7:0 DACCRWD[23:16] R/W 0 High byte of a 24-bit data register, contains the values to be written to the DACCRAM. The address written will have been specified by the DACCRAM Address fields. R61 (3Dh) DACCRAM_READ_LO 7:0 DACCRRD[7:0] R 0 Low byte of a 24-bit data register, contains the contents of the most recent DACCRAM address read from the RAM. The address read will have been specified by the DACCRAM Address fields. R62 (3Eh) DACCRAM_READ_MID 7:0 DACCRRD[15:8] R 0 Middle byte of a 24-bit data register, contains the contents of the most recent DACCRAM address read from the RAM. The address read will have been specified by the DACCRAM Address fields. R63 (3Fh) DACCRAM_READ_HI 7:0 DACCRRD[23:16] R 0 High byte of a 24-bit data register, contains the contents of the most recent DACCRAM address read from the RAM. The address read will have been specified by the DACCRAM Address fields.

Table 10. DACCRAM Read/Write Registers Table 11. DACCRAM Address Register

7 DACCRAM_Busy R 0 1 = read/write to DACCRAM in progress, cleared by

Table 12. DACCRAM Status Register

Write target address to DACCRAM_ADDR register.
Write D7:0 to the DACCRAM_WRITE_LO register
Write D15:8 to the DA CCRAM_WRITE_MID register
Write D23:16 to the DACCRAM_WRITE_HI register
On successful receipt of the DACCRAM_WRITE_HI data, the part will automatically start a write

cycle. The DACCRAM_Busy bit will be set high to indicate that a write is in progress.

On completion of the internal write cycle, the DACCRAM_Busy bit will be 0 (when operating the
The bus cycle may be terminated by the host or steps 2-6 may be repeated for writes to consec-

Figure 5. DAC Coefficient RAM Write Sequence

Write target address to DACCRAM_ADDR register.( EQ data is pre-fetched for read even if we
Start (or repeat start) a write cycle to DACCRAM _READ_LO and after the second byte (register
Signal a repeat start and indicate a read operation
Read D7:0 (register address incremented after ack by host)
Read D15:8 (register address incremented after ack by host)
Read D23:16 (register address incremented and ne xt EQ location pre-fetched after ack by host)
The host stops the bus cycle
Start (or repeat start instead of stopping the bus cycle in step 7) a write cycle indicating

DACCRAM_RD_LO as the target address.

After the second byte is acknowledged, signal a repeated start.
Indicate a read operation
Read the DACCRAM_READ_LO regist er as described in step 4

28 SCL cycles

Read the DACCRAM_READ_MID regi ster as described in step 5
Read the DACCRAM_READ_HI register as described in step 6
Repeat steps 8-13 as desired

Figure 6. DAC Coefficient RAM Read Sequence

DACCRAM EQ Addresess EQ 0 EQ1 Addr Channel 0 Coefficients Addr Channel 1 Coefficients Addr Channel 0 Coefficients Addr Channel 1 Coefficients 0x00 EQ_COEF_0F0_B0 0x20 EQ_COEF_1F0_B0 0x40 EQ_COEF_2F0_B0 0x60 EQ_COEF_3F0_B0 0x01 EQ_COEF_0F0_B1 0x21 EQ_COEF_1F0_B1 0x41 EQ_COEF_2F0_B1 0x61 EQ_COEF_3F0_B1 0x02 EQ_COEF_0F0_B2 0x22 EQ_COEF_1F0_B2 0x42 EQ_COEF_2F0_B2 0x62 EQ_COEF_3F0_B2 0x03 EQ_COEF_0F0_A1 0x23 EQ_COEF_1F0_A1 0x43 EQ_COEF_2F0_A1 0x63 EQ_COEF_3F0_A1 0x04 EQ_COEF_0F0_A2 0x24 EQ_COEF_1F0_A2 0x44 EQ_COEF_2F0_A2 0x64 EQ_COEF_3F0_A2 0x05 EQ_COEF_0F1_B0 0x25 EQ_COEF_1F1_B0 0x45 EQ_COEF_2F1_B0 0x65 EQ_COEF_3F1_B0 0x06 EQ_COEF_0F1_B1 0x26 EQ_COEF_1F1_B1 0x46 EQ_COEF_2F1_B1 0x66 EQ_COEF_3F1_B1 0x07 EQ_COEF_0F1_B2 0x27 EQ_COEF_1F1_B2 0x47 EQ_COEF_2F1_B2 0x67 EQ_COEF_3F1_B2 0x08 EQ_COEF_0F1_A1 0x28 EQ_COEF_1F1_A1 0x48 EQ_COEF_2F1_A1 0x68 EQ_COEF_3F1_A1 0x09 EQ_COEF_0F1_A2 0x29 EQ_COEF_1F1_A2 0x49 EQ_COEF_2F1_A2 0x69 EQ_COEF_3F1_A2 0x0A EQ_COEF_0F2_B0 0x2A EQ_COEF_1F2_B0 0x4A EQ_COEF_2F2_B0 0x6A EQ_COEF_3F2_B0 0x0B EQ_COEF_0F2_B1 0x2B EQ_COEF_1F2_B1 0x4B EQ_COEF_2F2_B1 0x6B EQ_COEF_3F2_B1 0x0C EQ_COEF_0F2_B2 0x2C EQ_COEF_1F2_B2 0x4C EQ_COEF_2F2_B2 0x6C EQ_COEF_3F2_B2 0x0D EQ_COEF_0F2_A1 0x2D EQ_COEF_1F2_A1 0x4D EQ_COEF_2F2_A1 0x6D EQ_COEF_3F2_A1 0x0E EQ_COEF_0F2_A2 0x2E EQ_COEF_1F2_A2 0x4E EQ_COEF_2F2_A2 0x6E EQ_COEF_3F2_A2 0x0F EQ_COEF_0F3_B0 0x2F EQ_COEF_1F3_B0 0x4F EQ_COEF_2F3_B0 0x6F EQ_COEF_3F3_B0 0x10 EQ_COEF_0F3_B1 0x30 EQ_COEF_1F3_B1 0x50 EQ_COEF_2F3_B1 0x70 EQ_COEF_3F3_B1 RA1 DA6AS DA0 RD7 Sr R AS RD0 AMRA7 1. DA: Device Address 6. A M: Acknowledge from master 2. RA: Register Address 7. N M: Not Acknowledge from master 3. EQ_A: EQ RAM Address 8. S: Start 4. RD: Register Data 9. S r: Repeated Start 5. AS: Acknowledge from slave 10. P: Stop SCL SDA DA[6:0], WS RA[7:0] RD[7:0] write EQ RAM Address RD[7:0] read EQ RAM Data Lo read EQ RAM Data Mid read EQ RAM Data Hi EQ_A ++; prefetch data DA[6:0], R Sr RD[7:0]RA[7:0] write EQ RAM Read Lo, truncate SP DA[6:0], W EQ RAM Data must be valid here Generic read operation EQ RAM read operation EQ_A updated; EQ RAM read req = 1

30 SCL cycles

Table 13. DACCRAM EQ Addresess

DACCRAM Bass/Treble Addresses 0x11 EQ_COEF_0F3_B2 0x31 EQ_COEF_1F3_B2 0x51 EQ_COEF_2F3_B2 0x71 EQ_COEF_3F3_B2 0x12 EQ_COEF_0F3_A1 0x32 EQ_COEF_1F3_A1 0x52 EQ_COEF_2F3_A1 0x72 EQ_COEF_3F3_A1 0x13 EQ_COEF_0F3_A2 0x33 EQ_COEF_1F3_A2 0x53 EQ_COEF_2F3_A2 0x73 EQ_COEF_3F3_A2 0x14 EQ_COEF_0F4_B0 0x34 EQ_COEF_1F4_B0 0x54 EQ_COEF_2F4_B0 0x74 EQ_COEF_3F4_B0 0x15 EQ_COEF_0F4_B1 0x35 EQ_COEF_1F4_B1 0x55 EQ_COEF_2F4_B1 0x75 EQ_COEF_3F4_B1 0x16 EQ_COEF_0F4_B2 0x36 EQ_COEF_1F4_B2 0x56 EQ_COEF_2F4_B2 0x76 EQ_COEF_3F4_B2 0x17 EQ_COEF_0F4_A1 0x37 EQ_COEF_1F4_A1 0x57 EQ_COEF_2F4_A1 0x77 EQ_COEF_3F4_A1 0x18 EQ_COEF_0F4_A2 0x38 EQ_COEF_1F4_A2 0x58 EQ_COEF_2F4_A2 0x78 EQ_COEF_3F4_A2 0x19 EQ_COEF_0F5_B0 0x39 EQ_COEF_1F5_B0 0x59 EQ_COEF_2F5_B0 0x79 EQ_COEF_3F5_B0 0x1A EQ_COEF_0F5_B1 0x3A EQ_COEF_1F5_B1 0x5A EQ_COEF_2F5_B1 0x7A EQ_COEF_3F5_B1 0x1B EQ_COEF_0F5_B2 0x3B EQ_COEF_1F5_B2 0x5B EQ_COEF_2F5_B2 0x7B EQ_COEF_3F5_B2 0x1C EQ_COEF_0F5_A1 0x3C EQ_COEF_1F5_A1 0x5C EQ_COEF_2F5_A1 0x7C EQ_COEF_3F5_A1 0x1D EQ_COEF_0F5_A2 0x3D EQ_COEF_1F5_A2 0x5D EQ_COEF_2F5_A2 0x7D EQ_COEF_3F5_A2 0x1E - 0x3E - 0x5E - 0x7E - 0x1F EQ_PRESCALE0 0x3F EQ_PRESCALE1 0x5F EQ_PRESCALE2 0x7F EQ_PRESCALE3 Addr Bass Coefficients1 Addr Treble Coefficients Addr 3D Coefficients 0x80 BASS_COEF_EXT1_B0 0x97 TR EB_COEF_EXT1_B0 0xAE 3D_COEF 0x81 BASS_COEF_EXT1_B1 0x98 TR EB_COEF_EXT1_B1 0xAF 3D_MIX 0x82 BASS_COEF_EXT1_B2 0x 99 TREB_COEF_EXT1_B2 0x83 BASS_COEF_EXT1_A1 0x9A TREB_COEF_EXT1_A1 0x84 BASS_COEF_EXT1_A2 0x9B TREB_COEF_EXT1_A2 0x85 BASS_COEF_EXT2_B0 0x9C TREB_COEF_EXT2_B0 0x86 BASS_COEF_EXT2_B1 0x9D TREB_COEF_EXT2_B1 0x87 BASS_COEF_EXT2_B2 0x9E TREB_COEF_EXT2_B2 0x88 BASS_COEF_EXT2_A1 0x9F TREB_COEF_EXT2_A1 0x89 BASS_COEF_EXT2_A2 0xA0 TREB_COEF_EXT2_A2 0x8A BASS_COEF_NLF_M1 2 0xA1 TREB_COEF_NLF_M1 0x8B BASS_COEF_NLF_M2 0xA2 TREB_COEF_NLF_M2 0x8C BASS_COEF_LMT_B0 0xA3 TREB_COEF_LMT_B0 EQ 0 EQ1 Addr Channel 0 Coefficients Addr Channel 1 Coefficients Addr Channel 0 Coefficients Addr Channel 1 Coefficients

Table 14. DACCRAM Bass/Treble Addresses the max positive or negative value. than 0dB it will saturate at 0dB as the final processing step within the DSP module. speaker output which from the user listening perception it would “sound louder”. 1.All B0 coefficients are set to unity (400000h) by default. All others, including M1 and M2, are 0 by default. 1 integer bit, and 22 fraction bits.

1 Addr Treble

Figure 7. Gain Compressor, Output vs Input expansion function for either increasing dynamic range or noise gating. nal level is increased, the gain is decreased to maintain a specific output level. lar threshold, the expander will reduce the gain even further to extend the dynamic range of the material.

IDT CONFIDENTIAL 14 V0.6 07/11 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS32201 ACS32201 LOW-POWER, HIGH-FIDELITY, CLASS-D AMPLIFIER 3.7.1. Configuration This compressor limiter provides the following configurable parameters.

Compressor/limiter
Threshold – The threshold ab ove which the compressor will reduce the dynamic range of the audio in the compression region.
Ratio – The ratio between the input dynamic range and the output dynamic range. For example, a ratio of 3 will reduce an input dynamic range of 9db to 3db.
Attack Time – The amount of time that changes in gain are smoothed over during the attack phase of the compressor.
Release Time – The amount of time that changes in gain are smoothed over during the release phase of the compressor.
Makeup gain – Used to increase the overall level of the compressed audio.
Expander
Threshold – The threshold below which the ex pander will increase the dynamic range of the audio.
Ratio – The ratio between the input dynamic range and the output dynamic range of the audio in the expansion range. For example a ratio of 3 will take an input dynamic range of 9db and expand it to 27db.
Attack Time – The amount of time that changes in gain are smoothed over during the attack phase of the expander
R e l e a s e T i m e
- The amount of time that changes in gain are smoothed over during the release phase of the expander.
Two level detection algorithms
RMS – Use an RMS measurement for the level.
Peak – Use a peak measurement for the level. 3.7.2. Controlling parameters In order to control this processing, there are a number of configurable parameters. The parameters and their ranges are:
Compressor/limiter
Threshold – -40db to 0db relative to full scale.
Ratio – 1 to 20
Attack Time – typically 0 to 500ms
Release Time – typically 25ms to 2 seconds
Makeup gain – 0 to 40db
Expander
Threshold – -30 to -60 dB
Ratio – 1 to 6
Attack Time – same as above
Release Time – same as above.
Two level detection algorithms
R M S
P e a k

Figure 8. Compressor block diagram As this diagram shows, there are 3 primary components of the compressor.

Level Detector: The level detector, oddly enough, detects the level of the incoming signal.
Gain Calculation: The gain calculation block is responsible for taking the output of the level

The gain calculation operates in 3 regions:
Linear region – If the level is higher th an the expander threshold and lower than the compression threshold, then the gain is 1.0
Compression region – When the level is higher than the compressor threshold, then the comp/limiter is in the compression region. The gain is a function of the compressor ratio and the signal level.
Expansion region – When the signal is lower than the expansion threshold, the comp/limiter is in the expansion region. In this region, the gain is a function of the signal level and the expansion ratio.
Compression region gain calculation: In the compression region, the gain calculation is: Atten(in db) = (1-1/ratio)(threshold(in db) – level(in db);
For example,
Ratio = 4:1 compression
Threshold = -16db
Level = -4 db The required attenuation is: 9db or a gain coefficient of 0.1259. Translating this calculation from log space to linear yields the formula: Gain =(level/threshold) 1/ratio*(threshold/level)
Expansion region gain calculation: In the ex pansion region, the attenuation calculation is: Level Detector Gain Calc Attack/ release filter Peak or RMS Compare to Thresholds Calc Gain Lowpass filter Gains based on Attack and release Audio In Audio Out

For example,
Ratio = 3:1
Threshold = -40db
Level = -44 db The resulting attenuation required is 8db or a gain value of 0.1585. The linear equation for calculating the gain is: Gain =(level/threshold) ratio*(threshold/level)
State Transitions: In addition to calculati ng the new gain for the compressor, the gain calcu- lation block will also select the filter coefficient for the attack/release filter. The rules for selecting the coefficient are as follows: In the compression region:
If the gain calculated is less than the last gain calculated (more compression is being applied), then the filter coefficient is the compressor attack.
If the gain calculated is more than the last ga in calculated (less compression), the filter coef- ficient is the compressor release.
In the expansion region:
If the calculated gain is less than the last gain calculated (closing expander, the filter coeffi- cient is the expander attack.
If the calculated gain is more than the last gain calculated, the filter coefficient is the expander release. In the linear region:
Modify gain until a gain of 1.0 is obtained.
If the last non-linear state was compression, use the compressor release.
If the last non-linear state was ex pansion, use the expander attack. 3. Attack/Release filter: In order to prevent objectionable artifacts, the gain is smoothly ramped from the current value to the new value calculated by the gain calculation block. In the PC-based comp/limiter, this is achieved using a simple tracking lowpass filter to smooth out the abrupt tran- sitions. The calculation (using the coefficient (coeff) selected by the gain block) is: Filtered_gain = coeff*last_filtered_gain + (1.0 - coeff)*target_gain; This creates a exponential ramp from the current gain value to the new value.

General compressor/limiter/expander control
Compressor/Limiter/Expander make-up gain
Compressor Threshold
Compressor ratio register
Compressor Attack Time Constant Register (Low) Register Address Bit Label Type Default Description R37 (25h) CLECTL 7:5 RSVD R 0h Reserved

4 Lvl_Mode RW 0

3 WindowSel RW 0

2 Exp_en RW 0 1 = enable expander

1 Limit_en RW 0 1 = enable limiter

0 Comp_en RW 0 1 = enable compressor

Table 15. CLECTL Register Table 16. MUGAIN Register Table 17. COMPTH Register Table 18. CMPRAT Register gain value during a compressor attack phase. Table 19. CATKTCL Register

Compressor Attack Time Constant Register (High)
Compressor Release Time Constant Register (Low)
Compressor Release Time Constant Register (High)
Limiter Threshold Register
Limiter Target Register
Limiter Attack Time Constant Register (Low )
Limiter Attack Time Constant Register (High )
Limiter Release Time Constant Register (Low ) Register Address Bit Label Type Default Description R42 (2Ah) CATKTCH 7:0 CATKTC[15:8] RW 00h High byte of the time constant used to ramp to a new gain value during a compressor attack phase.

Table 20. CATKTCH Register gain value during a compressor release phase. Table 21. CRELTCL Register gain value during a compressor release phase. Table 22. CRELTCH Register Table 23. LIMTH Register Table 24. LIMTGT Register gain value during a limiter attack phase. Table 25. LATKTCL Register gain value during a limiter attack phase. Table 26. LATKTCH Register gain value during a limiter release phase. Table 27. LRELTCL Register

Limiter Release Time Co nstant Register (High) 3.7.5. Expander Registers
Expander Threshold Register
Expander Ratio Register
Expander Attack Time Constant Register (Low)
Expander Attack Time Constant Register (High)
Expander Release Time Constant Register (Low)
Expander Release Time Constant Register (High) Register Address Bit Label Type Default Description R50 (32h) LRELTCH 7:0 LRELTC[15:8] RW 00h High byte of the time constant used to ramp to a new gain value during a limiter release phase.

Table 28. LRELTCH Register Table 29. EXPTH Register Table 30. EXPRAT Register gain value during a expander attack phase. Table 31. XATKTCL Register gain value during a expander attack phase. Table 32. XATKTCH Register gain value during a expander release phase. Table 33. XRELTCL Register gain value during a expander release phase. Table 34. XRELTCH Register

mable within a range. The input is prescaled (fixed) before summation to prevent saturation. The 3-D enhancement algorithm is a tried and true algorithm that uses two principles.

If the material common to the two channels is removed, then the speakers will sound more 3-D.
If the material for the opposite ch annel is presented to the current channel inverted, it will tend to

right ear that is leaking into the right ear. Figure 9. 3-D Channel Inversion

43 D E N R W 0 3D Enhancement Enable

3 TEEN RW 0 Treble Enhancement Enable

2 TNLFBYP RW 0 Treble Non-linear Function Bypass:

1 BEEN RW 0 Bass Enhancement Enable

0 BNLFBYP RW 0 Bass Non-linear Function Bypass:

Table 35. FX Control Register

tem below what it is actually capable of. Below is a diagram of the implementation of this algorithm. Figure 10. Bass Enhancement

Extract filter – This filter extracts the bass information that the speaker system can't reproduce.

This is a 4th order band pass filter with a typical bandwidth of 1.5 to 2 octaves.

NLF – This is a Nonlinear function that is used to generate the harmonics of the fundamentals in

the extracted audio. More on this function later.

Limit Filter – This filter will limit the amplitude of the harmonics generated to prevent the har-
Mixing – This structure allows mixing of the generated harmonics and the original material.
Cutoff Filter – This filter is used to remove all material below the cutoff frequency of the speaker

can't be reproduced. This is a 2nd order high pass filter.

IDT CONFIDENTIAL 22 V0.6 07/11 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS32201 ACS32201 LOW-POWER, HIGH-FIDELITY, CLASS-D AMPLIFIER SineOut = sin(Temp*pi/2); // Take the sine of this, the pi/2 provides full usage. // half wave rectifier part Temp = in*mix2; // Mix 2 can be between 0 and 8.0 Temp = clip(temp); // clip this result halfOut = rect(in); //Half wave rectify input; // if input<0; output=0; else output=input output = SineOut + halfOut; // Sum the two Implementation Notes: It is probably not practical to actua lly implement a sine function in hardware, so a table imple- mentation is probably appropriate. After some experimentatio n, a table of 512 entries provides sufficient resolution. Note that the table is symmetric, sin(x) = y; sin(-x) = -y. Depending on complexity of dealing with the sine, this can cut the table size in half. 3.10.2. Signal processing summary

DSP requirements:
Filters:
Extract Filter - 2 Biquads - 4th order extraction provides a tighter bass.
Limit Filter - 1 Biquad - 2nd order is now acceptable for limiting the output
Cutoff Filter - 1 Biquad - 2nd order is sufficient for this high pass filter.
Non-linear function:
2 Clipping Multiplies.
Sine lookup
Half wave rectifier.
S u m
F i n a l M i x e r :
2 multplies and sum 3.10.3. Control Points
Bass Extract Filter– Controls the frequency content that is processed by the harmonic genera- tor. This is 2 biquadratic filters the 2 sets of 5 coefficients are held in the EQ RAM block (see EQ section for RAM access information and coefficient addresses).
Nonlinear Function– Controls the harmonics generated. The 2 sets of coefficients are held in the EQ RAM block (see EQ section for RAM access information and coefficient addresses).
Limit Filter – Limits the harmonics mixed into the audio stream. This is a biquadratic filter. The 5 coefficients are held in the EQ RAM block (see EQ section for RAM access information and coefficient addresses).
Cutoff Filter – Limits the low frequencies sent to the speaker. This is a biquadratic filter. The 5 coefficients are held in the EQ RAM block (see EQ section for RAM access information and coefficient addresses).
Bass mix control – Controls the amount of the generated harmonics that are added to the orig- inal signal.

enhancement replaces these lost high frequencies. good predictor of audio between 10K-20K. Figure 11. Treble Enhancement frequencies. These harmonics are then summed back into the original signal, providing a brighter sound. This algorithm has 4 components.

Extract Filter– This filter is used to extract the treble between 4-8K. This is 2 2nd order high pass filters.
Enhanced Treble Non-Linear Function– Generates high frequency components
Limit Filter– This filter limits the harmonics generated by the NLF to prevent any significant aliasing. A second order filter is sufficient.
Mixing Network – This simply sums the generated harmonic signals into the original signal. 3.11.1. Enhanced Treble NLF The enhanced treble NLF has a different set of requirements than the psychoacoustic bass. In par- ticular, the presence of odd high frequency harmo nics is objectionable. Thus the most promising NLF for enhanced treble is a half wave rectifier. 3.11.2. Signal processing summary Thus the signal processing summary for the enhanced treble is currently:
1 bi-quad as an extraction filter.
same as Psychoacoustic bass (if possible) to a half wave rectifier - 1 comparison
1 bi-quad as a limit filter
Mixing network - 2 multiplies and sum. NLF Extract Filter Limit Filter

Extract Filter – This controls which frequencies in the original material are used to create the harmonics. This is 2 biquadratic filters. The 2 sets of 5 coefficients are held in the EQ RAM block (see EQ section for RAM access information and coefficient addresses.)
Nonlinear Function– This controls the creation of the harmonics. The 2 coefficients are held in the EQ RAM block (see EQ section for RAM access information and coefficient addresses.)
Limit Filter – This limits the harmonics mixed with the audio signal to prevent aliasing. This is a biquadratic filter. The 5 coefficients are held in the EQ RAM block (see EQ section for RAM access information and coefficient addresses.)
Treble (Harmonic) mix– controls how much of the generated harmonics are mixed back into the original content. 3.12. Mute and De-Emphasis The ACS32201 has a Soft Mute function, which is used to gr adually attenuate the digital signal volume to zero. The gain returns to its previous setting if the soft mute is removed. At startup, the codec is muted by default; to enable audio play, the mute bit must be cleared to 0. After the equalization filters, de-emphasis may be performe d on the audio data to compensate for pre-emphasis that may be included in the audio stream. De-emphasis filteri ng is only available for 48kHz, 44.1kHz, and 32kHz sample rates. 3.13. Mono Operation and Phase Inversion Normal stereo operation converts left and right channel digi tal audio data to analog in separate DACs. However, it is also possible to have the same signal (left or right) app ear on both output channels by disabling one channel; alter- nately, there is a mono-mix mode that mixes the two channels digitally before converting to using only one converter. In this mode, the resulting mixed stream signal can appear on both PWM output channels. The DAC output defaults to non-inverted. Setting DACPOLL and DACPOLR bits will invert the DAC output phase on the left and right channels. 3.13.1. DAC Control Register Register Address Bit Label Type Default Description R24 (18h) CNVRTR1

7 DACPOLR RW 0 Invert DAC Right signal

6 DACPOLL RW 0 Invert DAC Left signal

2 DEEMP RW 0

Table 36. CNVRTR1 Register

remains at ground, so that no click noise is produced when muting or un-muting. Gains above 0dB run the risk of clipping large signals. that smoothly changes volume from the current value to the target value.

Feedback filters are applied to shape any noise. The filters move noise from audible frequencies to frequencies above the audio range.
The PWM block converts the data streams to tri-state PWM signals and sends them to the power stages.
Finally, the Class-D controller bl ock adjusts the output volume to provide constant output power across supply voltage. The power stages boost the signals to higher levels, sufficient to drive speakers at a comfortable lis- tening level. Register Address Bit Label Type Default Description R2 (2h) SPKVOLL

7 RSVD R 0 Reserved

after the next write to the Right Input Volume register. Table 37. SPKVOL L/R Registers

IDT CONFIDENTIAL 26 V0.6 07/11 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS32201 ACS32201 LOW-POWER, HIGH-FIDELITY, CLASS-D AMPLIFIER 3.14.2.1. Constant Output Power Mode In normal operation the BTL amplifier is rated at 0. 5W (full scale digital with 6dB BTL gain) into an 8 However, when constant output power mode is enab led, the full scale output is held constant from 3.1V to 5.5V. The BTL amplifier in ACS32201 will co ntinuously adjust to power supply changes to ensure that the full scale output power remains constant. This is no t an automatic level control. Rather, this function prevents sudden volume changes when switching between battery and line power. Please note, when in this mode the amplifier efficiency may be reduced and decr eases with higher supply volt- ages and lower target values. A simple 5-bit ADC is used to monitor PVDD. As PVDD raises or lowers, the analog circuit will send a 5-bit code to the digital section that will aver age and then calculate a gain adjustment. The BTL audio signal will be multiplied by this gain value (in addition to the user volume controls). The user will select a target val ue for the circuit. The constant ou tput function will calculate a gain adjustment that will provide approximately the same full sc ale output voltage as provided when PVDD causes the same code value. So, if the tar get is 9 then a PVDD voltage of about 3.7V would generate a code value of 9 and a full scale output power of about 630mW into 8 ohms. If PVDD should rise to 4V, generating a code of 13, then th e constant output power circuit would reduce the gain by 0.75dB (4 codes * 0.1875dB) to keep the full scale output at the target level. The circuit may be configured to add gain, attenuation, or both to maintain the full-scale output level. If the needed adjustment falls outside of the range of the circuit (only attenuation is enabled and gain is needed, for example) then the circuit will apply as much correction as it is able. Through the use of gain, attenuation, and target values, different behaviors may be implemented:

Attenuation only, target set to mimic a low supply voltage - Constant output level across bat- tery state with constant quality (THD/SNR)
Attenuation only, target set to mimic a moderate supply voltage - Output limiting to an approximate power level. Level will decrease at lower supply voltages but won’t increase beyond a specific point.
Gain only, target at or near max - Output will remain relatively constant but distortion will increase as PVDD is lowered. This mimics the behavior of common class-AB amplifiers.
Gain and attenuation - Output remains at a le vel below the maximum possible at the highest supply voltage and above the theoretical full scale at minimum supply. Full scale PCM input clips when the supply voltage is low but won’t become too loud when the supply voltage is high. In addition to maintaining a constant output level, PVDD may be monitored for a large, sudden, change. If the High Delta function is enabled a nd PVDD changes more than 4 code steps since the last cycle, the output will be rapidly reduced then gradually increased to the target level. When using this circuit, please take note of the following:
The full scale output power may be limited by the supply voltage.
Full scale output power is affected by other gain controls in the output path including the EQ and compressor/limiter.
The Constant Output Power function is intended to help maintain a constant output level, not an exact output level. The output level for a specific target may vary part to part. If limiting is

Noise on the PVDD supply may cause erratic behavior. Use the recommended supply decoupling caps and verify that the power supply can support the peak currents demanded by a class-D amplifier. Constant Output Power error (dB) relative to a target of 8 for an ideal part and the output error if left uncorrected across a 3.1 to 5.5V supply range.

Figure 12. Constant Output Power Error

Figure 13. Constant Output Power nominal and high/low sense circuit will be averaged for at least 200ms.

Constant Output Power 1 Register Address Bit Label Type Default Description R34 (22h) Constant Output Power 1

7 COPAtten RW 0

higher than the target value. higher than the target value.

5 HDeltaEn RW 0

reduced rapidly then slowly returned to the target level. 4:0 COPTarget[4:0] RW 8h 5-bit target fo r the Constant Output Power function. Table 38. Constant Output Power 1 Register

Constant Output Power 2
Constant Output Power 3
Configuration Register Register Address Bit Label Type Default Description R35 (23h) Constant Output Power 2

6 RSVD R 0 Reserved

Table 39. Constant Output Power 2 Register

7 HighDelta R 0

6 RSVD R 0

higher than the target value. Table 40. Constant Output Power 3 Register 7:2 RSVD R 0h Reserved for future use. Table 41. CONFIG0 Register

PWM Control 0 Register
PWM Control 1 Register
PWM Control 2 Register
PWM Control 3 Register Register Address Bit Label Type Default Description R66 (42h) PWM0 7:5 SCTO RW 11 Class-D Short Circuit Detect Time-out 00 = 10uS 01 = 100uS 10 = 500uS 11 = 100mS 5U V L O R W 1 Under Voltage Lock Out 1 = BTL output disabled if PVDD sense circuit returns code 0 4 roundup RW 1 1 = roundup, 0 = truncate for quantizer 3 bfclr RW 0 1 = disable binomial filter 2 fourthorder RW 1 1 = 4th order bi nomial filter; 0 = 3rd order 1 add3_sel RW 0 1 = 24-bit Noise Shaper output (pre-quantizer) 0 = 8/9/10-bit quantizer output 0 quantizer_sel RW 0

Table 42. PWM0 Register Dither position, where dither inserted after NS. Table 43. PWM1 Register inverting the output signal. Table 44. PWM2 Register Table 45. PWM3 Register

the default state of the device. outputs will be turned off when disabled.

4 SPKOutL RW 0 Left Speaker Output Enable

3 SPKOutR RW 0 Right Speak er Output Enable

2 RSVD RW 0

1 RSVD RW 0

0 VREF RW 1 Voltage reference

Note: A value of “1” indicates the output is enabled; a value of ‘0’ disables the output. Table 46. Power Management 2 Register

current level is safe but that increased volume would result in a critical overheat condition. volume are programmable to happen every 1, 2, 4, or 8 Poll cycles and in steps of 0.75dB to 6dB. This allows a full scale volume increase in a range of 10s of milliseconds to 10s of seconds.

1 TSDEN RW 0

Table 47. Additional Control Register Table 48. Speaker Operation

IDT CONFIDENTIAL 33 V0.6 07/11 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS32201 ACS32201 LOW-POWER, HIGH-FIDELITY, CLASS-D AMPLIFIER When both overheat bits are 0, the volume is allo wed to increment by the IncStep size, unless the volume has already reached the maximum value allowed. Any subsequent increment will be held off until the programmed number of polling cycles have occurred. When the low overheat bit is 1 and the high overheat bit is 0, this indicates that the volume is cur- rently at a safe point but the temperature is higher than desired and incrementing the volume may cause severe overheating. The volume is held at the current value. When the high overheat bit is 1, damage could occur, so the volume se tting will be immediately reduced by the Decrement Step value. As the ov erheat bits are re-polled, this volume reduction will continue until the high overheat bit drops to 0 or the volume value reaches the minimum setting. If the high overheat bit remains 1 even at the minimum setting, th en the mute control bit will be asserted. If the high overheat bit persists even after mute, then the BTL amp will be powered down. 3.16.2. Thermal Trip Points. The high and low trip points can be adjusted to suit the needs of a particular system implementation. There is a “shift” value (TripShift) which sets the low trip point, and there is a “split” value (TripSplit) that sets how many degrees above the low trip point the high trip point is. By default: TripShift = 2 (140 degrees C) TripSplit = 0 (15 degrees C) Therefore: High Trip Point = 155°C. Low Trip Point = 140°C.

Figure 14. Temp sense volume adjustment algorithm

Only the high overheat is used, the low overheat is ignored.
Whenever polled, if the high over heat is 1, then the volume setting will immediately be set to 0h.
Conversely, if the high overheat is 0, the volume setting will immediately be set to the MaxVol value.
Both volume clear and volume set events occur at the polling rate. During this mode, the algorithm still possesses the ability to mute and then power down the BTL amp if the high overheat continues to be 1. This mode is disabled by default. 3.16.5. Short Circuit Protection To avoid damage to the outputs if a short circuit condition should occur, both the headphone and BTL amplifiers imple- ment short circuit protection circuits. The headphone output amplifier will detect the load current and limit its output if in an over current state. The BTL amplifie r will sense a short to PVDD, ground, or between its +/- outputs and disable its output if a short is detected. After a brief time, the amplifier will turn on again. If a short circuit condition is still present, the amplifier will disable itself again. Increment Ratio Count OverheatHL ==? IDLE TS Disabled Every “Poll” time (8ms default) 01 00 Increment Volume by IncStep Ratio met & Vol /= Max? No Yes Vol @ Min? Yes No Vol = Mute? Yes Decrement Volume by DecStep Volume = Mute BTL PWD No

The thermal shutdown circuit is enabled using the Additional Control Register, see Table 49. Table 49. Additional Control Register

7 TripHighStat R 0

6 TripLowStat R 0

Table 50. THERMTS Register

6 InstCutMode RW 0

Table 51. THERMTSPKR1 Register

7 ForcePwdStatus R 0

Table 52. THERMTSPKR2 Register

the LSB are then transmitted in order. Figure 19. I

6 BCLKINV RW 0

Table 53. AIC1 Register

1 BCLK1 BCLK

inputs. The Tri-stated pins are pulled low with an internal pull-down resistor unless that resistor is disabled. The BCM mode bit clock generator produces 16, 20, or 32 bit cycles per sample. Tri-states DACLRCLK and DACBCLK pins. Table 54. AIC2 Register

2 DDIPDD RW 0

0 DBCPDD RW 0

Table 55. AIC3 Register Table 56. Master Mode BCLK Frequency Control Register

Figure 24. Multiple Read Cycle descriptive code to higher level software such as an operating system driver or application software.

Device Address Register
Device Identification Registers
Device Revision Register 4.9.5.2. Register Reset The ACS32201 registers may be reset to their defau lt values using the reset register. Writing a spe- cial, non-zero value to this register causes all ot her registers to assume their default states. Device status bits will not necessarily change their values depending on the state of the device. Register Address Bit Label Type Default Description R124 (7Ch) DEVADR 7:1 ADDR[7:1] RW 1101010 7-bit slave address

0 RSVD R 0 Not used - this bit is the R/nW bit in the 2-wire

Table 57. DEVADRl Register Table 58. DEVID H&L Registers 7:4 MAJ[3:0] R xh 4-bit major revision number. Contact IDT. 3:0 MNR[3:0] R xh 4-bit minor revision number. Contact IDT. Table 59. REVID Register Table 60. RESET Register

122.880 MHz (2560 x 48 KHz)
112.896 (2560 x 44.1 KHz) It is important that the crystal oscillator and needed PLLs remain on until all audio functions are dis- abled. 5.2. Clocking and Sample Rates The ACS32201 utilizes internal PLLs to generate the audio mast er clock (MCLK) at 56.44 8MHz (22.5792MHz *2.5) a delay of up to 5mS may be needed for the part to properly lock PLLs, flush filters, etc. The clocking of the ACS32201 is controlled using the BR[1:0] and BM[2:0] control bits. Each value of BR[1:0] + BM[2:0]selects one combination of MC LK division ratios and hence one combination of sample rates The BR[1:0] and BM[2:0] bits must be set to configure the appropriate ADC and DAC sample rates in both master and slave mode. Register Address Bit Label Type Default Description R25 (19h) DAC Sample Rate Control (DACSR) 7:6 DBCM[1:0] RW 00 DAC Bit Clock Mode (for data interface DACBCLK generation in master mode) 00 = Auto 01 = 32x fs 10 = 40x fs 11 = 64x fs

5 RSVD R 0 Reserved

Table 61. DACSR Register

40.96 MHz

011 Reserved

Table 62. Master Clock and Sample Rates

61.44 MHz

recommended operating temperature range. Table 63. Electrical Specification: Maximum Ratings Table 64. Recommended Operating Conditions

2.1 Vrms

0.5 W(ave)

1 W(ave)

Table 65. Device Characteristics

Table 67. Low power mode power consumption load but not PLL/clock buffer section. Table 66. Typical Power Consumption

Table 68. Register Map

Registers not described in this map should be considered “reserved”.
Numerous portions of the register map are comp atible with popular codecs from other vendors. R52 (34h) EXPRAT Expander Ratio EXPRAT2 EXPRAT1 EXPRAT0 00h R53 (35h) XATKTCL Expander Attack time constant Low XATKTC7 XATKTC6 XATKTC5 XATKTC4 XATKTC3 XATKTC2 XATKTC1 XATKTC0 00h R54 (36h) XATKTCH Expander Attack time constant High XATKTC15 XATKTC14 XATKTC13 XATKTC12 XATKTC11 XATKTC10 XATKTC9 XATKTC8 00h R55 (37h) XRELTCL Expander Release time constant Low XRELTC7 XRELTC6 XRELTC5 XRELTC4 XRELTC3 XRELTC2 XRELTC1 XRELTC0 00h R56 (38h) XRELTCH Expander Release time constant High XRELTC15 XRELTC14 XRELTC13 XRELTC12 XRELTC11 XRELTC10 XRELTC9 XRELTC8 00h R57 (39h) FXCTL Effects Control 3DEN TEEN TNLFBYP BEEN BNLFBYP 00h R58 (3Ah) DACCRWRL DACCRAM_WRITE_LO DACCRWD[7:0] 00h R59 (3Bh) DACCRWRM DACCRAM_WRITE_MID DACCRWD[15:8] 00h R60 (3Ch) DACCRWRH DACCRAM_WRITE_HI DACCRWD[23:16] 00h R61 (3Dh) DACCRRDL DACCRAM_READ_LO DACCRRD[7:0] 00h R62 (3Eh) DACCRRDM DACCRRAM_READ_MID DACCRRD[15:8] 00h R63 (3Fh) DACCRRDH DACCRRAM_READ_HI DACCRRD[23:16] 00h R64 (40h) DACCRADDR DACCRAM_ADDR DACCRADD[7:0] 00h R65 (41h) DCOFSEL DC_COEF_SEL dc_coef_sel[2:0] 05h R66-123 RSVD RSVD NA R124(7Ch) DEVADR I2C Device Address ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 D4h R125(7Dh) DEVIDL Device IDLow DID7 DI D6 DID5 DID4 DID3 DI D2 DID1 DID0 32h R126(7Eh) DEVIDH Device ID High DID15 DID14 DID13 DID12 DID11 DID10 DID9 DID8 01h R127(7Fh) REVID Device Revision MA J3 MAJ2 MAJ1 MAJ0 MNR3 MNR2 MNR1 MNR0 xxh R128(80h) RESET Reset Writing 0x85 to this register resets all registers to their default state 00h R129-R135 (81h - 87h) Reserved RSVD NA R136(88h) THERMSPKR2 Speaker Thermal Algorithm Status ForcePwd Status VolStatus[6:0] 08h R137-R255 (88h-FFh) Reserved RSVD NA 1. For device revision information, please contact IDT. Register (D15:9) Name Remarks Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0] Default

Figure 25. ACS32201 TAG Pinout

Figure 26. ACS32201 NAG Pinout

Table 69. ACS32201 TAG Power Pins Table 70. ACS32201 TAG Reference Pins Table 71. ACS32201 TAG Analog Output Pins

Table 72. ACS32201 TAG Data and Control Pins Table 73. ACS32201 TAG Clock Pins

Table 74. ACS32201 NAG Power Pins Table 75. ACS32201 NAG Reference Pins Table 76. ACS32201 NAG Analog Output Pins

Table 77. ACS32201 NAG Data and Control Pins Table 78. ACS32201 NAG Clock Pins

Figure 27. Package Outline Note: IDT’s package thicknesses are <2.5mm and <350 mm3, so 260 applies in every case. temperature (this means Peak reflow temperature +0 oC. For example 260 oC+0 oC) at the rated MSL level. Table 79. Reflow Temperatures

Figure 28. NAG/HLA Package Outline Note: IDT’s package thicknesses are <2.5mm and <350 mm3, so 260 applies in every case. temperature (this means Peak reflow temperature +0 oC. For example 260 oC+0 oC) at the rated MSL level. Table 80. Reflow Temperatures

IDT CONFIDENTIAL 59 V0.6 07/11 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS32201 ACS32201 LOW-POWER, HIGH-FIDELITY, CLASS-D AMPLIFIER 11. ORDERING INFORMATION yy = silicon revision, contact IDT for current part number. 12.DISCLAIMER While the information presented herein has been checked for both accuracy and reliability, manufac- turer assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal co mmercial applications. Any other applications, such as those requiring extended temper ature range, high reliability, or other extraord inary environmental requirements, are not recommended without additi onal processing by manufacturer. Manufacturer reserves the right to change any circuitry or spec ifications without notice. Manufacturer does not authorize or warrant any product for use in life support devices or critical medical instruments. ACS32201XTAGyyX TLA package ACS32201XNAGyyX HLA package

LOW-POWER, HIGH-FIDELITY, CLASS-D AMPLIFIER

6024 Silver Creek Valley Road

San Jose, California 95138 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications de- scribed herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and perfor- mance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT p roduct can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, in- cluding protected names, logos and designs, are the property of IDT or their respective third party owners. 13.DOCUMENT REVISION HISTORY Revision Date Description of Change

0.5 June 2011 initial release

0.6 July 2011 updated power consumption, TLA package drawing.

Product Information

ACS32201 specifications and overview.

Summary

PORTABLE CONSUMER DEVICE

Description

PORTABLE CONSUMER DEVICE

Source title ACS32201 Datasheet(PDF) - Integrated Device Technology

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