ACS112MS INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- Devices QML Qualified in Accordance with MIL-PRF-38535
- Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96704 and Intersil’sIntersil QM Plan
- 1.25 Micron Radiation Hardened SOS CMOS
- Single Event Upset (SEU) Immunity: <1 x 10 -10 Errors/Bit/Day (Typ)
- Latch-Up Free Under Any Conditions oC to +125oC
- Significant Power Reduction Compared to ALSTTL Logic
- Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min
- Input Current≤ 1µA at VOL, VOH
Description
The Intersil ACS112MS is a Radiation Hardened Dual J-K Flip-Flop with Set and Reset. The output change states on the negative transition of the clock (CP1N or CP2N). The ACS112MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the radiation hard- ened, high-speed, CMOS/SOS Logic Family. The ACS112MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or a Ceramic Dual-In-Line Package (D suffix). January 1996
Ordering Information
PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE 5962F9670401VEC -55 oC to +125oC MIL-PRF-38535 Class V 16 Lead SBDIP 5962F9670401VXC -55 oC to +125oC MIL-PRF-38535 Class V 16 Lead Ceramic Flatpack ACS112D/Sample 25 oC Sample 16 Lead SBDIP ACS112K/Sample 25 oC Sample 16 Lead Ceramic Flatpack ACS112HMSR 25 oC Die Die Spec Number 518816 File Number 3571.1