ACS03MS RENESAS | Alldatasheet
Document overview
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- PDF pages: 3
Technical content
Features
- Devices QML Qualified in Accordance with MIL-PRF- 38535
- Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96703 and Intersil’s QM Plan
- 1.25 Micron Radiation Hardened SOS CMOS
- Total Dose >300K RAD (Si)
- Single Event Upset (SEU) Immunity: <1 x 10 -10 Errors/Bit/Day (Typ)
- SEU LET Threshold>100 MEV-cm2/mg
- Dose Rate Upset>1011 RAD (Si)/s, 20ns Pulse
- Dose Rate Survivability>1012 RAD (Si)/s, 20ns Pulse
- Latch-Up Free Under Any Conditions
- Military Temperature Range-55oC to +125oC
- Significant Power Reduction Compared to ALSTTL Logic
- DC Operating Voltage Range 4.5V to 5.5V
- Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min
- Input Current 1A at VOL, VOH
- Fast Propagation Delay15ns (Max), 10ns (Typ)
Description
The Intersil ACS03MS is a Radiation Hardened quad 2-input NAND gate with open drain outputs. The open drain output can drive resistive loads from a separate supply voltage. The ACS03MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic Family. The ACS03MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or a Ceramic Dual-In-Line Package (D suffix). Pinouts
14 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T14, LEAD FINISH C TOP VIEW
14 PIN CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR CDFP3-F14, LEAD FINISH C TOP VIEW GND VCC GND VCC
Ordering Information
PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE 5962F9670301VCC -55 oC to +125oC MIL-PRF-38535 Class V 14 Lead SBDIP 5962F9670301VXC -55 oC to +125oC MIL-PRF-38535 Class V 14 Lead Ceramic Flatpack ACS03D/Sample 25 oC Sample 14 Lead SBDIP ACS03K/Sample 25 oC Sample 14 Lead Ceramic Flatpack ACS03HMSR 25 oCD i e D i e
FN3064 Rev 1.00 Page 2 of 3 January 1996 ACS03MS Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 1999. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Functional Diagram An Bn Yn TRUTH TABLE INPUTS OUTPUT An Bn Yn L L Z (Note 2), H (Note 3) L H Z (Note 2), H (Note 3) H L Z (Note 2), H (Note 3) HH L NOTES: 1. L = Low, H = High, Z = High Impedance 2. Without Pull-up Resistor 3. With Pull-up Resistor
FN3064 Rev 1.00 Page 3 of 3 January 1996 Die Characteristics DIE DIMENSIONS: 68 mils x 79 mils 1730mm x 2010mm METALLIZATION: Type: AlSi Metal 1 Thickness: 7.125k Å 1.125kÅ Metal 2 Thickness: 9kÅ 1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ 1kÅ WORST CASE CURRENT DENSITY: <2.0 x 105A/cm2 BOND PAD SIZE: 110m x 110m 4.3 mils x 4.3 mils Metallization Mask Layout ACS03MS B1 VCC B4 (12) A4 (11) Y4 (10) B3 (7) (8) (9) A3 Y1 (3) A2 (4) B2 (5) Y2 (6) (14) Y3GND (2) (13) (1)