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Document overview
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Technical content
Features
Thin Package (0.9mm typ) Excellent Linearity 3-mode power control with Vbp and Vmode – Bypass / Mid Power Mode / High Power Mode High Effi ciency at max output power 10-pin surface mounting package Internal 50ohm matching networks for both RF input and output Integrated coupler – Coupler and Isolation ports for daisy chain Lead-free, RoHS compliant, Green
Applications
UMTS (WCDMA, HSDPA, HSUPA, HSPA+) LTE
Ordering Information
Part Number Number of Devices Container ACPM-5008-TR1 1000 178mm (7”) Tape/Reel ACPM-5008-BLK 100 Bulk
No damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value. Operation of any single parameter outside these conditions with the remaining parameters set at or below nominal values may result in permanent damage. Description Min. Typ. Max. Unit RF Input Power (Pin) 0 10 dBm DC Supply Voltage (Vcc1, Vcc2) 0 3.4 5.0 V Enable Voltage (Ven) 0 2.6 3.3 V Mode Control Voltage (Vmode) 0 2.6 3.3 V Bypass Control (Vbp) 0 2.6 3.3 V Storage Temperature (Tstg) -55 25 +125 °C Recommended Operating Condition Description Min. Typ. Max. Unit DC Supply Voltage (Vcc1, Vcc2) 3.2 3.4 4.2 V Enable Voltage (Ven) Low High 1.35 2.6 0.5 3.1 V V Mode Control Voltage (Vmode) Low High 1.35 2.6 0.5 3.1 V V Bypass Control Voltage (Vbp) Low High 1.35 2.6 0.5 3.1 V V Operating Frequency (fo) 880 915 MHz Ambient Temperature (Ta) -20 25 85 °C Operating Logic Table Power Mode Ven Vmode Vbp Pout (Rel99) Pout (HSDPA, HSUPA MPR=0dB) High Power Mode High Low X ~ 28.5 dBm ~ 27.5 dBm Mid Power Mode High High Low ~ 17 dBm ~ 16 dBm Bypass Mode High High High ~ 7.5 dBm ~ 6.5 dBm Shut Down Mode Low Low Low – –
Electrical Characteristics for WCDMA Mode – Conditions: Vcc = 3.4V, Ven = 2.6V, Ta = 25°C, Zin/Zout = 50ohm – Signal Confi guration: 3GPP (DPCCH + 1DPDCH) Up-Link unless specifi ed otherwise. Characteristics Condition Min. Typ. Max. Unit Operating Frequency Range 880 – 915 MHz Maximum Output Power (High Power Mode) Rel99 28.5 dBm HSDPA, HSUPA MPR=0dB 27.5 dBm Gain High Power Mode, Pout=28.5dBm 24.5 28 dB Mid Power Mode, Pout=17dBm 14 18 dB Bypass Mode, Pout=7dBm 8 11 dB Power Added Effi ciency High Power Mode, Pout=28.5dBm 36.5 40 % Mid Power Mode, Pout=17dBm 16.1 20.7 % Bypass Mode, Pout=7dBm 6.8 12.3 % Total Supply Current High Power Mode, Pout=28.5dBm 520 570 mA Mid Power Mode, Pout=17dBm 70 90 mA Bypass Mode, Pout13.5dBm 50 mA Bypass Mode, Pout=7dBm 11 20 mA Bypass Mode, Pout=3.5dBm 8.5 mA Quiescent Current High Power Mode 90 123 155 mA Mid Power Mode 10 19 30 mA Bypass Mode 1 3.1 5 mA Enable Current High Power Mode 5 A Mid Power Mode 5 A Bypass Mode 5 A Mode Control Current Mid Power Mode 5 A Bypass Mode 5 A Bypass Control Current Bypass 5 A Total Current in Power-down mode Ven=0V, Vmode=0V, Vbp=0V 5 A UMTS Adjacent Channel Leakage Ratio (ACLR)
5 MHz off set
10 MHz off set
14.8MHz off set Pout ≤ (max power – MPR) -42 -57 -66 -36 -46 -58 dBc dBc dBc LTE ACLR LTE to LTE, E-UTRA ACLR Pout ≤ (maximum power – MPR) -33 dBc UTRAACLR1 Pout ≤ (maximum power – MPR) -36 dBc UTRAACLR2 Pout ≤ (maximum power – MPR) -39 dBc Harmonic Suppression Second Third High Power Mode, Pout=28.5dBm -43 -66 -35 -42 dBc dBc Input VSWR 2.5:1 Stability (Spurious Output) VSWR 5:1, All phase -60 dBc Rx Band Noise Power (Vcc=4.2V) High Power Mode, Pout=28.5dBm -136.5 dBm/Hz GPS Band Noise Power (Vcc=4.2V) High Power Mode, Pout=28.5dBm -150 dBm/Hz ISM Band Noise Power (Vcc=4.2V) High Power Mode, Pout=28.5dBm -158 dBm/Hz Rx Band Gain (925-960MHz) Where G is gain in Tx band G-1 dB GPS Band Gain (1574-1577MHz) Where G is gain in Tx band G-28 dB GLONASS Band Gain (1597-1607MHz) Where G is gain in Tx band G-30 dB ISM Band Gain (2400-2483.5MHz) Where G is gain in Tx band G-65 dB Media Band Gain (716-728MHz) Where G is gain in Tx band G-1.5 dB Continued on next page...
HSDPA Signal confi guration used: 3GPP TS 34.121-1 Annex C (normative e): Measurement channels C.10.1 UL reference measurement channel for HSDPA tests Table C.10.1.4: values for transmitter characteristics tests with HS-DPCCH Sub-test 2 (CM=1.0, MPR=0.0) HSUPA signal confi guration used: 3GPP TS 34.121-1 Annex C (normative): Measurement channels C.11.1 UL reference measurement channel for E-DCH tests At 3.2V operation, 0.5dB backoff is allowed for maximum power output. Footprint All dimensions are in millimeter X-Ray Top View 0.125 0.10 0.35 0.35 0.60 0.10 1.50 0.25 0.3 Pin 1 PIN Description Pin # Name Description
1 Vcc1 DC Supply Voltage
2 RFin RF Input
3 Vbp Bypass Control
4 Vmode Mode Control
5 Ven PA Enable
6 CPL Coupling port of Coupler
7 GND Ground
8 ISO Isolation port of Coupler
9 RFOut RF Out
10 Vcc2 DC Supply Voltage
Electrical Characteristics for WCDMA Mode (Cont.) Phase Discontinuity low power modemid power mode, at Pout=7dBm mid power modehigh power mode, at Pout=17dBm deg deg Ruggedness Pout<28.5dBm, Pin<10dBm, All phase High Power Mode 10:1 VSWR Coupling factor RF Out to CPL port 20 dB Daisy Chain Insertion Loss ISO port to CPL port, Ven=Low 0.25 dB
All dimensions ae in millimeter Marking Specifi cation Manufacturing Part Number Lot Number P Manufacturing Info YY Manufacturing Year WW Work Week QAAAAA Assembly Lot Number Pin 1 Mark A5008 PYYWW QAAAAA 3 ± 0.1 3 ± 0.1 Pin 1 Mark 0.5 0.9 ± 0.1
Solder Paste Stencil Aperture PCB Design Guidelines The recommended PCB land pattern is shown in fi gures on the left side. The substrate is coated with solder mask between the I/O and conductive paddle to protect the gold pads from short circuit that is caused by solder bleeding/bridging. Stencil Design Guidelines A properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the PCB pads. The recommended stencil layout is shown here. Reducing the stencil opening can potentially generate more voids. On the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the I/O pads or conductive paddle to adjacent I/O pads. Considering the fact that solder paste thickness will directly aff ect the quality of the solder joint, a good choice is to use laser cut stencil composed of 0.100mm(4mils) or 0.127mm(5mils) thick stainless steel which is capable of producing the required fi ne stencil outline. 0.65 0.45 0.50 0.60 1.50 1.30 0.525 0.55 0.45 1.10 1.10 0.60 0.35 0.475 0.30 0.60 0.35 0.55 0.45 on 0.5mm pitch Ø 0.3mm 0.475 connected to a inner layer through a via hole for a better isolation between CPL_IN(ISO) and RFout
Evaluation Board Schematic Evaluation Board Description
1 Vcc1
2 RF In
3 Vbp
4 Vmode
5 Ven
2.2uF C6 C7 680pF 680pF 2.2uF Vbp 100pF ISO 8 RF Out Coupler 50ohm C1C2C3 C4 C6 C5 C7 A5008 PYYWW QAAAAA
A0 3.40±0.10 B0 3.40±0.10 K0 1.35±0.10 D0 1.55±0.05 D1 1.60±0.10 P0 4.00±0.10 P1 8.00±0.10 Annote Millimeter P2 2.00±0.05 P10 40.00±0.20 E 1.75±0.10 F 5.50±0.05 W 12.00±0.30 T 0.30±0.05 Tape and Reel Format – 3 mm x 3 mm A5008 PYYWW QAAAAA
Plastic Reel Format (all dimensions are in millimeters) Reel Drawing NOTES: 1. Reel shall be labeled with the following information (as a minimum). a. manufacturers name or symbol b. Avago Technologies part number c. purchase order number d. date code e. quantity of units 2. A certificate of compliance (c of c) shall be issued and accompany each shipment of product. 3. Reel must not be made with or contain ozone depleting materials. 4. All dimensions in millimeters (mm) 50 min. 12.4 +2.0 -0.0 18.4 max. min wide (ref) Slot for carrier tape insertion for attachment to reel hub (2 places 180° apart) BACK VIEW FRONT VIEW 178 Shading indicates thru slots +0.4 -0.2 21.0 ± 0.8 13.0 ± 0.2 1.5 min.
ESD (Electrostatic Discharge) Electrostatic discharge occurs naturally in the environ- ment. With the increase in voltage potential, the outlet of neutralization or discharge will be sought. If the acquired discharge route is through a semiconductor device, de- structive damage will result. ESD countermeasure methods should be developed and used to control potential ESD damage during handling in a factory environment at each manufacturing site. MSL (Moisture Sensitivity Level) Plastic encapsulated surface mount package is sensitive to damage induced by absorbed moisture and temperature. Avago Technologies follows JEDEC Standard J-STD 020B. Each component and package type is classifi ed for moisture sensitivity by soaking a known dry package at Moisture Classifi cation Level and Floor Life MSL Level Floor Life (out of bag) at factory ambient =< 30°C/60% RH or as stated
1 Unlimited at =< 30°C/85% RH
6 Mandatory bake before use. After bake, must be refl owed within the time limit specifi ed on the label Note : 1. The MSL Level is marked on the MSL Label on each shipping bag. various temperatures and relative humidity, and times. After soak, the components are subjected to three con- secutive simulated refl ows. The out of bag exposure time maximum limits are deter- mined by the classifi cation test describe below which cor- responds to a MSL classifi cation level 6 to 1 according to the JEDEC standard IPC/JEDEC J-STD-020B and J-STD-033. ACPM-5008-TR1 is MSL3. Thus, according to the J-STD-033 p.11 the maximum Manufacturers Exposure Time (MET) for this part is 168 hours. After this time period, the part would need to be removed from the reel, de-taped and then re-baked. MSL classifi cation refl ow temperature for the ACPM-5008-TR1 is targeted at 260°C +0/-5°C. Figure and table on next page show typical SMT profi le for maximum temperature of 260 +0/-5°C.
Refl ow Profi le Recommendations Typical SMT Refl ow Profi le for Maximum Temperature = 260 +0/-5°C Time Temperature Tp TL tp tL t 25°C to Peak Ramp-up ts Tsmin Ramp-down Preheat Critical Zone TL to Tp Tsmax Typical SMT Refl ow Profi le for Maximum Temperature = 260 +0/-5°C Profi le Feature Sn-Pb Solder Pb-Free Solder Average ramp-up rate (TL to TP) 3°C/sec max 3°C/sec max Preheat – Temperature Min (Tsmin) – Temperature Max (Tsmax) – Time (min to max) (ts) 100°C 150°C 60-120 sec 150°C 200°C 60-120 sec Tsmax to TL – Ramp-up Rate 3°C/sec max Time maintained above: – Temperature (TL) – Time (TL) 183°C 60-150 sec 217°C 60-150 sec Peak temperature (Tp) 240 +0/-5°C 260 +0/-5°C Time within 5°C of actual Peak Temperature (tp) 10-30 sec 20-40 sec Ramp-down Rate 6°C/sec max 6°C/sec max Time 25°C to Peak Temperature 6 min max. 8 min max.
Packages described in this document must be stored in sealed moisture barrier, antistatic bags. Shelf life in a sealed moisture barrier bag is 12 months at <40°C and 90% relative humidity (RH) J-STD-033 p.7. Out-of-Bag Time Duration After unpacking the device must be soldered to the PCB within 168 hours as listed in the J-STD-020B p.11 with factory conditions <30°C and 60% RH. Baking It is not necessary to re-bake the part if both conditions (storage conditions and out-of bag conditions) have been satisfi ed. Baking must be done if at least one of the con- ditions above have not been satisfi ed. The baking condi- tions are 125°C for 12 hours J-STD-033 p.8. CAUTION Tape and reel materials typically cannot be baked at the temperature described above. If out-of-bag exposure time is exceeded, parts must be baked for a longer time at low temperatures, or the parts must be de-reeled, de-taped, re-baked and then put back on tape and reel. (See moisture sensitive warning label on each shipping bag for information of baking). Board Rework Component Removal, Rework and Remount If a component is to be removed from the board, it is recommended that localized heating be used and the maximum body temperatures of any surface mount component on the board not exceed 200°C. This method will minimize moisture related component damage. If any component temperature exceeds 200°C, the board must be baked dry per 4-2 prior to rework and/or component removal. Component temperatures shall be measured at the top center of the package body. Any SMD packages that have not exceeded their fl oor life can be exposed to a maximum body temperature as high as their specifi ed maximum refl ow temperature. Removal for Failure Analysis Not following the above requirements may cause moisture/refl ow damage that could hinder or com- pletely prevent the determination of the original failure mechanism. Baking of Populated Boards Some SMD packages and board materials are not able to withstand long duration bakes at 125°C. Examples of this are some FR-4 materials, which cannot withstand a 24 hr bake at 125°C. Batteries and electrolytic capacitors are also temperature sensitive. With component and board temperature restrictions in mind, choose a bake tem- perature from Table 4-1 in J-STD 033; then determine the appropriate bake duration based on the component to be removed. For additional considerations see IPC-7711 and IPC-7721. Derating due to Factory Environmental Conditions Factory fl oor life exposures for SMD packages removed from the dry bags will be a function of the ambient envi- ronmental conditions. A safe, yet conservative, handling approach is to expose the SMD packages only up to the maximum time limits for each moisture sensitivity level as shown in next table. This approach, however, does not work if the factory humidity or temperature is greater than the testing conditions of 30°C/60% RH. A solution for addressing this problem is to derate the exposure times based on the knowledge of moisture diff usion in the component package materials ref. JESD22-A120). Recommended equivalent total fl oor life exposures can be estimated for a range of humidities and temperatures based on the nominal plastic thickness for each device. Table on next page lists equivalent derated fl oor lives for humidities ranging from 20-90% RH for three tempera- ture, 20°C, 25°C, and 30°C. Table on next page is applicable to SMDs molded with novolac, biphenyl or multifunctional epoxy mold compounds. The following assumptions were used in cal- culating this table: 1. Activation Energy for diff usion = 0.35eV (smallest known value). 2. For ≤60% RH, use Diff usivity = 0.121exp ( -0.35eV/kT) mm2/s (this used smallest known Diff usivity @ 30°C). 3. For >60% RH, use Diff usivity = 1.320exp ( -0.35eV/kT) mm2/s (this used largest known Diff usivity @ 30°C).
For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. AV02-2480EN - August 5, 2011 Recommended Equivalent Total Floor Life (days) @ 20°C, 25°C & 30°C, 35°C For ICs with Novolac, Biphenyl and Multifunctional Epoxies (Refl ow at same temperature at which the component was classifi ed) Maximum Percent Relative Humidity Maximum Percent Relative Humidity Package Type and Body Thickness Moisture Sensitivity Level 5% 10% 20% 30% 40% 50% 60% 70% 80% 90% Body Thickness ≥3.1 mm Including PQFPs >84 pin, PLCCs (square) All MQFPs or All BGAs ≥1 mm Level 2a ∞ 124 167 231 103 35°C 30°C 25°C 20°C Level 3 ∞ 35°C 30°C 25°C 20°C Level 4 ∞ 35°C 30°C 25°C 20°C Level 5 ∞ 35°C 30°C 25°C 20°C Level 5a ∞ 35°C 30°C 25°C 20°C Body 2.1 mm ≤ Thickness <3.1 mm including PLCCs (rectangular) 18-32 pin SOICs (wide body) SOICs ≥20 pins, PQFPs ≤80 pins Level 2a ∞ 148 35°C 30°C 25°C 20°C Level 3 ∞ 35°C 30°C 25°C 20°C Level 4 ∞ 35°C 30°C 25°C 20°C Level 5 ∞ 35°C 30°C 25°C 20°C Level 5a ∞ 0.5 0.5 0.5 0.5 35°C 30°C 25°C 20°C Body Thickness <2.1 mm including SOICs <18 pin All TQFPs, TSOPs or All BGAs <1 mm body thickness Level 2a ∞ 0.5 0.5 35°C 30°C 25°C 20°C Level 3 ∞ 0.5 0.5 35°C 30°C 25°C 20°C Level 4 ∞ 0.5 0.5 35°C 30°C 25°C 20°C Level 5 ∞ 0.5 0.5 35°C 30°C 25°C 20°C Level 5a ∞ 0.5 0.5 0.5 35°C 30°C 25°C 20°C