ACPL-071L

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Technical content

Features

 +3.3V and +5 V CMOS compatibility  30 ns max. pulse width distortion  40 ns max. propagation delay (3.3V supply voltage)  30 ns max. propagation delay skew  High speed: 15 MBd min.  10 kV/µs minimum common mode rejection  –40°C to 105°C temperature range  Safety and regulatory approvals: – UL recognized: 3750 V rm s for 1 min. per UL 1577 – CSA component acceptance Notice #5 – IEC/EN/DIN EN 60747-5-5 CAUTION! It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The components featured in this data sheet are not to be used in military or aerospace applications or environments. ACPL-071L and ACPL-074L Single-Channel and Dual-Channel High-Speed 15-MBd CMOS Optocoupler

ACPL-071L and ACPL-074L Data Sheet Single-Channel and Dual-Channel High-Speed 15-MBd C MOS Optocoupler Functional Diagram NOTE: A 0.1-µF bypass capacitor must be connected as close as possible between pins VDD and GND. Truth Table LED VO, OUTPUT OFF H ON L NC ANODE CATHODE NC 4 ACPL-071L SHIELD VDD NC Vo GND5

1 VDD

ACPL-071L and ACPL-074L Data Sheet Single-Channel and Dual-Channel High-Speed 15-MBd C MOS Optocoupler

Ordering Information

ACPL-071L/074L are UL Recognized with 3750 Vrms for 1 minute per UL1577. To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACPL-071L-500E to order product of Small Outline SO-8 package in Tape and Reel packaging in RoHS compliant. Example 2: ACPL-074L-000E to order product of Small Outline SO-8 package in tube packaging and RoHS compliant. Option data sheets are available. Contact your Broadcom sales representative or authorized distributor for information. Reflow Soldering Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-halide flux should be used. Regulatory Information The ACPL-071L and ACPL-074L have been approved by the following organizations: Part Number Option Package Surface Mount Tape and Reel IEC/EN/DIN EN 60747-5-5 QuantityRoHS Compliant ACPL-071L -000E SO-8 X 100 per tube -500E X X 1500 per reel -060E X X 100 per tube -560E X X X 1500 per reel ACPL-074L -000E SO-8 X 100 per tube -500E X X 1500 per reel -060E X X 100 per tube -560E X X X 1500 per reel UL Recognized under UL 1577, component recognition program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA88324. IEC/EN/DIN EN 60747-5-5

ACPL-071L and ACPL-074L Data Sheet Single-Channel and Dual-Channel High-Speed 15-MBd C MOS Optocoupler Package Dimensions ACPL-071L and ACPL-074L (Small Outline S0-8 Package) 8765 4321 5.994 ± 0.203 (0.236 ± 0.008) 0.406 ± 0.076 (0.050)BSC 5.080 ± 0.127 (0.200 ± 0.005) 3.175 ± 0.127 (0.060) 45° X 0.432 (0.017) 0.228 ± 0.025 (0.009 ± 0.001) 0.305 (0.012)MIN. 0.203 ± 0.102 (0.008 ± 0.004) 0 ~ 7° YYWW• NNNN Z EEE TEST RATING CODEDEVICE PART NUMBER LEAD-FREE LOT ID DATE CODE PIN 1 LAND PATTERN RECOMMENDATION 7.49 (0.295) 1.91 (0.075) 0.64 (0.025) 3.95 (0.156) 1.27 (0.5) * Total package length (inclusive of mold flash) Dimensions in Millimeters (Inches). Note: Floating lead protrusion is 0.15 mm (6 mils) max. Lead coplanarity = 0.10 mm (0.004 inches) max. Option number 500 not marked.

ACPL-071L and ACPL-074L Data Sheet Single-Channel and Dual-Channel High-Speed 15-MBd C MOS Optocoupler Insulation and Safety Related Specifications IEC/EN/DIN EN 60747-5-5 Insulation Characteristics NOTE: These optocouplers are suitable for safe electrical isolation only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. Parameter Symbol Value Units Conditions Minimum External Air Gap (Clearance) L(I01) 4.9 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(I02) 4.8 mm Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic Gap (Internal Clearance) 0.08 mm Insulation thickness betw een emitter and detector; also known as distance through insulation. Tracking Resistance (Comparative Tracking Index) CTI 175 Volts DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Description Symbol Option 060 Unit Installation classification per DIN VDE 0110, Table 1 for rated mains voltage ≤ 150 Vrms I – IV for rated mains voltage ≤ 300 Vrms I – IV for rated mains voltage ≤ 600 Vrms I – III Climatic Classification 40/85/21 Pollution Degree (DIN VDE 0110/39) 2 Maximum Working Insulation Voltage V IORM 567 Vpeak Input to Output Test Voltage, Method b VIORM × 1.875 = VPR, 100% Production Test with tm = 1s, Partial discharge < 5 pC VPR 1063 Vpeak Input to Output Test Voltage, Method a VIORM × 1.6 = VPR, Type and Sample Test, tm=10s, Partial discharge < 5 pC VPR 907 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60s) V IOTM 6000 Vpeak Safety-limiting values – maximum values allowed in the event of a failure. Case Temperature T S 150 °C Input Current I S, INPUT 150 mA Output Power P S, OUTPUT 600 mW Insulation Resistance at TS, VIO = 500 V R S ≥ 109 Ω

ACPL-071L and ACPL-074L Data Sheet Single-Channel and Dual-Channel High-Speed 15-MBd C MOS Optocoupler Absolute Maximum Ratings Recommended Operating Conditions Electrical Specifications All typical specifications are at TA = +25°C, VDD = +3.3V. Parameter Symbol Min. Max. Units Storage Temperature T S –55 +125 °C Ambient Operating Temperature T A –40 +105 °C Supply Voltages V DD 06 . 0 V o l t s Output Voltage V O –0.5 V DD +0.5 Volts Average Forward Input Current I F —2 0 . 0 m A Average Output Current I o —1 0 . 0 m A Input Power Dissipation P I —3 5 m W Output Power Dissipation P O —1 0 0 m W Lead Solder Temperature 260°C fo r 10s., 1.6 mm below seating plane Solder Reflow Temperature Profile See Reflow Soldering Profile Parameter Symbol Min. Max. Units Ambient Operating Temperature T A –40 +105 °C Supply Voltages V DD 4.5 5.5 V 3.0 3.6 V Input Current (ON) I F 12 18 mA Supply Voltage Slew Ratea a. Slew rate of supply voltage ramping is recommended to ensure no glitch more than 1V to appear at the output pin. SR 0.5 500 V/ms Parameter Symbol Part Number Min. Typ. Max. Units Test Conditions Input Forward Voltage V F 1.3 1.5 1.8 V I F = 14 mA Input Reverse Breakdown Voltage BV R 5.0 — — V I R = 10 µA Logic High Output Voltage V OH VDD – 1 VDD – 0.3 — V I F = 0, IO = –4 mA, VDD = 3.3V VDD – 1 VDD – 0.2 — V I F = 0, IO = –4 mA, VDD = 5V Logic Low Output Voltage V OL —0 . 3 5 0 . 8V I F = 14 mA, IO = 4 m A, VDD = 3.3V —0 . 2 0 . 8 V I F = 14 mA, IO = 4 mA, VDD = 5V Input Threshold Current I TH —4 . 5 8 . 8 m A I OL = 20 µA Logic Low Output Supply Current I DDL ACPL-071L — 4.1 6.0 mA I F = 14 mA ACPL-074L — 8.3 12.0 mA I F = 14 mA Logic Low Output Supply Current I DDH ACPL-071L — 3.8 6.0 mA I F = 0 ACPL-074L — 7.6 12.0 mA I F = 0

ACPL-071L and ACPL-074L Data Sheet Single-Channel and Dual-Channel High-Speed 15-MBd C MOS Optocoupler Switching Specifications All typical specifications are at TA = +25°C, VDD = +3.3V. Package Characteristics All Typical at TA = 25°C. Parameter Symbol Min. Typ. Max. Units Test Conditions Propagation Delay Time to Logic Low Outputa a. tPHL propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level of the rising edge of the VO signal. tPHL —2 9 4 0 n s I F = 14 mA, CL = 15 pF, VDD = 3.3V, CMOS Signal Levels — — 50 ns I F = 14 mA, CL = 15 pF, VDD = 5V, CMOS Signal Levels Propagation Delay Time to Logic High Outputa tPLH —2 2 4 0 n s I F = 14 mA, CL = 15 pF, VDD = 3.3V, CMOS Signal Levels — — 50 ns I F = 14 mA, CL = 15 pF, VDD = 5V, CMOS Signal Levels Pulse Width t PW 66.7 — — ns Pulse Width Distortionb b. PWD is defined as |tPHL – tPLH|. |PWD | 0 7 25 ns I F = 14 mA, CL = 15 pF, VDD = 3.3V, CMOS Signal Levels — — 30 ns I F = 14 mA, CL = 15 pF, VDD = 5V, CMOS Signal Levels Propagation Delay Skewc c. t PSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. tPSK — — 30 ns I F = 14 mA, CL = 15 pF, CMOS Signal Levels Output Rise Time (10% – 90%) t R —2 0 — n s I F = 14 mA, CL = 15 pF, CMOS Signal Levels Output Fall Time (90% - 10%) t F —2 5 — n s I F = 14 mA, CL = 15 pF, CMOS Signal Levels Common Mode Transient Immunity at Logic High Outputd d. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. | CMH | 10 15 — kV/µs V CM = 1000 V, TA = 25°C, IF = 0 mA Common Mode Transient Immunity at Logic Low Outpute e. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state. | CML | 10 15 — kV/µs V CM = 1000 V, TA = 25°C, IF = 14 mA Parameter Symbol Min. Typ. Max. Units Test Conditions Input-Output Insulation II-O — — 1.0 µA 45% RH, t = 5s, V I-O = 3 kV DC, TA = 25°C Input-Output Momentary Withstand Voltage VISO 3750 — — Vrms RH 50%, t = 1 min., T A = 25°C Input-Output Resistance R I-O — 1012 —Ω V I-O = 500 V dc Input-Output Capacitance C I-O — 0.6 — pF f = 1 MHz, T A = 25°C

ACPL-071L and ACPL-074L Data Sheet Single-Channel and Dual-Channel High-Speed 15-MBd C MOS Optocoupler Broadcom AV02-0963EN Speed Improvement A peaking capacitor can be placed across the input current limit resistor (Figure 9) to achieve enhanced speed performance. The value of the peaking cap is dependent to the rise and fall time of the input signal and supply voltages and LED input driving current (If). Figure 10 shows significant improvement of propagation delay and pulse with distortion with added peak capacitor at driving current of 14 mA and 3.3V or 5V power supply. Figure 10: Improvement of tp and PWD with Added 100 pF Peaking Capacitor in Parallel of Input Limiting Resistor Figure 11: Test circuit for Common Mode Transient Immunity and Typical Waveforms. Rtotal is the total resistance of the driver output impedence (which is assumed to be 50Ω) and the limiting resistor (Rtotal = Rdrv + Rlimit). TA - TEMPERATURE - o C tp - PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION -ns TA - TEMPERATURE - o C tp - PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION -ns 0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 -40 -20 0 20 40 60 80 100 tPHL tPLH tPLH tPHL |PWD| With peaking cap Without peaking cap 0.00 5.00 10.00 15.00 20.00 25.00 30.00 -40 -20 0 20 40 60 80 100 tPHL tPLHtPLH tPHL |PWD| With peaking cap Without peaking cap GND2 VDD2 VO monitoring note VCM 0.1μF Rlimit SHIELD IF A B + -Pulse Gen. Zo=50Ω VO GND2 OV (min.) VDD

0 V SWITCH AT A: I = 0 mAF

SWITCH AT B: I = 14 mAF CMV HCM CM L OV (max.) CMV (PEAK) VO

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