ACPL-064L BOARDCOM | Alldatasheet

Document overview

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Technical content

Features

 Low IDD current: 1.3 mA/channel maximum  Low input current: 1.6 mA  Built-in slew-rate controlled outputs  20 kV/μs minimum Common-Mode Rejection (CMR) at VCM = 1000V  High speed: 10 MBd minimum  Guaranteed AC and DC performance over wide temperature: –40°C to +105°C  Wide package selection: SO-5, SO-8, stretched SO-6, and stretched SO-8  Safety approval — UL 1577 recognized: 3750Vrms for 1 minute for ACPL-064L/M61L and 5000Vrms for 1 minute for ACPL-W61L/K64L — CSA approval — IEC/EN/DIN EN 60747-5-5 approval for Reinforced Insulation  RoHS-compliant

Applications

 Communication interfaces: RS485, CANBus, and I2C  Microprocessor system interfaces  Digital isolation for A/D and D/A converters CAUTION It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The components featured in this data sheet are not to be used in military or aerospace applications or environments. 5NC* Anode Cathode VDD GND Vo SHIELD ACPL-M61L Anode Cathode VDD GND Vo A 0.1 μF bypass capacitor must be connected between pins VDD and GND.

1 VDD

(POSITIVE LOGIC) LED OUTPUT ON L OFF H ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Low-Power 10-MBd Digital CMOS Optocouplers Data Sheet

  • 2 - ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet

Ordering Information

The ACPL-064L and ACPL-M61L are UL recognized with an isolation voltage of 3750Vrms for 1 minute per UL1577. The ACPL-W61L and ACPL-K64L are UL recognized with an isolation voltage of 5000Vrms for 1 minute per UL1577. All devices are RoHS-compliant. To form an ordering part number, choose a part number from the part number column and combine it with the desired option from the RoHS option column. Example: Part number ACPL-M61L-560E describes an optocoupler with a surface mount SO-5 package; delivered in Tape and Reel with 1500 parts-per-reel; with IEC/EN/DIN EN 60747-5-5 Safety Approval; and full RoHS compliance. Option data sheets are available. Contact your Broadcom sales representative or authorized distributor for information. Part Number Option RoHS-Compliant Package Surface Mount Tape and Reel UL1577 5000 Vrms /1 Minute Rating IEC/EN/DIN EN 60747-5-5 Quantity ACPL-M61L -000E SO-5 X 100 per tube -060E X X 100 per tube -500E X X 1500 per reel -560E X X X 1500 per reel ACPL-064L -000E SO-8 X 100 per tube -060E X X 100 per tube -500E X X 1500 per reel -560E X X X 1500 per reel ACPL-W61L -000E Stretched S06 X X 100 per tube -060E X X X 100 per tube -500E X X X 1000 per reel -560E XXXX 1 0 0 0 p e r r e e l ACPL-K64L -000E Stretched S08 XX 8 0 p e r t u b e -060E X X X 80 per tube -500E X X X 1000 per reel -560E XXXX 1 0 0 0 p e r r e e l

  • 3 - ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Package Outline Drawings 8765 4321 5.994 ± 0.203 (0.236 ± 0.008) 0.406 ± 0.076 (0.050)BSC 5.080 ± 0.127 (0.200 ± 0.005) 3.175 ± 0.127 (0.060) 45° X 0.432 (0.017) 0.228 ± 0.025 (0.009 ± 0.001) 0.305 (0.012)MIN. 0.203 ± 0.102 (0.008 ± 0.004) 0 ~ 7° YYWW• NNNN Z EEE TEST RATING CODEDEVICE PART NUMBER LEAD-FREE LOT ID DATE CODE PIN 1 LAND PATTERN RECOMMENDATION 7.49 (0.295) 1.91 (0.075) 0.64 (0.025) 3.95 (0.156) 1.27 (0.5) * Total package length (inclusive of mold flash) Dimensions in Millimeters (Inches). Note: Floating lead protrusion is 0.15 mm (6 mils) max. Lead coplanarity = 0.10 mm (0.004 inches) max. Option number 500 not marked. 7.0 ± 0.2 (0.276 ± 0.008) 2.5 ± 0.1 (0.098 ± 0.004) 0.102 ± 0.102 (0.004 ± 0.004) 4.4 ± 0.1 (0.173 ± 0.004) 1.27 (0.050)BSC 0.15 ± 0.025 (0.006 ± 0.001) 0.71 (0.028) MIN 0.4 ± 0.05 (0.016 ± 0.002) 3.6 ± 0.1* (0.142 ± 0.004) Dimensions in millimeters (inches). Note: Foating Lead Protrusion is 0.15 mm (6 mils) max. * Maximum Mold flash on each side is 0.15 mm (0.006). 7° MAX. MAX. LEAD COPLANARITY = 0.102 (0.004) 8.26 (0.325) 1.80 (0.071) 2.54 (0.10) 1.27 (0.05) 0.64 (0.025) 4.39 (0.17) LAND PATTERN RECOMMENDATION 0.33 (0.013) YYWW PIN 1 DOT NNNN DEVICE PART NUMBER DATE CODE Z TEST RATING CODE EEE LOT ID LEAD FREE
  • 4 - ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet ACPL-W61L Stretched SO-6 Package ACPL-K64L Stretched SO-8 Package 4.580±0.254 (0.180±0.010) 45° 0.381±0.127 (0.015±0.005) 1.27 (0.050) BSG 0.20±0.10 (0.008±0.004) 0.45 (0.018) 0.750±0.250 (0.0295±0.010) 11.50±0.250 (0.453±0.010) 6.807 0.268 Dimensions in Millimeters (Inches). Lead coplanarity = 0.1 mm (0.004 inches). 12.65 (0.498) LAND PATTERN RECOMMENDATION 3.180±0.127 (0.125±0.005) 1.590±0.127 (0.063±0.005)7° 1.91 (0.075) 321 456 0.76 (0.030) +0.127 +0.005 - 0.000 )( PART NUMBER DATE CODE RoHS-COMPLIANCE INDICATOR NNNN YYWW EEE Lot ID 0.381±0.13 321 5678 5.850±0.254 (0.230±0.010) Dimensions in Millimeters (Inches). Lead coplanarity = 0.1 mm (0.004 inches). 7° 45° 0.254±0.100 (0.010±0.004) 0.450 (0.018) 0.750±0.250 (0.0295±0.010) 11.5±0.250 (0.453±0.010) 1.590±0.127 (0.063±0.005) PART NUMBER RoHS-COMPLIANCE INDICATOR 6.807±0.127 (0.268±0.005) 3.180±0.127 (0.125±0.005) NNNN YYWW EEE DATE CODE Lot ID 12.650 (0.5) 1.905 (0.1) LAND PATTERN RECOMMENDATION
  • 5 - ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Reflow Soldering Profile The recommended reflow soldering conditions are per JEDEC Standard J-STD-020 (latest revision). Non-halide flux should be used. Regulatory Information The ACPL-064L, ACPL-M61L, ACPL-W61L, and ACPL-K64L are approved by the following organizations:  IEC/EN/DIN EN 60747-5-5 (Option 060 only)  UL — Approval under UL 1577 component recognition program up to VISO = 3750Vrms for the ACPL-M61L/064L and VISO = 5000Vrms for the ACPL-W61L/K64L File E55361.  CSA — Approval under CSA Component Acceptance Notice #5, File CA 88324. Insulation and Safety Related Specifications Parameter Symbol ACPL-064L ACPL-M61L ACPL-W61L ACPL-K64L Unit Conditions Minimum External Air Gap (External Clearance) L(101) 4.9 5 8 mm Measured from in put terminals to output terminals, shortest distance through air. Minimum External Tracking (External Creepage) L(102) 4.8 5 8 mm Measured from in put terminals to output terminals, shortest distance path along body. Minimum Internal Plastic Gap (Internal Clearance) 0.08 0.08 0.08 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. Tracking Resistance (Comparative Tracking Index) CTI 175 175 175 V DIN IEC 112/VDE 0303 Part 1. Isolation Group IIIa IIIa IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
  • 6 - ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet IEC/EN/DIN EN 60747-5-5 Insulation Characteristicsa (Option 060) NOTE These optocouplers are suitable for safe electrical isolation only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. Description Symbol Characteristic UnitACPL-064L/ ACPL-M61L ACPL-W61L/ ACPL-K64L Installation classification per DIN VDE 0110/39, Table 1 for rated mains voltage ≤ 150Vrms for rated mains voltage ≤ 300Vrms for rated mains voltage ≤ 600Vrms for rated mains voltage ≤ 1000Vrms I – IV I – IV I – III I – IV I – IV I – IV I – III Climatic Classification 55/105/21 55/105/21 Pollution Degree (DIN VDE 0110/39) 2 2 Maximum Working Insulation Voltage V IORM 567 1140 V peak Input to Output Test Voltage, Method ba VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial discharge < 5 pC a. Refer to the optocoupler section of the Isolation and Control Co mponents Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles. VPR 1063 2137 V peak Input to Output Test Voltage, Method aa VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec, Partial discharge < 5 pC VPR 907 1824 V peak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) V IOTM 6000 8000 V peak Safety-Limiting Values – maximum values allowed in the event of a failure Case Temperature Input Currentb Output Powerb b. Refer to the following figures for dependence of P S and IS on ambient temperature: TS IS, INPUT PS, OUTPUT 150 150 600 175 230 600 mA mW Insulation Resistance at TS, VIO = 500V R S >109 >109 Ω TS – CASE TEMPERATURE (°C) 400 600 200 100 300 500 700 PS (mW) IS (mA) Surface Mount SO-8 Product 200 400 600 800 1000 0 25 50 75 100 125 150 175 TS – CASE TEMPERATURE (°C) PS (mW) IS (mA) POWER OUTPUT – PS, INPUT CURRENT – IS Surface Mount SSO-6/SSO-8 Product POWER OUTPUT – PS, INPUT CURRENT – IS 0 25 50 75 100 125 150 175 200
  • 7 - ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Absolute Maximum Ratings Recommended Operating Conditions Parameter Symbol Min Max Unit Condition Storage Temperature T S –55 +125 °C Operating Temperature T A –40 +105 °C Reverse Input Voltage V R —5V Supply Voltage V DD —6 . 5V Average Forward Input Current I F —8 m A Peak Forward Input Current (IF at 1 μs pulse width, <10% duty cycle) IF(TRAN) — 1 A ≤1-μs Pulse Width, <300 pulses/second 80 mA ≤1-μs Pulse Width, <10% Duty Cycle Output Current I O —1 0 m A Output Voltage V O –0.5 V DD + 0.5 V Input Power Dissipation P I —1 4 m W Output Power Dissipation P O —2 0 m W Lead Solder Temperature T LS — 260°C for 10 sec., 1.6 mm below seating plane Solder Reflow Temperature Profile See Package Outline Drawings section. Parameter Symbol Min Max Unit Operating Temperature T A –40 +105 °C Input Current, Low Level I FL 0 250 μA Input Current, High Level I FH 1.6 6.0 mA Power Supply Voltage V DD 2.7 5.5 V Forward Input Voltage V F (OFF) —0 . 8 V
  • 8 - ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Electrical Specifications (DC) Over the recommended temperature (TA = –40°C to +105°C) and supply voltage (2.7V ≤ VDD ≤ 5.5V). All typical specifications are at VDD = 5V and TA = 25°C. Switching Specifications (AC) Over the recommended temperature (TA = –40°C to +105°C) and supply voltage (2.7V ≤ VDD ≤ 5.5V). All typical specifications are at VDD = 5V and TA = 25°C. Parameter Symbol Channel Min Typ Max Unit Test Conditions Input Forward Voltage V F 0.95 1.3 1.7 V I F = 2 mA; Figure 1 and Figure 2 Input Reverse Breakdown Voltage BV R 35 — V I R = 10 μA Logic High Output Voltage V OH VDD – 0.1 V DD —V I F = 0 mA, VI = 0V (RT = 1.68 kΩ) or (RT = 870Ω), IO = –20 μA VDD – 1.0 V DD —V I F = 0 mA, VI = 0V (RT = 1.68 kΩ) or (RT = 870Ω), IO = –3.2 mA Logic Low Output Voltage V OL — 0.03 0.1 V I F = 2 mA, VI = 5V (RT = 1.68 kΩ) or VI = 3.3V (RT = 870Ω), IO = 20 μA — 0.18 0.4 V I F = 2 mA, VI = 5V (RT = 1.68 kΩ) or VI = 3.3V (RT = 870Ω), IO = 3.2 mA Input Threshold Current I TH —0 . 7 1 . 3 m A Figure 3 Logic Low Output Supply Current I DDL Single — 0.8 1.3 mA Figure 4 Dual — 1.6 2.6 Logic High Output Supply Current I DDH Single — 0.8 1.3 mA Figure 5 Dual — 1.6 2.6 Input Capacitance C IN —6 0 — p F f = 1 M H z , V F = 0V Input Diode Temperature Coefficient ΔVF/ΔTA —– 1 . 6 — m V / ° C I F = 2 mA Parameter Symbol Min Typ Max Unit Test Conditions Propagation Delay Time to Logic Low Outputa tPHL —4 6 8 0n s I F = 2 mA, VI = 5V, RT = 1.68 kΩ, CL = 15 pF, CMOS Signal Levels. IF = 2 mA, VI = 3.3V, RT = 870Ω, CL = 15 pF, CMOS Signal Levels. Figure 6 and Figure 7 Propagation Delay Time to Logic High Outputa tPLH —4 0 8 0n s Pulse Width t PW 100 — — ns Pulse Width Distortionb PWD — 6 30 ns Propagation Delay Skewc tPSK —3 0 n s Output Rise Time (10% to 90%) t R —1 2 — n s I F = 2 mA, VI = 5V, RT = 1.68 kΩ, CL = 15 pF, CMOS Signal Levels. —1 0 — n s I F = 2 mA, VI = 3.3V, RT = 870Ω, CL = 15 pF, CMOS Signal Levels. Output Fall Time (90% to 10%) t F —1 2 — n s I F = 2 mA, VI = 5V, RT = 1.68 kΩ, CL = 15 pF, CMOS Signal Levels. —1 0 — n s I F = 2 mA, VI = 3.3V, RT = 870Ω, CL = 15 pF, CMOS Signal Levels.
  • 12 - ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Supply Bypassing, LED Bias Resistors, and PC Board Layout The ACPL-x6xL optocouplers are extremely easy to use and feature high-speed, push-pull CMOS outputs. Pull-up resistors are not required. The external components required for proper operation are the input limiting resistors and the output bypass capacitor. Capacitor values should be 0.1 μF. For each capacitor, the total lead length connecting the capacitor to the VDD and GND pins should not exceed 20 mm. Figure 8 Recommended PCB Layout and Input Current-Limiting Resistor Selection For ACPL-M61L/W61L: VI = 3.3V: R1 = 510Ω ± 1%, R2 = 360Ω ± 1% VI = 5.0V: R1 = 1000Ω ± 1%, R2 = 680Ω ± 1% RT = R1 + R2 R1/R2 = 1.5 For ACPL-064L/K64L: VI = 3.3V: R1 = 430Ω ± 1%, R2 = 430Ω ± 1% VI = 5.0V: R1 = 845Ω ± 1%, R2 = 845Ω ± 1% RT = R1 + R2 R1/R2 = 1 IF GND1 Vo VDD C = 0.1 μF GND2 VI ACPL-M61L ACPL-W61L ACPL-064L/K64L IF GND1 Vo VDD C = 0.1 μF GND2 VI 2 7 81IF GND1 Vo1 VDD C = 0.1 μF GND2 VI IF GND2 VI Vo2 3.3V/5V Anode Cathode VDD GND Vo Shield BA IF VCM Pulse Gen C = 0.1 μF VO GND OV (min.) VDD 0 V SWITCH AT A: I = 0 mAF SWITCH AT B: I = 2 mAF CMV HCM CM L OV (max.) CMV (PEAK) VOOutput Monitoring node
  • 14 - ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Optocoupler CMR Performance The principal protection against common-mode noise comes from the fundamental isolation properties of the optocoupler, and this in turn is directly related to the Input-Output leakage capacitance of the optocoupler. To provide maximum protection to circuitry connected to the input or output of the optocoupler, the leakage capacitance is minimized by having large separation distances at all points in the optocoupler construction, including the LED/photodiode interface. In addition to the optocouplers' basic physical construction, additional circuit design steps mitigate the effects of common-mode noise. The most important of these is the Faraday shield on the photodetector stage. A Faraday shield is effective in optocouplers because the internal modulation frequency (light) is many orders of magnitude higher than the common-mode noise frequency. Improving CMR Performance at the Application Level In an end application, it is desirable that the optocouplers' common-mode isolation be as close as possible to that indicated in the data sheet specifications. The first step in meeting this goal is to ensure maximum separation between PCB interconnects on either side of the optocoupler is maintained and that PCB tracks beneath the optocoupler are avoided. It is inevitable that a certain amount of CMR noise will be coupled into the inputs and this can potentially result in false-triggering of the input. This problem is frequently observed in devices with high input impedance. In some cases, this can cause momentary missing pulses and can even cause input circuitry to latch-up in some alternate technologies. The ACPL-x6xL optocoupler family does not have an input latch-up issue. Even at very high CMR levels, such as those experienced in end equipment level tests (for example IEC61000-4-4), the ACPL-x6xL series is immune to latch-up because of the simple diode structure of the LED. In some cases, achieving the rated data sheet CMR performance level is not possible in an application. This is often because of the practical requirement to actually connect the isolator input to the output of a dynamically changing signal rather than statically tying the input to V DD or GND. To address achievable end application performance on data sheets, the ACPL-x6xL optocouplers include an additional typical performance specification for dynamic CMR in the electrical parameter table. The dynamic CMR specification indicates the typical achievable CMR performance as the input is toggled on or off during a CMR transient. The logic output of the ACPL-x6xL optocouplers is mainly controlled by LED current level, and since the LED current features very fast rise and fall times, dynamic noise immunity is essentially the same as static noise immunity. Despite their immunity to input latch-up and the excellent dynamic CMR immunity, ACPL-x6xL optocoupler devices are still potentially vulnerable to misoperation caused by turning the LED either on or off during a CMR disturbance. If the LED status could be ensured by design, the overall application level CMR performance would be that of the photodetector. To benefit from the inherently high CMR capabilities of the ACPL-x6xL family, take the following precautions when operating the LED at the application level. In particular, ensure that the LED stays either on or off during a CMR transient. Some common design techniques to accomplish this include the following: Keep the LED On: 1. Overdrive the LED with a higher-than-required forward current. Keep the LED Off: 1. Reverse bias the LED during the off state. 2. Minimize the off-state impedance across the anode and cathode of the LED during the off state. All of these methods allow the full CMR capability of the ACPL-x6xL family to be achieved, but they do have practical implementation issues or require a compromise on power consumption. There is, however, an effective method to meet the goal of maintaining the LED status during a CMR event with no other design compromises other than a single added resistor. This CMR optimization takes advantage of the differential connection to the LED. By ensuring the common-mode impedances at both the cathode and anode of the LED are equal, the CMR transient on the LED is effectively canceled. As shown in Figure 11, this is easily achieved by using two, instead of one, input bias resistors.
  • 16 - ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Figure 12 AC Equivalent Circuit of ACPL-x6xL For ACPL-M61L/W61L: VDD = 3.3V: R1 = 510Ω ± 1%, R2 = 360Ω ± 1% VDD = 5.0V: R1 = 1000Ω ± 1%, R2 = 680Ω ± 1% RT = R1 + R2 R1/R2 = 1.5 For ACPL-064L/K64L: VDD = 3.3V: R1 = 430Ω ± 1%, R2 = 430Ω ± 1% VDD = 5.0V: R1 = 845Ω ± 1%, R2 = 845Ω ± 1% RT = R1 + R2 R1/R2 = 1 Table 1 Common-Mode Pulse Polarity and LED Current Transient dVCM/dt Value Resultant ILP Flow Direction Resultant ILN Flow Direction If |ILP| < |ILN|, LED current IF is momentarily: If |ILP| > |ILN|, LED current IF is momentarily: Positive (> 0) Away from the LED anode through CLA Away from the LED cathode through C LC Increased Decreased Negative (< 0) Toward the LED anode through CLA Toward the LED cathode through C LC Decreased Increased GND2 VO VDD2 0.1μF Shield ILN ILP CLC CLA
  • 17 - ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Slew-Rate Controlled Outputs Feature Typically, the output slew rate (rise and fall time) varies with the output load, as more time is required to charge up the higher load. The propagation delay and the PWD both increase with the load capacitance. This will be an issue especially in parallel communication because different communication lines will have different load capacitances. However, optocoupler ACPL-x6xL has a built-in slew-rate controlled feature to ensure that the output slew rate remains stable across wide load capacitance. Figure 13 shows the rise time and fall time for ACPL-x6xL at 3.3V and 5V. Figure 13 Rise and Fall Time of ACPL-x6xL across Wide-Load Capacitance Rise Time (VDD = 5.0V) Temperature (°C) Rise Time (nS) 10 pF 15 pF 22 pF 33 pF 47 pF 100 pF Temperature (°C) Fall Time (nS) Fall Time (VDD = 5.0V) 10 pF 15 pF 22 pF 33 pF 47 pF 100 pF Rise Time (VDD = 3.3V) Temperature (°C) Rise Time (nS) 10 pF 15 pF 22 pF 33 pF 47 pF 100 pF Fall Time (VDD = 3.3V) –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 Temperature (°C) Rise Time (nS) 10 pF 15 pF 22 pF 33 pF 47 pF 100 pF

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