ACNT-H61L BOARDCOM | Alldatasheet

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Technical content

Features

 Low IDD power supply consumption: 2 mA max.  Input current capability: 4.5 mA min.  Package: 15-mm stretched SO-8.  20 kV/µs minimum common-mode rejection (CMR) at VCM = 1000 V.  High speed: 10 MBd min.  Guaranteed AC and DC performance over wide temperature range: –40°C to +105°C.  Comparative tracking index, CTI: 600V (Material Group I) - ACNT-H61LC  Safety approval: – UL 1577 recognized: 7500 V rms for 1 minute – CSA approval – IEC/EN 60747-5-5 V IORM = 2262 Vpeak for reinforced insulation

Applications

 Communication Interface: RS-485, CAN bus  Digital isolation for A/D, D/A conversion  High-voltage power systems, e.g., 690V drives  Renewable energy inverters  Medical imaging and patient monitoring CAUTION! It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation that may be induced by ESD. The components featured in this data sheet are not to be used in military or aerospace applications or environments. The components are not AEC-Q100 qualified and not recommended for automotive applications. LED Output VO ON L OFF H Anode VDD GND Vo Shield NC NC NC Cathode ACNT-H61L, ACNT-H61LC Low Power 10-MBd Digital CMOS Optocoupler in 15-mm Stretched SO8 Package

ACNT-H61L, ACNT-H61LC Data Sheet Low Power 10-MBd Digital CMOS Optocoupler in 15-mm Stretched SO8 Package

Ordering Information

ACNT-H61L/H61LC is UL Recognized with 7500 Vrms for 1 minute per UL 1577. To order, choose a part number from the Part Number column and combine with the desired option from the Option column to form an order entry. Package Outline Drawing ACNT-H61L/H61LC Stretched SO-8 Package Solder Reflow Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-halide flux should be used. Regulatory Information The ACNT-H61L/H61LC is pending approval by the following organizations. Part Number Option RoHS Compliant Package Surface Mount Tape & Reel UL 1577 IEC/EN 60747-5-5 Quantity ACNT-H61L ACNT-H61LC -000E 15-mm Stretched SO8 X X X 80 per tube - 5 0 0 E XXXX 1 000 per reel IEC/EN 60747-5-5 UL Approval under UL 1577, component recognition program up to VISO = 7500 VRMS File E55361. CSA Approval under CSA Component Acceptance Notice #5, File CA 88324. 6.248 ±0.127 0.246 ±0.005 0.457 ±0.100 0.018 ±0.004 1.270 0.05 BSC 16.61 ±0.25 0.654 ±0.010 0.254 ±0.050 0.010 ±0.002 15.01 0.591 0.20 ±0.10 0.008 ± 0.004 7° 8° Nom 13.600 ± 0.127 0.535 ± 0.005 0.635 0.025 Min 3.607 ± 0.127 0.142 ± 0.005 7° 17.857 0.703 Ref 0.630 0.025 1.905 0.075 Ref14.047 0.553 Land Pattern Recommendation Dimensions in mm [inch] Maximum Mold Flash on each side is 0.127 mm [0.005 inch] Note: Floating Lead Protusion is 0.15 mm [0.006 inch] Max if applicable NNNN NNNN Ɣ YYWW EEE Device Part Number Date Code Lead Free Lot ID

ACNT-H61L, ACNT-H61LC Data Sheet Low Power 10-MBd Digital CMOS Optocoupler in 15-mm Stretched SO8 Package Insulation and Safety Related Specifications IEC/EN 60747-5-5 Insulation Characteristicsa Parameter Symbol ACNT-H61L ACNT-H61LC Unit Conditions Minimum External Air Gap (External Clearance) L(101) 14.2 14.2 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (External Creepage) L(102) 15 15 mm Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic Gap (Internal Clearance) 0.5 0.5 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. Tracking Resistance (Comparative Tracking Index) CTI >300 600 V DIN IEC 112/VDE 0303 Part 1. Isolation Group IIIa I Material Grou p (DIN VDE 0110, 1/89, Table 1.) Description Symbol Characteristic Unit Installation Classification per DIN VDE 0110/39, Table 1 For Rated Mains Voltage ≤ 600 Vrms For Rated Mains Voltage ≤ 1000 Vrms I – IV I – IV Climatic Classification 40/105/21 Pollution Degree (DIN VDE 0110/39) 2 Maximum Working Insulation Voltage V IORM 2262 V peak Input to Output Test Voltage, Method ba VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC a. Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles. VPR 4241 V peak Input to Output Test Voltage, Method aa VIORM x 1.6 = VPR, Type and Sample Test, tm=10 sec, Partial Discharge < 5 pC VPR 3619 V peak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 12000 V peak Safety-limiting Values – Maximum Values Allowed in the Event of a Failure Case Temperature Input Current Output Power T S IS, INPUT PS, OUTPUT 150 400 1000 mA mW Insulation Resistance at TS, VIO = 500V R S >109 Ω

ACNT-H61L, ACNT-H61LC Data Sheet Low Power 10-MBd Digital CMOS Optocoupler in 15-mm Stretched SO8 Package Absolute Maximum Ratings Recommended Operating Conditions Parameter Symbol Min. Max. Units Conditions Storage Temperature T S –55 125 °C — Operating Temperature T A –40 105 °C — Reverse Input Voltage V R —5V — Supply Voltage V DD —6 . 5V — Average Forward Input Current I F —1 0 m A — Peak Forward Input Current I F(TRAN) —1A < 1 μs Pulse Width, <300 pulses per second —8 0 m A < 1 μs Pulse Width, <10% Duty Cycle Output Current I O —1 0 m A — Output Voltage V O –0.5 V DD + 0.5 V — Input Power Dissipation P I —2 0 m W — Output Power Dissipation P O —2 2 m W — Lead Solder Temperature T LS 260°C for 10 seconds, 1.6 mm below seating plane Solder Reflow Temperature Profile — See Solder Reflow Profile. Parameter Symbol Min. Max. Units Operating Temperature T A –40 105 °C Input Current, Low Level I FL 02 5 0 μA Input Current, High Level I FH 4.5 8 mA Power Supply Voltage V DD 2.7 5.5 V Forward Input Voltage V F (OFF) —0 . 8 V

ACNT-H61L, ACNT-H61LC Data Sheet Low Power 10-MBd Digital CMOS Optocoupler in 15-mm Stretched SO8 Package Electrical Specifications (DC) Over recommended temperature (TA = –40°C to +105°C), supply voltage (2.7V ≤ VDD ≤ 5.5V). All typical specifications are at VDD = 5V, TA = 25°C. Parameter Symbol Min. Typ. Max. Units Test Conditions Figure Input Forward Voltage V F 1.20 1.38 1.85 V I F = 7 mA 2, 3 Input Reverse Breakdown Voltage BVR 7— —V I R = 10 µA Logic High Output Voltage V OH VDD – 0.1 V DD —V I F = 0 mA, VI = 0V, IO = –20 µA VDD – 1.0 V DD —V I F = 0 mA, VI = 0V, IO = –3.2 mA Logic Low Output Voltage V OL — 0.02 0.1 V I F = 7 mA, VI = 5V/3.3V, IO = 20 µA —0 . 2 0 . 4V I F = 7 mA, VI = 5V/3.3V, IO = 3.2 mA Input Threshold Current I TH —0 . 7 3 . 8 m A — 4 Logic Low Output Supply Current I DDL —12 m A — 5 Logic High Output Supply Current IDDH —12 m A — 6 Input Capacitance C IN — 20 — pF f = 1 MHz, V F = 0V Input Diode Temperature Coefficient ΔVF/ΔTA —– 1 . 5 — m V / ° C I F = 7 mA

ACNT-H61L, ACNT-H61LC Data Sheet Low Power 10-MBd Digital CMOS Optocoupler in 15-mm Stretched SO8 Package Switching Specifications (AC) Over recommended temperature (TA = –40°C to +105°C), supply voltage (2.7V ≤ VDD ≤ 5.5V). All typical specifications are at VDD = 5V, TA = 25°C. Package Characteristics All typical at TA = 25°C. Parameter Symbol Min. Typ. Max. Units Test Conditions Propagation Delay Time to Logic Low Outputa a. t PHL propagation delay is measured from the 50% (Vin or IF) on the rising edge of the input pulse to the 50% VDD of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% (Vin or IF) on the falling edge of the input pulse to the 50% level of the rising edge of the VO signal. tPHL — 40 100 ns I F = 7 mA, VI = 3.3V/5V, CL= 15 pF, CMOS Signal Levels. Figures 7, 8, 9, 10 Propagation Delay Time to Logic High Outputa tPLH — 40 100 ns Pulse Width t PW 100 — — ns Pulse Width Distortionb b. PWD is defined as |t PHL – tPLH|. PWD — 5 40 ns Propagation Delay Skewc c. t PSK is equal to the magnitude of the worst-case difference in tPHL and/or tPLH that is seen between units at any given temperature within the recommended operating conditions. tPSK — — 40 ns Output Rise Time (10% to 90%) t R —1 0—n s Output Fall Time (90% to 10%) t F —1 0—n s Static Common-Mode Transient Immunity at Logic High Outputd d. CM H is the maximum tolerable rate of rise of the common-mode voltage to assure that the output remains in a high logic state. | CMH | 20 35 — kV/ μsV CM = 1000V, TA = 25°C, IF = 0 mA, VI = 0V, CL= 15 pF, CMOS Signal Levels Static Common-Mode Transient Immunity at Logic Low Outpute e. CM L is the maximum tolerable rate of fall of the common-mode voltage to assure that the output remains in a low logic state. | CML | 20 35 — kV/ μsV CM = 1000 V, TA = 25°C, IF = 7 mA, VI = 5V/3.3V, CL= 15 pF, CMOS Signal Levels Dynamic Common-Mode Transient Immunityf f. CMD is the maximum tolerable rate of the common-mode voltage during data transmission to assure that the absolute increase of the PWD is less than 10 ns. CMRD — 35 — kV/ μsV CM = 1000V, TA = 25°C, IF = 7 mA, VI = 5V/3.3V, 10-MBd data rate, the absolute increase of PWD <10 ns Parameter Symbol Min. Typ. Max. Units Test Conditions Input-Output Insulation V ISO 7500 — — Vrms RH < 50% for 1 min. T A = 25°C Input-Output Resistance R I-O — 1012 — Ω VI-O = 500V Input-Output Capacitance C I-O — 0.6 — pF f = 1 MHz, T A = 25°C

ACNT-H61L, ACNT-H61LC Data Sheet Low Power 10-MBd Digital CMOS Optocoupler in 15-mm Stretched SO8 Package Broadcom AV02-4677EN Bypassing and PC Board Layout The external components required for proper operation are the input limiting resistors and the output bypass capacitor. Capacitor values should be 0.1 µF and should be placed as close as possible to the power-supply pins of the optocoupler. Propagation Delay, Pulse-Width Distortion, and Propagation Delay Skew Propagation delay is a figure of merit that describes how quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 12). Figure 11: Recommended Printed Circuit Board Layout Pulse-width distortion (PWD) results when tPLH and tPHL differ in value. PWD is defined as the difference between tPLH and tPHL. This parameter determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD in the order of 20% to 30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-1, and so on). Propagation delay skew, t PSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it determines the maximum rate at which parallel data can be sent through the optocouplers. Anode Cathode VCMPulse Gen C = 0.1 PF Output Monitoring node VO GND OV (min.) VDD 0 V SWITCH AT A: I = 0 mAF SWITCH AT B: I = 7 mAF CMV HCM CM L OV (max.) CMV (PEAK) VO 2 7 XXX YWW IF GND1 VDD C = 0.1 PF GND2 VI RT = R1 + R2, R1/R2 ≈ 1.5 3.3V / 5V B IF VDD GND VO Shield A

ACNT-H61L, ACNT-H61LC Data Sheet Low Power 10-MBd Digital CMOS Optocoupler in 15-mm Stretched SO8 Package Table 2: Effects of Common-Mode Pulse Direction on Transient ILED If dVCM/dt Is: Then ILP Flows: And ILN Flows: LED IF Current Is Momentarily: LED IF Current Is Momentarily: Positive (>0) Away from LED anode through CLA Away from LED cathode through C LC Increased Decreased Negative (<0) Toward LED anode through CLA Toward LED cathode through C LC Decreased Increased

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