74ALVCH16821 PHILIPS | Alldatasheet

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Technical content

/C0109 /C0110 /C0114 74ALVCH16821 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) Product specification IC24 Data Handbook

1998 May 29

Philips Semiconductors Product specification 74ALVCH1682120-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

21998 May 29 853-2066 19467

FEATURES

  • Wide supply voltage range of 1.2V to 3.6V
  • Complies with JEDEC standard no. 8-1A
  • Current drive ± 24 mA at 3.0 V
  • CMOS low power consumption
  • Direct interface with TTL levels
  • MULTIBYTE TM flow-through standard pin-out architecture
  • Low inductance multiple VCC and ground pins for minimum noise and ground bounce
  • All data inputs have bus hold
  • Output drive capability 50Ω transmission lines @ 85°C

DESCRIPTION

The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE ) control gates. Each register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output. When nOE is LOW, the data in the register appears at the outputs. When nOE is HIGH, the outputs are in high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops. The 74ALVCH16821 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL /tPLH Propagation delay nCP to nQn VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF 2.6 2.5 ns C I Input capacitance 5.0 pF C Power dissipation capacitanceper buffer V = GND to VCC 1 Outputs enabled 33 pFC PD Pow er dissipation capacitance per buffer VI = GND to VCC 1 Outputs disabled 17 pF Fmax Maximum clock frequency VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF 250 350 MHz NOTE: 1. C PD is used to determine the dynamic power dissipation (PD in W): PD = CPD × VCC 2 × fi + (CL × VCC 2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC 2 × fo) = sum of outputs.

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 56-Pin Plastic SSOP Type III –40°C to +85°C 74ALVCH16821 DL ACH16821 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVCH16821 DGG ACH16821 DGG SOT364-1

Philips Semiconductors Product specification 74ALVCH1682120-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

1998 May 29 3

PIN NUMBER SYMBOL FUNCTION 48, 47, 45, 44, 43 1D0 - 1D9 Data inputs 36, 34, 33, 31, 30 2D0 - 2D9 Data in uts 2, 3, 5, 6, 8, 9, 10, 12, 13, 14 1Q0 - 1Q9 Data outputs 21, 23, 24, 26, 27 2Q0 - 2Q9 Data out uts 1, 28 1OE , 2OE Output enable inputs (active-Low) 56, 29 1CP, 2CP Clock pulse inputs (active rising edge) 4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V) 7, 22, 35, 50 VCC Positive supply voltage PIN CONFIGURATION 28 29 561OE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 GND VCC GND 1Q7 1Q8 1Q9 2Q0 2Q1 2Q2 GND 2Q3 2Q4 2Q5 VCC 2Q6 2Q7 GND 2Q8 2Q9 2OE 1CP 1D0 1D1 GND 1D2 1D3 V CC 1D4 1D5 1D6 GND 1D7 1D8 1D9 2D0 2D1 2D2 GND 2D3 2D4 2D5 V CC 2D6 2D7 GND 2D8 2D9 2CP SH00001 FUNCTION TABLE INPUTS OUTPUT nOE CP Dx Q L ↑ L L L ↑ H H L X Q0 H X X Z H = HIGH voltage level L = LOW voltage level X = Don’t care Z = High impedance OFF state ↑ = LOW to HIGH clock transition = Not a LOW-to-HIGH clock transition LOGIC SYMBOL 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1D8 1D9 1Q8 1Q9 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2D8 2D9 2Q8 2Q9 1CP1OE 2CP2OE 561 2928 SH00127

Philips Semiconductors Product specification 74ALVCH1682120-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

1998 May 29 4

LOGIC SYMBOL (IEEE/IEC) EN2 2 ∇ EN4 4 ∇3D SH00003 1OE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 2OE 1CP 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 2CP LOGIC DIAGRAM CP Q D nD0 nQ0 nCP nOE CP Q D nD1 nQ1 CP Q D nD2 nQ2 CP Q D nD3 nQ3 CP Q D nD4 nQ4 CP Q D nD5 nQ5 CP Q D nD6 nQ6 CP Q D nD7 nQ7 CP Q D nD8 nQ8 CP Q D nD9 nQ9 SH00004

Philips Semiconductors Product specification 74ALVCH1682120-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

1998 May 29 5

RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS LIMITS UNITSYMBOL PARAMETER CONDITIONS MIN MAX UNIT VCC DC supply voltage 2.5V range (for max. speed performance @ 30 pF output load) 2.3 2.7 VVCC DC supply voltage 3.3V range (for max. speed performance @ 50 pF output load) 3.0 3.6 V VI DC Input voltage range 0 VCC V VO DC output voltage range 0 VCC V Tamb Operating free-air temperature range –40 +85 °C tr, tf Input rise and fall times VCC = 2.3 to 3.0V VCC = 3.0 to 3.6V ns/V ABSOLUTE MAXIMUM RATINGS In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL PARAMETER CONDITIONS RATING UNIT VCC DC supply voltage –0.5 to +4.6 V IIK DC input diode current VI 0 –50 mA VI DC input voltage For control pins1 –0.5 to +4.6 VVI DC in ut voltage For data inputs1 –0.5 to VCC +0.5 V IOK DC output diode current VO VCC or VO 0 50 mA VO DC output voltage Note 1 –0.5 to VCC +0.5 V IO DC output source or sink currentVO = 0 to VCC 50 mA IGND , ICC DC V CC or GND current 100 mA Tstg Storage temperature range –65 to +150 °C PTOT Power dissipation per package –plastic medium-shrink (SSOP) –plastic thin-medium-shrink (TSSOP) For temperature range: –40 to +125 °C above +55°C derate linearly with 11.3 mW/K above +55°C derate linearly with 8 mW/K 850 600 mW NOTE: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

Philips Semiconductors Product specification 74ALVCH1682120-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

1998 May 29 6

DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT MIN TYP 1 MAX V HIGH level Input voltage VCC = 2.3 to 2.7V 1.7 1.2 VVIH HIGH level Input voltage VCC = 2.7 to 3.6V 2.0 1.5 V V LOW level Input voltage VCC = 2.3 to 2.7V 1.2 0.7 VVIL LOW level Input voltage VCC = 2.7 to 3.6V 1.5 0.8 V VCC =23t o36 V;V =V or V ;IO = 100 µA VCC 02 VCCVCC = 2.3 to 3.6V; VI = VIH or VIL; IO = –100µA VCC /C00420.2 VCC VCC = 2.3V; VI = VIH or VIL; IO = –6mA VCC /C00420.3 VCC /C00420.08 VO HIGH level output voltage VCC = 2.3V; VI = VIH or VIL; IO = –12mA VCC /C00420.6 VCC /C00420.26 VVOH HIGH level output voltage VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC /C00420.5 VCC /C00420.14 V VCC = 3.0V; VI = VIH or VIL; IO = –12mA VCC /C00420.6 VCC /C00420.09 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC /C00421.0 VCC /C00420.28 V =23t o36 V; V =V or V ;I = 100µA GND 02 0 VVCC = 2.3 to 3.6V; VI = VIH or VIL; IO = 100µA GND 0.20 V VCC = 2.3V; VI = VIH or VIL; IO = 6mA 0.07 0.40 V VOL LOW level output voltage VCC = 2.3V; VI = VIH or VIL; IO = 12mA 0.15 0.70 VCC = 2.7V; VI = VIH or VIL; IO = 12mA 0.14 0.40 V VCC = 3.0V; VI = VIH or VIL; IO = 24mA 0.27 0.55 VCC =23t o36 V;II Input leakage current VCC = 2.3 to 3.6V; V V or GND 0.1 5 µAI g VI = VCC or GND µ IOZ 3-State output OFF-state currentVCC = 2.7 to 3.6V; VI = VIH or VIL; VO = VCC or GND 0.1 10 µA ICC Quiescent supply current VCC = 2.3 to 3.6V; VI = VCC or GND; IO = 0 0.2 40 µA ΔICC Additional quiescent supply currentVCC = 2.3V to 3.6V; VI = VCC – 0.6V; IO = 0 150 750 µA I Bus hold LOW sustaining current VCC = 2.3V; VI = 0.7V2 45 – µAIBHL Bus hold LOW sustaining current VCC = 3.0V; VI = 0.8V2 75 150 µA I Bus hold HIGH sustaining current VCC = 2.3V; VI = 1.7V2 –45 µAIBHH Bus hold HIGH sustaining current VCC = 3.0V; VI = 2.0V2 –75 –175 µA IBHLO Bus hold LOW overdrive currentVCC = 3.6V2 500 µA IBHHO Bus hold HIGH overdrive currentVCC = 3.6V2 –500 µA NOTES: 1. All typical values are at Tamb = 25°C. 2. Valid for data inputs of bus hold parts.

Philips Semiconductors Product specification 74ALVCH1682120-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

1998 May 29 7

AC CHARACTERISTICS FOR V CC = 2.3V TO 2.7V RANGE GND = 0V; tr = tf ≤ 2.0ns; CL = 30pF LIMITS SYMBOL PARAMETER WAVEFORM VCC = 2.5V ± 0.2V UNIT MIN TYP 1 MAX tPLH /tPHL Propagation delay nCP to nQn 1, 4 1.0 2.6 5.8 ns tPZH /tPZL 3-State output enable time nOE n to nQn 2, 4 1.0 2.8 6.6 ns tPHZ /tPLZ 3-State output disable time nOE n to nQn 2, 4 1.0 2.2 5.7 ns tW nCP pulse width HIGH or LOW 3, 4 3.0 1.8 ns tSU Set up time nDn to nCP 3, 4 1.4 0.3 ns th Hold time nDn to nCP 3, 4 0.4 0.0 ns Fmax Maximum clock pulse frequency 1, 4 150 250 MHz NOTE: 1. All typical values are at VCC = 2.5V and Tamb = 25°C. AC CHARACTERISTICS FOR V CC = 3.0V TO 3.6V RANGE AND VCC = 2.7V GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3 ± 0.3V VCC = 2.7V UNIT MIN TYP 1 MAX MIN TYP 1 MAX tPHL /tPLH Propagation delay nCP to nQn tPZH /tPZL 3-State output enable time nOE n to nQn tPHZ /tPLZ 3-State output disable time nOE n to nQn tW nCP pulse width HIGH or LOW 3, 4 3.3 0.2 3.3 1.7 ns tSU Set up time nDn to nCP 3, 4 1.0 0.2 1.2 0.3 ns th Hold time nDn to nCP 3, 4 0.8 0.4 0.6 –0.3 ns Fmax Maximum clock pulse frequency 1, 4 150 350 150 300 MHz NOTES: 1. All typical values are at Tamb = 25°C.

Philips Semiconductors Product specification 74ALVCH1682120-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

1998 May 29 8

VCC = 2.3 TO 2.7 V RANGE 1. VM = 0.5 V 2. VX = VOL + 0.15V 3. VY = VOH – 0.15V 4. VI = VCC 5. VOL and VOH are the typical output voltage drop that occur with the output load. VCC = 3.0 TO 3.6 V RANGE AND VCC = 2.7 V 1. VM = 1.5 V 2. VX = VOL + 0.3V 3. VY = VOH – 0.3V 4. VI = 2.7 V 5. VOL and VOH are the typical output voltage drop that occur with the output load. VMnCP INPUT nQ n OUTPUT tw tPHL VM tPLH 1/fMAX VM VOH VOL SH00128 VI GND Waveform 1. The input (nCP) to output propagation delays. tPLZ tPZL VI nOE INPUT GND VCC OUTPUT LOW-to-OFF OFF-to-LOW VOL VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs enabled outputs disabled tPHZ VM VM VM tPZH VX VY SW00308 Waveform 2. The 3-State enable and disable times. nQ n OUTPUT VM VMnD n INPUT SH00129 nCP INPUT VM GND VI GND VI VOL VOH tsu tsu th th Waveform 3. Set up and hold times. TEST CIRCUIT SWITCH POSITION PULSE GENERATOR R T VI D.U.T. VO C L VCC R L = 500 Ω Test Circuit for switching times Open GND DEFINITIONS VCC VI < 2.7V V CC TEST S 1 tPLH/tPHL Open R L = Load resistor C L = Load capacitance includes jig and probe capacitance R T = Termination resistance should be equal to ZOUT of pulse generators. 2 /C0060 VCCtPLZ/tPZL 2.7V2.7–3.6V tPHZ/tPZH GND R L = 500 Ω 2 * VCC SV00906 Waveform 4. Load circuitry for switching times

Philips Semiconductors Product specification 74ALVCH1682120-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

1998 May 29 9

SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1

Philips Semiconductors Product specification 74ALVCH1682120-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

1998 May 29 10

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1

Philips Semiconductors Product specification 74ALVCH1682120-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

1998 May 29 11

Philips Semiconductors Product specification 74ALVCH1682120-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

1998 May 29 12

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Date of release: 05-96 Document order number: 9397-750-04553 /C0109 /C0110 /C0114 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.