AC9272F | DigiCamel IC Datasheet

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AC9272F TOSHIBA | Alldatasheet

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TENTATIVE TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC9271F, TC9271N TC9271F and TC9271N are modulation / transmission ICs TC9271F for digital audio interface based on EIAJ CP-1201 standards. FEATURES SQ canst Ett Vie @ Based on EIAJ CP-1201 standards. © Data input format selectable between MSB first or LSB SOP28-P-450-1.27 first. Data length is 24bit max. 1C9271N @ Two modes : 2 channel and 4 channel @ Channel status data easily set with external pins. The data can be input serially by microcontroller. @ User data can be transmitted. @ Double-speed operation @ Selectable LRCK polarity SDIP28-P-400-1.78 @ Two packages : 28-pin flat package, 28-pin shrink DIP Weight ‘Wo pi ges : pl Pp ge, pl ul SOP28-P-450-1.27 : 0.8g (Typ.) package SDIP28-P-400-1.78 : 2.2g (Typ.) 9809 10EBA2 ©@ TOSHIBA is continually working to improve the quality and the reliability of its products, Nevertheless, semiconductor devices in general can malfunction or ‘all due to their inherent electrical sensivty and vulnerability to physical stress. ts the responsibilty of the buyer, when tiizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. @ The products described in this document are subject to the foreign exchange and foreign trade laws. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others e The information contained herein is subject to change without notice. 1999-03-19 1/17

BCK BS (24 Ml FR32 pata 6 23 crG3 voy 7 22 cree EMPH #8 21M CTG1 cory 9 20 fa sz si 10 19st 5211 7 cxs 12 ahem xig3 16 fu 002 Vss 14 15 [9 D01 BLOCK DIAGRAM , & 3 5 8 8 x 6 38 G6 GG isan oxon vssQ CLOCK GENERATION SERIAL Orcrat ss CIRCUIT INTERFACE f) ursC) C)cka2 arr urck C) © CATEGORY CODE cult usa C) BL-PHASE MARK w parity GeneraTion | | SVRHASE MARK Ors: ORCUTT CIRCUIT O—-O—-O-O O O 5 2 8 8 z 8 1999-03-19 2/17

[ow ne [swooc]vo] —__ancrow dC [1 [Stock | © [Block top positon output pm SSCS SSCS [2 [usba | 1 [User bit data input pin SSCS SSCS

3 LRS LRCK polarity selection pin With pull-up resistor

27 CKA2 Clock accuracy setting pin 2 Prohibits output With pull-up resistor

pL [TPP iee serena pehgricet | PP ORO (Note) In the above pin description, “2ch” indicates 2 channel mode; “4ch", 4 channel mode. “P” indicates parallel mode; “S”, serial mode. For mode settings, use FS1 (pin 10) and FS2 (pin 11). 1999-03-19 3/17

Internal mode setting 1-1. 2ch mode and 4ch mode setting To switch between 2ch mode and 4ch mode, use both the M1 and M2 pins. The 4ch mode is further divided into two modes. In one mode, data are output from two channels from both output pins, DO1 and DO2. In the other mode, data are output from four channels from one output pin (DO1 output =DO2 output). Two modes are also supported for inputting data. In the first mode, two channels of data are input from two input pins, DATA and VLDY. In the second mode, four channels of data are input from one input pin. Table 1 2 Channel and 4 Channel Mode Setting MODE SETTING INPUT SIGNAL OUTPUT SIGNAL Comment | v2 PIN | M1 PIN DO2 PIN | DO1 PIN | Pot tf tek [ ek | dim | valid [ int | bint | ach mode | pte [ek | Bint [ini | int pw [tf trek [ek | dint | Ding | Bint +2 | Bint —————*Y [a | #]Frek [ek [Bint +2 [-waek[ dint? [dinte2 > +d (Note) Adding validity flag A validity flag can be added in 2 channel mode. However, in 4 channel mode, the flag is fixed to low, as VLDY (pin 7) functions as a data or clock input pin in this mode. The signals in Table 1 are as follows. Lrck : Left channel and right channel selection clock Beck : Bit clock Frek : Frame clock (4 channel mode) Valid : Validity flag Wdck : Word clock (4 channel mode) Din1, Din2 : 2 channel multiplexed input data Din1+2 : 4 channel multiplexed input data Dit1, Dit2 : 2 channel multiplexed output data Dit1 +2 : 4 channel multiplexed output data 1999-03-19 4/17

2-1-2. Category code setting ; The category code is set using pins CTG1~3. The category bits shown in Table 5 as “L” can be freely set using the LBIT pin. For details, refer to the EIAJ CP-1201 standards. Table 5 Category Code Setting AATEGORY | 0 [General format [000 00000 } Digital mixer [010 01001 } Sample rate converter [010 1100L ] | 0 [Digital sampler [010 0010L J | 1 [ADC (no copy right) [011 O000L ] 1 | 0 [ADC (copy right) [011 01001 } | 0 [Synthesizer [101 0000L J | 1 [Microphone [101 1000L ] 2-1-3. Channel number setting ; In 2 channel mode, the channel number is added automatically. In 4 channel mode, all the bits are fixed to 0. Table 6 shows the specific details. Table 6 Channel Number Addition Correspondence [PIN NAME | CHANNEL NUMBER | m2 [| m1 | LRCK LRS =H LRS=L Tt Trooo] | 10100) _| [0100] [1000] : [1000] | 0700) fo100) | {1000 [0000] 1999-03-19 10/17

2-1-4. Sampling frequency setting ; Pins FS1 and FS2 are used for setting the sampling frequency. Table 7 Sampling Frequency Setting PIN INPUT SETTING DATA SETTING MODE SAMPLING FREQUENCY [TS24-27] (PINS CTG1~3, LBIT, CKA1~2) 44.1kHz [0000] [0700] Parallel mode 32kHz [1100] Setting by serial data transfer (Note) When FS1=high and FS2=low, serial mode is set. Thus, the mode becomes momentarily serial mode when the sampling frequency switches, momentarily disturbing clocks and data. 2-1-5. Clock accuracy bit setting ; Use the CKA1 and CKA2 pins to set the clock accuracy. The following describes the modes. (a) Standard mode (level II) ; When setting to output disable mode, change CKA1 and CKA2 from low to high. (b) Variable pitch mode (level Ill) ; When setting to output disable mode, change CKA1 only from low to high and keep CKA2 high. (c) Accuracy mode (level I) ; When setting to output disable mode, change CKA2 only from low to high and keep CKA1 high. Table 8 Clock Accuracy Setting PIN INPUT SETTING DATA CLOCK ACCURACY T1528, 201 DO1, DO2 OUTPUT STATUS rit t | teen | fo) _| pou fT a ft tevelim ft fo) Normal output PH of t fT tevett Tt DO1 and DO2 output fixed to low (output disable mode) (Note) When (CKA1, CKA2) =(H, H), output disable mode for digital data is entered, and DO1 and DO2 output is fixed to low. 1999-03-19 11/17

2-2. Serial mode This mode is used to serially set data for the channel status using a microcontroller. As Table 9 shows, in serial mode some pin functions differ from those in parallel mode. Table 9 Pin Functions in Serial Mode PIN NAME FUNCTION REMARKS EMPH EMPH flag input The flag is set based on the OR of EMPH and serial data. cory | —(Fuedtonig | SSCSCSC~CSC~SCSCS*S —_ (Fixed to high) . —“fFixed to low) Set for serial mode Fc CTG2_| clock input ta Latch pulse put SS LBIT 32/192bit switching | Set to low for 192bit mode Processing = Fined to high | SSSOSCSCSCC‘*Y DO1/2 output setting [Set to high to disable DO1 and DO2 pin output. (Note 1) As channel status data, the EMPH flag uses the OR of the parallel data and serial data. (Note 2) The channel number (TIME SLOT 20 and 21 in Figure 5) is automatically set. (Effective only in 2 channel mode. (M2 pin =low)) (Note 3) The serial setting register consists of 32bit. To reset (clear) this register at power on, set to parallel mode. That is, fixing FS2 to low, set the FS1 pin to low at power on then to high. 9999-03-19 12/17

MAXIMUM RATINGS (Ta = 25°C) ITEM SYMBOL RATING UNIT Power Supply Voltage —0.3~7.0 =O3—Vpp +03 pve oon PR >of — at Operating Temperature = 35~85 Storage Temperature =55~150 ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Ta = 25°C, Vpp =5V) DC characteristics TEST ITEM SYMBOL | CiR- TEST CONDITION TYP. | MAX. | UNIT CUIT Operating Power Supply _ o, Voltage Vpp Ta = -35~85°C 5.0 Vv . XI = 16.9MHz recone | we [= SSE, f= = ela VoD cd Voltage Vpb v me * ee cd Output ["H™ Level | ton | — | 3), Von=45V [— [= isl, Current [U7 Level | tor | — | 3), Vo.=05V [30 | — | — | Pull-up Resistance | _rup[—| (aS ‘| TO | — | KY (*1) All input pins (*2) All input pins other than (*4) (*3) All output pins (*4) All pins with pull-up resistor AC characteristics TEST ITEM SYMBOL | CIR- TEST CONDITION TYP. | MAX. | UNIT CUIT Operating Frequency | for | — | 75 | 168 | 400] we | input TRCK duty Gle =50% [30.0 [44.1 [100.0_| ke | nput Frequency Tack | ~ |BCK duty acle =50% [ose [rat | 640 | wie | peeing Time __}_tu_| _ [Pins trex ack, pata, and xt | =f — {| 5 = ano, Falling Time (10~90%4) [=T= Ts] ,, Delay Time t BCK falling edge y d SLRCK, DATA 1999-03-19 14/17

(1) Clock and data output timings TEST ITEM SYMBOL | cIR- TEST CONDITION TYP. | MAX. | UNIT CUIT Pins BLOCK, DOT, Doz, and | — | — | 20 | Output Falling Time FR32_(10~90%) [= |=] 20 | (2) Microcontroller interface timing (in serial mode) TEST ITEM SYMBOL | CiR- TEST CONDITION TYP. | MAX. | UNIT CUIT Hold Time [tip | — [eter serea [os | — | — | Delay Time ta [= lererscres Los [—T— | (*5) In 192bit serial input mode, set th>1,s. (*6) Input data in sync with the clock falling edge. Data are loaded internally at the clock rising edge. FR32 twe cre3 (Latch Pulse) tw | twe to (Clock) th cTG1 os ] (Data) tHLD 1999-03-19 15/17

SOP28-P-450-1.27 Unit : mm 28 15 ; HHHEEPEBEPREPe 2 p | : | si u 14 19.0MAX 18.5+0.2 po N |: i Fe ToT) s 3 Lesa Z 8 70. x S 1,010.2 Weight : 0.8g (Typ.) 1999-03-19 16/17

SDIP28-P-400-1.78 Unit : mm 28 15 7 Oommen ° N ) 3 ° 33 | 3 1 14 26.1MAX 25.640.2 po nen (1 HUH ORO URE OU Es) os z 2 —o o Weight : 2.2g (Typ.) 1999-03-19 17/17

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AC9272F specifications and overview.

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CMOS DIGITAL INTEGRATED CIRCUIT

Description

CMOS DIGITAL INTEGRATED CIRCUIT

Source title AC9272F Datasheet(PDF) - Toshiba Semiconductor

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