AC74HC40105AP

AC74HC40105AP TOSHIBA | Alldatasheet

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TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC40105AP, TC74HC40105AF

4 Bitx16 Word FIFO REGISTER

The TC74HC40105A is a high speed CMOS 4bitx16word mS, first - in, first - out (FIFO) Strage Register fabricated with —s a) silicon gate C2MOS technology. NR maricialll It achieves the high speed operation while maintaining the eu SAY \\ que CMOS low power dissipation. vee The device is capable of handling 16 four-bit words and it is P (DIP16-P-300-2.54A) possible to handle the input and output data at different Weight : 1.00g (Typ.) shifting rates. When the DATA - IN - READY (DIR) is high, data is written _——™ into the registers by a low to high transition of the SHIFT 6 eel IN (SI) input. And when DATA - OUT - READY (DOR) is NGS high, data is read out of the registers by a high to low 1 transition of the SHIFT OUT (SO) input. F(SOP16-P-2001 27) If the MASTER RESET (MR) is high, the DIR goes high and Weight : 0.189 (Typ.) DOR goes low. The data in the internal registers are not PIN ASSIGNMENT changed but are declared invalid. The TC74HC40105A can be cascaded to form longer registers OE 1 16 Vec or wider words. — The DATA OUTPUTs (Qn) are 3 - State Outputs. When DIR 2 15 SO OUTPUT ENABLE (OE) is held high, the Qn’s are in high sl 3 14 DOR impedance state. Do 4 13 Qo All inputs are equipped with protection circuits against static D5 12 Q) discharge or transient excess voltage. Do 6 11 Q2 FEATURES: D3 7 10 Q3 High Speedsssssssssesssssssssssseeeeeeeeees fiyax = 25MHz(typ.) at Voc = 5V GND 8 9 MR «Low Power Dissipation +--+ Igo = 4A(Max.) at Ta = 25°C eHigh Noise Immunity--++++-+-- Vii = Vu =28% Voc (Min.) (TOP VIEW)

15 LSTTL Loads For Q0~ Q3 IEC_LOGIC SYMBOL

«Symmetrical Output Impedance--- llon|=loL=4mA(min.)For DIR,DOR lon] = lo. = 6MA(min.)For QO~ Q3 oe tSyenc hiro t6xa 2 bir «Balanced Propagation Delays---tptH=tpHL I CI 12 + DOR «Wide Operating Voltage Range- Vcc (opr.) = 2V~6V maa , 50 Lape m 3. cr>0 {o3 L 325 4 1 Do [4p 6] Qo Bi ee Qi ee 2 D3 {Sq o*€3. 980508642 (© TOSHIBA is continually working to improve the quality and the reliability of its products, Nevertheless semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vuinerabiity to physical stress it is the responsibilty of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to, property..In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges. as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. 1998-08-18 1/8

ux —Do 7 of Y tog "4 twi ss -bo—D> on Ry U U >> fo} : Yi 1 [lf pee eee + Hf H ¢> bor JID UO WO: UO Uo i ot qr 6 qr 4 1 o 14~14, @ qr o 1 1 | VY VY Yt iV Y | | io4 ¥ 4 Yi} i iy Y i ot i oF x} <p- & iin Tr Tr: itt Tr l pee rs es | asa x ; of Word 1 Word 2 Word3 | 1 Word 15 Word 16 TIMING CHART MASTER RESET fe en Fe A oureut ENABLE = 200ns = 230n5 at Vec=4.5V at Voc =4.5V DATA INPUT DATA OUTPUT DATA IN | | (Dn) to 111401 0 010 11 0 01 tn °"" ZL VZEZ. UN KNOWN | 100 41010 INVALID Zs HIGH Impedance 980508EBA2" 3 The products described in this document are subject to foreign exchange and foreign trade laws. The Information contained herein is presented only as a guide for the applications of our products. No responsiblity is assumed by TOSHIBA CORPORATION for any iningerents of imlectual property or other nights ofthe thd pares which may result from 1 se. No icense s granted by implication or Otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others @ The information contained herein is subject to change without notice. 1998-08-18 2/8

SHIFT IN| SHIFT OUT CLOCK CLOCK (SI) (SO) 3 15 DATA-INPUT-READY MASTER 9 CONTROL (DIR) (MR) Locic 14 DATA-OUTPUT-READY (DOR)

1 OUTPUT ENABLE

(OE) po __4 13 Qo 5 12 D1 4x16 OUTPUT Qi DATA 6 DATA BUFFER " D2 REGISTER (3-STATE) Q2 D3 7 10 Q3 FUNCTIONAL DESCRIPTION 1) WRITING DATA Data can be written into the FIFO whenever DIR is high and a low to high transition occurs on the SI pin. DIR will toggle momentarily until the data has been transferred to the second word register. SI must be toggled before the next 4-bit word can be written. The first and subsequent words will automatically ripple to the output end of the device even if there is not a full 16 words of input data. When all 16 words are filled with data, DIR will go low and additional data cannot be written into the device. 2) READING DATA When a data word appears in the sixteenth data register (just before the output buffer), DOR goes high and, if OE is low, data can be output on the high to low transition of SO. The data remaining in the registers now ripples to the next higher word position opening the first word position for new data. DIR goes high and additional data can be written in. During the output of data, DOR toggles momentarily after each read. When the data registers become empty, DOR goes low and SO is ignored. 3) MASTER REST When a high is input to MR, the internal control logic is initialized. This causes DIR to go high and DOR to go low. The contents of the data registers are not changed, but are invalid and will be written over when the first word is loaded. 4) CASCADING The TC74HC40105A can be cascaded to form longer registers simply by connecting DOR of the first device to SI of the second and DIR of the second device to SO of the furst. Additional devices may be cascaded by repeating the above. Of course, the Qn outputs of the first device must be connected to the Dn inputs of the second. In this mode, an MR pulse must be applied after the supply voltage is turned on. For words wider than 4-bits, the DIR and DOR outputs from each FIFO must be ANDed respectively and the SI and SO inputs must each be paralleled. 1998-08-18 3/8

PARAMETER VALUE UNIT *500mW in the range of Ta= Supply Voltage Range ~ 40°C~65°C. From Ta=65°C DC Input Voltage Vin 0.5~Vec + 0.5 Vv = tomW/°C shall be applied until 300mW. [input Diode Current [ix [#20 | ma Output Diode Current | lox | #20 | ma_ DC Output (DIR,DOR)| | +25 mA Current (QO~Q3) | ‘out +35 DC Vec/ Ground Current [Power Dissipation | Pp | _S00(DIP/180(50R) = 65-150 RECOMMENDED OPERATING CONDITIONS Supply Voltage [vec [| ae | Input Voltage Output Voltage Operating Temperature —40~85 O~ 1000 (Vcc = 2.0V) Input Rise and Fall Time tr, tt O~ 500(Vcc =4.5V) O~ 400(Vcc = 6.0V) DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION Voc 7a=2s°¢ Ta=—40-85°C UNIT L065 [an [ rye. [wax | Min [ MAX. High - Level 2.0 | 1.50 1.50 2.0 0.50 0.50 Low - Level foe fm | LL | TERT NE 2.0] 1.9 2.0 19 lon = — 20nA 45) 44 45 44 High - Level 6.0 | 5.9 6.0 5.9 outpurvottage — | Yo" | | (Sox) [igis=S.ama | 68 | $38 | $80 | = | $08 | = | lo. = 20nA a3 00 Low - Level “ 6.0 0.0 outputvortase | “| | (Sox) [inssama_| €8| = | 8:38 | 838 | = | 833 | lo. =6 mA 45 0.17 | 0.26 0.33 3 - State Output Vin=ViworV, [inputteakage current | ty | Vin=VecorGND | 60 | — | — [#o1[ — [210] “A Viv=Vec or GND [eo] = [= [40 | = [40.0 | 1998-08-18 4/8

TIMING REQUIREMENTS ( Input t,=t;=6ns) Ta = -40-85°C TEST CONDITION a a Minimum Pulse Width twu 20 2 98 4.5 15 19 (sl) tw 6.0 13 16 Minimum Pulse Width tww 2.0 75 95 uss 4.5 15 19 (SO) tw 6.0 13 16 Minimum Pulse Width twu 20 73 98 4.5 15 19 (MR) two 6.0 13 16 Minimum Set—up Time t 20 (DATA-SI) 6.0 ini F 2.0 100 125 Minimum Hold Time th 45 20 5 (DATA~ SI) 6.0 7 21 7 2.0 50 65 Minimum Removal Time trem a5 10 1B (MR~SI) 6.0 9 u 2.0 24 Clock Frequency f 45 12 6.0 13 AC ELECTRICAL CHARACTERISTICS (C,=15pF, Vcc=5V, Ta=25°C, Input t,=t,=6ns) Output Transition Time thu 4 (DIR, DOR) trae Propagation Delay Time t 22 39 (SO, MR—DOR) pHL Propagation Delay Time t 242 (SO—DIR) ian Propagation Delay Time t 187 (SI-DOR) in Propagation Delay Time t 22 35 (SI—DIR) ian Propagation Delay Time toy 25 39 (MR-—DIR) tone 1998-08-18 5/8

AC ELECTRICAL CHARACTERISTICS (Input t, = t;=6ns) TEST CLV. Ta =-40~85°C PARAMETER srweot | Conomion [St] Yoh [an [ Tre. [wax [mn [Max [UN Output Transition Time trin 32 4 89 2 (Q0~Q3) tru 60 6 10 B Output Transition Time tru 32 4 R 8 (DIR, DOR) tri 6.0 7 13 16 F 7 2.0 84 | 225 280 Propagation Delay Time tone 50| 45 28 45 56 (SO, MR—DOR) 6.0 24 38 48 i i 2.0 798 | 2000 2500 Propaa a tous as 266 | ‘400 500 6.0 226 | 340 425 i i 2.0 624 | 1650 2060 Propagation Delay vime town 50| 4.5 208 | 330 412 i i 2.0 78 | 200 250 Propagation Delay Time ton 50| 45 6 40 50 (sI~DIR) 6.0 22 | 34 43 2.0 156 | 400 500 ; ; 45 52 80 100 Propagation Delay Time town 6.0 44 68 85 (SO-—Qn) ton 2.0 171 440 550 150] 4.5 57 88 110 6.0 48 75 94 2.0 612 | 1500 1875 45 204 | 300 375 Propagation Delay Time toy 6.0 173 255 319 (SI-Qn) tout 2.0 627 | 1540 7925 150] 4.5, 209 | 308 385 6.0 178_| 262 327 Propagation Delay Time ton 50 20 Ey 223 280 (MR~ DIR) tone 6.0 25 | 38 438 2.0 45 | 125 155 50| 4.5 15 25 31 F toa - 6.0 13 21 26 Output Enable time tn R, = 1k0 20 60 205 150] 4.5 20 41 6.0 7 35 t 2.0 32 | 125 155 Output Disable time oo RL =1k0 50] 4.5 16 25 31 HZ 6.0 14 21 26 1998-08-18 6/8

AC ELECTRICAL CHARACTERISTICS ( Input t, = t;=6ns) (Cont'd) TEST CL] Vec Ta = -40-85°C PARAMETER SMSO‘ | conorion_|(6F)| (V) [win | Tye. [Max | mi, Tmax, [UNIT 2.0 3 7 2.4 50} 4.5 15 22 12 . 6.0 18 26 14 Maximum Clock Frequency fuax 20] 2.6 2 MHz 45 13 10 6.0 15 12 i 2.0 Output Pulse on fn 50/45 ) 6.0 Output Pulse Width tu ze (DOR) tw) 6.0 Input Capacitance Pow Po TT to T= J 0 | Output Capacitance [cor [oT = Tt | = fT = = | [Power Dissipation Capacitance] Co | _Note(t) | = | 300 | — [| - | — | Note (1) Cpp is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: lec (opr) =Cpo * Vee * fin + lee 1998-08-18 7/8

DIP 16PIN OUTLINE DRAWING (DIP16-P-300-2.54A) Unit in mm 16 és) é i eS) 8 = a j : ~Y 19:75Max . 19.2540.2 (.9520.1 ama wl # | a Peres ne, pel 10.25) Weight : 1.00g (Typ.) SOP 16PIN (200mil BODY) OUTLINE DRAWING (SOP16-P-300-1.27) Unit in mm 16 c:) SHSaSHaRG [ 8) on 3 lt | 8 0.705TYP, 0.43101 ea TEG 10.8MAx 10.8:0.2 a x =f 2 3 3 ~ 3 L [osiee Weight : 0.18g (Typ.) 1998-08-18 8/8